arm64: Decode the ID_AA64MMFR4_EL1 register
No fields have been defined, but it has been documented in the Architecture Reference Manual. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D40894
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@ -140,6 +140,7 @@ struct cpu_desc {
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uint64_t id_aa64mmfr1;
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uint64_t id_aa64mmfr2;
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uint64_t id_aa64mmfr3;
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uint64_t id_aa64mmfr4;
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uint64_t id_aa64pfr0;
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uint64_t id_aa64pfr1;
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uint64_t id_aa64zfr0;
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@ -1297,6 +1298,12 @@ static const struct mrs_field id_aa64mmfr3_fields[] = {
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};
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/* ID_AA64MMFR4_EL1 */
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static const struct mrs_field id_aa64mmfr4_fields[] = {
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MRS_FIELD_END,
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};
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/* ID_AA64PFR0_EL1 */
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static const struct mrs_field_value id_aa64pfr0_csv3[] = {
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MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_NONE, ""),
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@ -1778,6 +1785,7 @@ static const struct mrs_user_reg user_regs[] = {
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USER_REG(ID_AA64MMFR1_EL1, id_aa64mmfr1),
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USER_REG(ID_AA64MMFR2_EL1, id_aa64mmfr2),
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USER_REG(ID_AA64MMFR3_EL1, id_aa64mmfr3),
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USER_REG(ID_AA64MMFR4_EL1, id_aa64mmfr4),
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USER_REG(ID_AA64PFR0_EL1, id_aa64pfr0),
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USER_REG(ID_AA64PFR1_EL1, id_aa64pfr1),
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@ -2509,6 +2517,11 @@ print_cpu_features(u_int cpu, struct cpu_desc *desc,
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print_id_register(sb, "Memory Model Features 3",
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desc->id_aa64mmfr3, id_aa64mmfr3_fields);
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/* AArch64 Memory Model Feature Register 4 */
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if (SHOULD_PRINT_REG(id_aa64mmfr4))
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print_id_register(sb, "Memory Model Features 4",
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desc->id_aa64mmfr4, id_aa64mmfr4_fields);
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/* AArch64 Debug Feature Register 0 */
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if (SHOULD_PRINT_REG(id_aa64dfr0))
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print_id_register(sb, "Debug Features 0",
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@ -2624,6 +2637,7 @@ identify_cpu(u_int cpu)
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desc->id_aa64mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1);
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desc->id_aa64mmfr2 = READ_SPECIALREG(id_aa64mmfr2_el1);
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desc->id_aa64mmfr3 = READ_SPECIALREG(id_aa64mmfr3_el1);
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desc->id_aa64mmfr4 = READ_SPECIALREG(id_aa64mmfr4_el1);
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desc->id_aa64pfr0 = READ_SPECIALREG(id_aa64pfr0_el1);
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desc->id_aa64pfr1 = READ_SPECIALREG(id_aa64pfr1_el1);
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@ -1094,6 +1094,14 @@
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#define ID_AA64MMFR3_Spec_FPACC_NONE (UL(0x0) << ID_AA64MMFR3_Spec_FPACC_SHIFT)
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#define ID_AA64MMFR3_Spec_FPACC_IMPL (UL(0x1) << ID_AA64MMFR3_Spec_FPACC_SHIFT)
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/* ID_AA64MMFR4_EL1 */
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#define ID_AA64MMFR4_EL1 MRS_REG(ID_AA64MMFR4_EL1)
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#define ID_AA64MMFR4_EL1_op0 3
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#define ID_AA64MMFR4_EL1_op1 0
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#define ID_AA64MMFR4_EL1_CRn 0
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#define ID_AA64MMFR4_EL1_CRm 7
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#define ID_AA64MMFR4_EL1_op2 4
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/* ID_AA64PFR0_EL1 */
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#define ID_AA64PFR0_EL1 MRS_REG(ID_AA64PFR0_EL1)
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#define ID_AA64PFR0_EL1_op0 0x3
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