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Fix creating the early arm64 level 2 blocks

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In 48ba9b2669 we switched from creating level 1 blocks to smaller
level 2 blocks when creating the early arm64 page tables. On issue
was that they had a different meaning for register x7. The former used
it to hold page table attributes, while the latter held just the memory
type. This caused these attributes to be incorrectly shifted.

Fix this by changing the meaning of x7 to hold the block attributes
and fix the only caller that used the old meaning.

Most hardware seems to have handled the bits being off however qemu
failed to boot as reserved bits that should be zero were being set and
qemu fails to clear these when translating from a virtual address to a
physical address.

Sponsored by:	Innovate UK
This commit is contained in:
Andrew Turner 2021-03-04 14:00:19 +00:00
parent f05b724ecb
commit 23553d6b94
1 changed files with 3 additions and 4 deletions
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7
sys/arm64/arm64/locore.S
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@ -430,7 +430,7 @@ common:
/* Create the kernel space L2 table */
mov x6, x26
mov x7, #VM_MEMATTR_WRITE_BACK
mov x7, #(ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK))
mov x8, #(KERNBASE & L2_BLOCK_MASK)
mov x9, x28
bl build_l2_block_pagetable
@ -600,7 +600,7 @@ LEND(link_l1_pagetable)
/*
* Builds count 2 MiB page table entry
* x6 = L2 table
* x7 = Type (0 = Device, 1 = Normal)
* x7 = Block attributes
* x8 = VA start
* x9 = PA start (trashed)
* x10 = Entry count (trashed)
@ -615,8 +615,7 @@ LENTRY(build_l2_block_pagetable)
and x11, x11, #Ln_ADDR_MASK
/* Build the L2 block entry */
lsl x12, x7, #2
orr x12, x12, #L2_BLOCK
orr x12, x7, #L2_BLOCK
orr x12, x12, #(ATTR_DEFAULT)
orr x12, x12, #(ATTR_S1_UXN)