Sync with Creative's 8010.h rev 1.51.
This commit is contained in:
David E. O'Brien
parent
a554deb2a8
commit
2511c244ad
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=124277
@ -1,4 +1,5 @@
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/*
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* Copyright (c) 2004 David O'Brien <obrien@FreeBSD.org>
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* Copyright (c) 1999 Cameron Grant <cg@freebsd.org>
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* All rights reserved.
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*
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@ -36,10 +37,16 @@ SND_DECLARE_FILE("$FreeBSD$");
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/* -------------------------------------------------------------------- */
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#define NUM_G 64 /* use all channels */
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#define WAVEOUT_MAXBUFSIZE 32768
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#define EMUPAGESIZE 4096 /* don't change */
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#define MAXPAGES (WAVEOUT_MAXBUFSIZE * NUM_G / EMUPAGESIZE)
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#define EMU10K1_PCI_ID 0x00021102
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#define EMU10K2_PCI_ID 0x00041102
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#define EMU_DEFAULT_BUFSZ 4096
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#define EMU_CHANS 4
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#define ENV_ON DCYSUSV_CHANNELENABLE_MASK
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#define ENV_OFF 0x00 /* XXX: should this be 1? */
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#undef EMUDEBUG
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struct emu_memblk {
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@ -1,7 +1,7 @@
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/*
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**********************************************************************
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* emu10k1.h, derived from 8010.h
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* Copyright 1999, 2000 Creative Labs, Inc.
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* Copyright 1999-2001 Creative Labs, Inc.
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*
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**********************************************************************
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*
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@ -11,6 +11,8 @@
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* November 2, 1999 Alan Cox Cleaned of 8bit chars, DOS
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* line endings
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* December 8, 1999 Jon Taylor Added lots of new register info
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* May 16, 2001 Daniel Bertrand Added unofficial DBG register info
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* Oct-Nov 2001 D.B. Added unofficial Audigy registers
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*
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**********************************************************************
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*
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@ -35,24 +37,20 @@
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*/
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#ifndef EMU10K1_H
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#define EMU10K1_H
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#ifndef _8010_H
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#define _8010_H
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/* ------------------- DEFINES -------------------- */
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/*
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#include <linux/types.h>
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*/
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#define EMUPAGESIZE 4096 /* don't change */
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#define MAXREQVOICES 8
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#define MAXPAGES (32768 * 64 / EMUPAGESIZE) /* WAVEOUT_MAXBUFSIZE * NUM_G / EMUPAGESIZE */
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#define RESERVED 0
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#define NUM_MIDI 16
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#define NUM_G 64 /* use all channels */
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#define NUM_FXSENDS 4
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// Driver version:
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#define MAJOR_VER 0
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#define MINOR_VER 20
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#define DRIVER_VERSION "0.20a"
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#define TMEMSIZE 256*1024
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#define TMEMSIZEREG 4
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#define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
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// Audigy specify registers are prefixed with 'A_'
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/************************************************************************************************/
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/* PCI function 0 registers, address = <val> + PCIBASE0 */
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@ -72,6 +70,11 @@
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#define IPR 0x08 /* Global interrupt pending register */
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/* Clear pending interrupts by writing a 1 to */
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/* the relevant bits and zero to the other bits */
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/* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
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#define A_IPR_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */
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#define A_IPR_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */
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#define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */
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#define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */
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#define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */
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@ -96,6 +99,10 @@
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/* IP is written with CL set, the bit in CLIPL */
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/* or CLIPH corresponding to the CIN value */
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/* written will be cleared. */
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#define A_IPR_MIDITRANSBUFEMPTY1 IPR_MIDITRANSBUFEMPTY /* MIDI UART transmit buffer empty */
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#define A_IPR_MIDIRECVBUFEMPTY1 IPR_MIDIRECVBUFEMPTY /* MIDI UART receive buffer empty */
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#define INTE 0x0c /* Interrupt enable register */
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#define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */
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@ -123,6 +130,11 @@
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/* behavior and possibly random segfaults and */
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/* lockups if enabled. */
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/* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
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#define A_INTE_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
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#define A_INTE_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
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#define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */
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/* NOTE: This bit must always be enabled */
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#define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */
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@ -139,6 +151,10 @@
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#define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
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#define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
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/* The next two interrupts are for the midi port on the Audigy (A_MPU2) */
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#define A_INTE_MIDITXENABLE1 INTE_MIDITXENABLE
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#define A_INTE_MIDIRXENABLE1 INTE_MIDIRXENABLE
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#define WC 0x10 /* Wall Clock register */
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#define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */
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#define WC_SAMPLECOUNTER 0x14060010
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@ -170,7 +186,10 @@
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#define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
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#define HCFG_GPINPUT0 0x00004000 /* External pin112 */
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#define HCFG_GPINPUT1 0x00002000 /* External pin110 */
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#define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */
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#define HCFG_GPOUT0 0x00001000 /* set to enable digital out on 5.1 cards */
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#define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */
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#define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */
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/* 1 = Force all 3 async digital inputs to use */
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@ -178,6 +197,7 @@
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#define HCFG_AC3ENABLE_MASK 0x0x0000e0 /* AC3 async input control - Not implemented */
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#define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */
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#define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */
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#define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */
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#define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */
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/* will automatically mute their output when */
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/* they are not rate-locked to the external */
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@ -186,6 +206,7 @@
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/* NOTE: This should generally never be used. */
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#define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */
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/* NOTE: This should generally never be used. */
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#define HCFG_LOCKTANKCACHE 0x01020014
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#define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */
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/* NOTE: This is a 'cheap' way to implement a */
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/* master mute function on the mute button, and */
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@ -196,6 +217,8 @@
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/* Should be set to 1 when the EMU10K1 is */
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/* completely initialized. */
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//For Audigy, MPU port move to 0x70-0x74 ptr register
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#define MUDATA 0x18 /* MPU401 data register (8 bits) */
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#define MUCMD 0x19 /* MPU401 command register (8 bits) */
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@ -207,13 +230,16 @@
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#define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */
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#define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */
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#define TIMER 0x1a /* Timer terminal count register */
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#define A_IOCFG 0x18 /* GPIO on Audigy card (16bits) */
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#define A_GPINPUT_MASK 0xff00
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#define A_GPOUTPUT_MASK 0x00ff
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#define TIMER 0x1a /* Timer terminal count register (16-bit) */
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/* NOTE: After the rate is changed, a maximum */
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/* of 1024 sample periods should be allowed */
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/* before the new rate is guaranteed accurate. */
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#define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */
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#define TIMER_RATE_MASK 0x03ff /* Timer interrupt rate in sample periods */
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/* 0 == 1024 periods, [1..4] are not useful */
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#define TIMER_RATE 0x0a00001a
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#define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
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@ -221,54 +247,6 @@
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#define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
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#define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */
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/************************************************************************************************/
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/* PCI function 1 registers, address = <val> + PCIBASE1 */
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/************************************************************************************************/
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#define JOYSTICK1 0x00 /* Analog joystick port register */
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#define JOYSTICK2 0x01 /* Analog joystick port register */
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#define JOYSTICK3 0x02 /* Analog joystick port register */
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#define JOYSTICK4 0x03 /* Analog joystick port register */
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#define JOYSTICK5 0x04 /* Analog joystick port register */
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#define JOYSTICK6 0x05 /* Analog joystick port register */
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#define JOYSTICK7 0x06 /* Analog joystick port register */
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#define JOYSTICK8 0x07 /* Analog joystick port register */
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/* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */
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/* When reading, use these bitfields: */
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#define JOYSTICK_BUTTONS 0x0f /* Joystick button data */
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#define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */
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/********************************************************************************************************/
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/* AC97 pointer-offset register set, accessed through the AC97ADDRESS and AC97DATA registers */
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/********************************************************************************************************/
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#define AC97_RESET 0x00
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#define AC97_MASTERVOLUME 0x02 /* Master volume */
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#define AC97_HEADPHONEVOLUME 0x04 /* Headphone volume */
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#define AC97_MASTERVOLUMEMONO 0x06 /* Mast volume mono */
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#define AC97_MASTERTONE 0x08
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#define AC97_PCBEEPVOLUME 0x0a /* PC speaker system beep volume */
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#define AC97_PHONEVOLUME 0x0c
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#define AC97_MICVOLUME 0x0e
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#define AC97_LINEINVOLUME 0x10
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#define AC97_CDVOLUME 0x12
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#define AC97_VIDEOVOLUME 0x14
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#define AC97_AUXVOLUME 0x16
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#define AC97_PCMOUTVOLUME 0x18
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#define AC97_RECORDSELECT 0x1a
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#define AC97_RECORDGAIN 0x1c
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#define AC97_RECORDGAINMIC 0x1e
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#define AC97_GENERALPURPOSE 0x20
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#define AC97_3DCONTROL 0x22
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#define AC97_MODEMRATE 0x24
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#define AC97_POWERDOWN 0x26
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#define AC97_VENDORID1 0x7c
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#define AC97_VENDORID2 0x7e
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#define AC97_ZVIDEOVOLUME 0xec
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#define AC97_AC3VOLUME 0xed
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/********************************************************************************************************/
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/* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
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/********************************************************************************************************/
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@ -444,6 +422,8 @@
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#define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */
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#define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */
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/* Signed 2's complement, with +/- 12dB extremes */
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#define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */
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/* ??Hz steps, maximum of ?? Hz. */
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#define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */
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#define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */
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@ -484,7 +464,12 @@
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#define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */
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/* NOTE: To guarantee phase coherency, both channels */
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/* must be disabled prior to enabling both channels. */
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#define A_ADCCR_RCHANENABLE 0x00000020
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#define A_ADCCR_LCHANENABLE 0x00000010
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#define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */
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#define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */
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#define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
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#define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
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#define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
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@ -494,10 +479,16 @@
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#define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
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#define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
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#define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */
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#define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */
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#define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */
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#define FXWC 0x43 /* FX output write channels register */
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/* When set, each bit enables the writing of the */
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/* corresponding FX output channel into host memory */
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/* corresponding FX output channel (internal registers */
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/* 0x20-0x3f) into host memory. This mode of recording */
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/* is 16bit, 48KHz only. All 32 channels can be enabled */
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/* simultaneously. */
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#define TCBS 0x44 /* Tank cache buffer size register */
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#define TCBS_MASK 0x00000007 /* Tank cache buffer size field */
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#define TCBS_BUFFSIZE_16K 0x00000000
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@ -565,8 +556,25 @@
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#define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
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/* definitions for debug register - taken from the alsa drivers */
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#define DBG_ZC 0x80000000 /* zero tram counter */
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#define DBG_SATURATION_OCCURED 0x02000000 /* saturation control */
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#define DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */
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#define DBG_SINGLE_STEP 0x00008000 /* single step mode */
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#define DBG_STEP 0x00004000 /* start single step */
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#define DBG_CONDITION_CODE 0x00003e00 /* condition code */
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#define DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */
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#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
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#define A_DBG 0x53
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#define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
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#define A_DBG_ZC 0x40000000 /* zero tram counter */
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#define A_DBG_STEP_ADDR 0x000003ff
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#define A_DBG_SATURATION_OCCURED 0x20000000
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#define A_DBG_SATURATION_ADDR 0x0ffc0000
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#define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
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#define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
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@ -613,6 +621,10 @@
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#define SPBYPASS 0x5e /* SPDIF BYPASS mode register */
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#define SPBYPASS_ENABLE 0x00000001 /* Enable SPDIF bypass mode */
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#define AC97SLOT 0x5f /* additional AC97 slots enable bits */
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#define AC97SLOT_CNTR 0x10 /* Center enable */
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#define AC97SLOT_LFE 0x20 /* LFE enable */
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#define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
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#define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */
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@ -626,10 +638,19 @@
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#define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */
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#define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */
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/* Note that these values can vary +/- by a small amount */
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#define SRCS_SPDIFRATE_44 0x0003acd9
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#define SRCS_SPDIFRATE_48 0x00040000
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#define SRCS_SPDIFRATE_96 0x00080000
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#define MICIDX 0x63 /* Microphone recording buffer index register */
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#define MICIDX_MASK 0x0000ffff /* 16-bit value */
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#define MICIDX_IDX 0x10000063
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#define A_ADCIDX 0x63
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#define A_ADCIDX_IDX 0x10000063
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#define ADCIDX 0x64 /* ADC recording buffer index register */
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#define ADCIDX_MASK 0x0000ffff /* 16 bit index field */
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#define ADCIDX_IDX 0x10000064
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@ -638,9 +659,50 @@
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#define FXIDX_MASK 0x0000ffff /* 16-bit value */
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#define FXIDX_IDX 0x10000065
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/* This is the MPU port on the card (via the game port) */
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#define A_MUDATA1 0x70
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#define A_MUCMD1 0x71
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#define A_MUSTAT1 A_MUCMD1
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/* This is the MPU port on the Audigy Drive */
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#define A_MUDATA2 0x72
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#define A_MUCMD2 0x73
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#define A_MUSTAT2 A_MUCMD2
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/* The next two are the Audigy equivalent of FXWC */
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/* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */
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/* Each bit selects a channel for recording */
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#define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
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#define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
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#define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */
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#define A_SPDIF_48000 0x00000080
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#define A_SPDIF_44100 0x00000000
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#define A_SPDIF_96000 0x00000040
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#define A_FXRT2 0x7c
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#define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */
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#define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */
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#define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */
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#define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */
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#define A_SENDAMOUNTS 0x7d
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#define A_FXSENDAMOUNT_E_MASK 0xff000000
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#define A_FXSENDAMOUNT_F_MASK 0x00ff0000
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#define A_FXSENDAMOUNT_G_MASK 0x0000ff00
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#define A_FXSENDAMOUNT_H_MASK 0x000000ff
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/* The send amounts for this one are the same as used with the emu10k1 */
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#define A_FXRT1 0x7e
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#define A_FXRT_CHANNELA 0x0000003f
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#define A_FXRT_CHANNELB 0x00003f00
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#define A_FXRT_CHANNELC 0x003f0000
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#define A_FXRT_CHANNELD 0x3f000000
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/* Each FX general purpose register is 32 bits in length, all bits are used */
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#define FXGPREGBASE 0x100 /* FX general purpose registers base */
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#define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
|
||||
/* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
|
||||
/* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
|
||||
/* locations are for external TRAM. */
|
||||
@ -665,10 +727,14 @@
|
||||
#define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
|
||||
#define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
|
||||
|
||||
#define ENABLE 0xffffffff
|
||||
#define DISABLE 0x00000000
|
||||
|
||||
#define ENV_ON 0x80
|
||||
#define ENV_OFF 0x00
|
||||
/* Audigy Soundcard have a different instruction format */
|
||||
#define AUDIGY_CODEBASE 0x600
|
||||
#define A_LOWORD_OPY_MASK 0x000007ff
|
||||
#define A_LOWORD_OPX_MASK 0x007ff000
|
||||
#define A_HIWORD_OPCODE_MASK 0x0f000000
|
||||
#define A_HIWORD_RESULT_MASK 0x007ff000
|
||||
#define A_HIWORD_OPA_MASK 0x000007ff
|
||||
|
||||
#endif /* EMU10K1_H */
|
||||
|
||||
#endif /* _8010_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user