Implement dirty and access bit exceptions.
This commit is contained in:
Doug Rabson
parent
3e90246a82
commit
254d92cca6
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=66463
@ -257,16 +257,211 @@ ia64_vector_table:
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/* 0x2000: Dirty-Bit vector */
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TRAP(8)
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mov r16=cr.ifa
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mov r17=pr
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mov r20=12<<2 // XXX get page size from VHPT
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;;
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ptc.l r16,r20 // purge TLB
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thash r18=r16
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ttag r19=r16
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;;
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srlz.d
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add r20=24,r18 // collision chain
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;;
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ld8 r20=[r20] // first entry
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;;
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rsm psr.dt // turn off data translations
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;;
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srlz.d // serialize
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;;
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1: cmp.eq p1,p2=r0,r20 // done?
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(p1) br.cond.spnt.few 9f // bail if done
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;;
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add r21=16,r20 // tag location
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;;
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ld8 r21=[r21] // read tag
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;;
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cmp.eq p1,p2=r21,r19 // compare tags
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(p2) br.cond.sptk.few 2f // if not, read next in chain
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;;
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ld8 r21=[r20] // read pte
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mov r22=PTE_D
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;;
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or r21=r22,r21 // set dirty bit
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;;
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st8 [r20]=r21 // store back
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;;
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ld8 r22=[r20] // read rest of pte
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;;
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dep r18=0,r18,61,3 // convert vhpt ptr to physical
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;;
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add r20=16,r18 // address of tag
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;;
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ld8.acq r23=[r20] // read old tag
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movl r24=(1<<63) // ti bit
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;;
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or r23=r23,r24 // set ti bit
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;;
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st8.rel [r20]=r23 // store old tag + ti
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;;
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mf // make sure everyone sees
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;;
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st8 [r18]=r21,8 // store pte
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;;
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st8 [r18]=r22,8
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;;
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st8.rel [r18]=r19 // store new tag
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;;
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mov pr=r17,0x1ffff // restore predicates
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;;
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rfi // walker will retry the access
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2: add r20=24,r20 // next in chain
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;;
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ld8 r20=[r20] // read chain
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br.cond.sptk.few 1b // loop
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9: mov pr=r17,0x1ffff // restore predicates
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TRAP(8) // die horribly
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.align 1024
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/* 0x2400: Instruction Access-Bit vector */
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mov r16=cr.ifa
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mov r17=pr
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mov r20=12<<2 // XXX get page size from VHPT
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;;
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ptc.l r16,r20 // purge TLB
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thash r18=r16
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ttag r19=r16
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;;
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srlz.d
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add r20=24,r18 // collision chain
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;;
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ld8 r20=[r20] // first entry
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;;
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rsm psr.dt // turn off data translations
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;;
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srlz.d // serialize
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;;
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1: cmp.eq p1,p2=r0,r20 // done?
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(p1) br.cond.spnt.few 9f // bail if done
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;;
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add r21=16,r20 // tag location
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;;
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ld8 r21=[r21] // read tag
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;;
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cmp.eq p1,p2=r21,r19 // compare tags
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(p2) br.cond.sptk.few 2f // if not, read next in chain
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;;
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ld8 r21=[r20] // read pte
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mov r22=PTE_A
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;;
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or r21=r22,r21 // set accessed bit
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;;
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st8 [r20]=r21 // store back
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;;
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ld8 r22=[r20] // read rest of pte
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;;
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dep r18=0,r18,61,3 // convert vhpt ptr to physical
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;;
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add r20=16,r18 // address of tag
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;;
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ld8.acq r23=[r20] // read old tag
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movl r24=(1<<63) // ti bit
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;;
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or r23=r23,r24 // set ti bit
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;;
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st8.rel [r20]=r23 // store old tag + ti
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;;
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mf // make sure everyone sees
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;;
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st8 [r18]=r21,8 // store pte
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;;
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st8 [r18]=r22,8
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;;
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st8.rel [r18]=r19 // store new tag
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;;
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mov pr=r17,0x1ffff // restore predicates
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;;
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rfi // walker will retry the access
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2: add r20=24,r20 // next in chain
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;;
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ld8 r20=[r20] // read chain
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br.cond.sptk.few 1b // loop
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9: mov pr=r17,0x1ffff // restore predicates
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TRAP(9)
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.align 1024
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/* 0x2800: Data Access-Bit vector */
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mov r16=cr.ifa
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mov r17=pr
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mov r20=12<<2 // XXX get page size from VHPT
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;;
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ptc.l r16,r20 // purge TLB
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thash r18=r16
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ttag r19=r16
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;;
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srlz.d
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add r20=24,r18 // collision chain
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;;
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ld8 r20=[r20] // first entry
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;;
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rsm psr.dt // turn off data translations
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;;
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srlz.d // serialize
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;;
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1: cmp.eq p1,p2=r0,r20 // done?
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(p1) br.cond.spnt.few 9f // bail if done
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;;
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add r21=16,r20 // tag location
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;;
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ld8 r21=[r21] // read tag
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;;
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cmp.eq p1,p2=r21,r19 // compare tags
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(p2) br.cond.sptk.few 2f // if not, read next in chain
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;;
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ld8 r21=[r20] // read pte
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mov r22=PTE_A
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;;
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or r21=r22,r21 // set accessed bit
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;;
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st8 [r20]=r21 // store back
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;;
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ld8 r22=[r20] // read rest of pte
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;;
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dep r18=0,r18,61,3 // convert vhpt ptr to physical
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;;
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add r20=16,r18 // address of tag
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;;
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ld8.acq r23=[r20] // read old tag
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movl r24=(1<<63) // ti bit
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;;
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or r23=r23,r24 // set ti bit
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;;
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st8.rel [r20]=r23 // store old tag + ti
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;;
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mf // make sure everyone sees
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;;
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st8 [r18]=r21,8 // store pte
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;;
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st8 [r18]=r22,8
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;;
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st8.rel [r18]=r19 // store new tag
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;;
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mov pr=r17,0x1ffff // restore predicates
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;;
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rfi // walker will retry the access
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2: add r20=24,r20 // next in chain
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;;
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ld8 r20=[r20] // read chain
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br.cond.sptk.few 1b // loop
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9: mov pr=r17,0x1ffff // restore predicates
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TRAP(10)
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.align 1024
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@ -257,16 +257,211 @@ ia64_vector_table:
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/* 0x2000: Dirty-Bit vector */
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TRAP(8)
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mov r16=cr.ifa
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mov r17=pr
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mov r20=12<<2 // XXX get page size from VHPT
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;;
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ptc.l r16,r20 // purge TLB
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thash r18=r16
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ttag r19=r16
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;;
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srlz.d
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add r20=24,r18 // collision chain
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;;
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ld8 r20=[r20] // first entry
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;;
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rsm psr.dt // turn off data translations
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;;
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srlz.d // serialize
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;;
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1: cmp.eq p1,p2=r0,r20 // done?
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(p1) br.cond.spnt.few 9f // bail if done
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;;
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add r21=16,r20 // tag location
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;;
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ld8 r21=[r21] // read tag
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;;
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cmp.eq p1,p2=r21,r19 // compare tags
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(p2) br.cond.sptk.few 2f // if not, read next in chain
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;;
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ld8 r21=[r20] // read pte
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mov r22=PTE_D
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;;
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or r21=r22,r21 // set dirty bit
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;;
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st8 [r20]=r21 // store back
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;;
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ld8 r22=[r20] // read rest of pte
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;;
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dep r18=0,r18,61,3 // convert vhpt ptr to physical
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;;
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add r20=16,r18 // address of tag
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;;
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ld8.acq r23=[r20] // read old tag
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movl r24=(1<<63) // ti bit
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;;
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or r23=r23,r24 // set ti bit
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;;
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st8.rel [r20]=r23 // store old tag + ti
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;;
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mf // make sure everyone sees
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;;
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st8 [r18]=r21,8 // store pte
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;;
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st8 [r18]=r22,8
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;;
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st8.rel [r18]=r19 // store new tag
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;;
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mov pr=r17,0x1ffff // restore predicates
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;;
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rfi // walker will retry the access
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2: add r20=24,r20 // next in chain
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;;
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ld8 r20=[r20] // read chain
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br.cond.sptk.few 1b // loop
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9: mov pr=r17,0x1ffff // restore predicates
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TRAP(8) // die horribly
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.align 1024
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/* 0x2400: Instruction Access-Bit vector */
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mov r16=cr.ifa
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mov r17=pr
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mov r20=12<<2 // XXX get page size from VHPT
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;;
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ptc.l r16,r20 // purge TLB
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thash r18=r16
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ttag r19=r16
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;;
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srlz.d
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add r20=24,r18 // collision chain
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;;
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ld8 r20=[r20] // first entry
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;;
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rsm psr.dt // turn off data translations
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;;
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srlz.d // serialize
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;;
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1: cmp.eq p1,p2=r0,r20 // done?
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(p1) br.cond.spnt.few 9f // bail if done
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;;
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add r21=16,r20 // tag location
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;;
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ld8 r21=[r21] // read tag
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;;
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cmp.eq p1,p2=r21,r19 // compare tags
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(p2) br.cond.sptk.few 2f // if not, read next in chain
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;;
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ld8 r21=[r20] // read pte
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mov r22=PTE_A
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;;
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or r21=r22,r21 // set accessed bit
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;;
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st8 [r20]=r21 // store back
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;;
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ld8 r22=[r20] // read rest of pte
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;;
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dep r18=0,r18,61,3 // convert vhpt ptr to physical
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;;
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add r20=16,r18 // address of tag
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;;
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ld8.acq r23=[r20] // read old tag
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movl r24=(1<<63) // ti bit
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;;
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or r23=r23,r24 // set ti bit
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;;
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st8.rel [r20]=r23 // store old tag + ti
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;;
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mf // make sure everyone sees
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;;
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st8 [r18]=r21,8 // store pte
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;;
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st8 [r18]=r22,8
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;;
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st8.rel [r18]=r19 // store new tag
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;;
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mov pr=r17,0x1ffff // restore predicates
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;;
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rfi // walker will retry the access
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2: add r20=24,r20 // next in chain
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;;
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ld8 r20=[r20] // read chain
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br.cond.sptk.few 1b // loop
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9: mov pr=r17,0x1ffff // restore predicates
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TRAP(9)
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.align 1024
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/* 0x2800: Data Access-Bit vector */
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mov r16=cr.ifa
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mov r17=pr
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mov r20=12<<2 // XXX get page size from VHPT
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;;
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ptc.l r16,r20 // purge TLB
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thash r18=r16
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ttag r19=r16
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;;
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srlz.d
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add r20=24,r18 // collision chain
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;;
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ld8 r20=[r20] // first entry
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;;
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rsm psr.dt // turn off data translations
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;;
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srlz.d // serialize
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;;
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1: cmp.eq p1,p2=r0,r20 // done?
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(p1) br.cond.spnt.few 9f // bail if done
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;;
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add r21=16,r20 // tag location
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;;
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ld8 r21=[r21] // read tag
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;;
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cmp.eq p1,p2=r21,r19 // compare tags
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(p2) br.cond.sptk.few 2f // if not, read next in chain
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;;
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ld8 r21=[r20] // read pte
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mov r22=PTE_A
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;;
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or r21=r22,r21 // set accessed bit
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;;
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st8 [r20]=r21 // store back
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;;
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ld8 r22=[r20] // read rest of pte
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;;
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dep r18=0,r18,61,3 // convert vhpt ptr to physical
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;;
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add r20=16,r18 // address of tag
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;;
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ld8.acq r23=[r20] // read old tag
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movl r24=(1<<63) // ti bit
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;;
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or r23=r23,r24 // set ti bit
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;;
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st8.rel [r20]=r23 // store old tag + ti
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;;
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mf // make sure everyone sees
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;;
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st8 [r18]=r21,8 // store pte
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;;
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st8 [r18]=r22,8
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;;
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st8.rel [r18]=r19 // store new tag
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;;
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mov pr=r17,0x1ffff // restore predicates
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;;
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rfi // walker will retry the access
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2: add r20=24,r20 // next in chain
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;;
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ld8 r20=[r20] // read chain
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br.cond.sptk.few 1b // loop
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9: mov pr=r17,0x1ffff // restore predicates
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TRAP(10)
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.align 1024
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@ -969,6 +969,10 @@ pmap_set_pv(pmap_t pmap, pv_entry_t pv, vm_offset_t pa,
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}
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pv->pv_pte.pte_p = 1; /* set to valid */
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/*
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* Only track access/modify for managed pages.
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*/
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if (m) {
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pv->pv_pte.pte_a = 0;
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pv->pv_pte.pte_d = 0;
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@ -976,10 +980,9 @@ pmap_set_pv(pmap_t pmap, pv_entry_t pv, vm_offset_t pa,
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pv->pv_pte.pte_a = 1;
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pv->pv_pte.pte_d = 1;
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}
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pv->pv_pte.pte_a = 1; /* XXX remove this after implementing trap */
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pv->pv_pte.pte_d = 1;
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pv->pv_pte.pte_pl = prot & 3; /* privilege level 0 */
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pv->pv_pte.pte_ar = prot >> 2; /* read/write/execute */
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pv->pv_pte.pte_pl = prot & 3; /* privilege level */
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pv->pv_pte.pte_ar = prot >> 2; /* access rights */
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pv->pv_pte.pte_ppn = pa >> 12; /* physical address */
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if (m) {
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