Vendor import of llvm release_50 branch r312293:
https://llvm.org/svn/llvm-project/llvm/branches/release_50@312293
This commit is contained in:
parent
5e529592b1
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/vendor/llvm/dist/; revision=323088 svn path=/vendor/llvm/llvm-release_50-r312293/; revision=323089; tag=vendor/llvm/llvm-release_50-r312293
@ -5,11 +5,6 @@ LLVM 5.0.0 Release Notes
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.. contents::
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:local:
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.. warning::
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These are in-progress notes for the upcoming LLVM 5 release.
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Release notes for previous releases can be found on
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`the Download Page <http://releases.llvm.org/download.html>`_.
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Introduction
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============
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@ -26,55 +21,50 @@ have questions or comments, the `LLVM Developer's Mailing List
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<http://lists.llvm.org/mailman/listinfo/llvm-dev>`_ is a good place to send
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them.
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Note that if you are reading this file from a Subversion checkout or the main
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LLVM web page, this document applies to the *next* release, not the current
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one. To see the release notes for a specific release, please see the `releases
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page <http://llvm.org/releases/>`_.
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Non-comprehensive list of changes in this release
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=================================================
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.. NOTE
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For small 1-3 sentence descriptions, just add an entry at the end of
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this list. If your description won't fit comfortably in one bullet
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point (e.g. maybe you would like to give an example of the
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functionality, or simply have a lot to talk about), see the `NOTE` below
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for adding a new subsection.
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* LLVM's ``WeakVH`` has been renamed to ``WeakTrackingVH`` and a new ``WeakVH``
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has been introduced. The new ``WeakVH`` nulls itself out on deletion, but
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does not track values across RAUW.
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* A new library named ``BinaryFormat`` has been created which holds a collection
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of code which previously lived in ``Support``. This includes the
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``file_magic`` structure and ``identify_magic`` functions, as well as all the
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structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file
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formats.
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* The tool ``llvm-pdbdump`` has been renamed ``llvm-pdbutil`` to better reflect
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its nature as a general purpose PDB manipulation / diagnostics tool that does
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more than just dumping contents.
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* The ``BBVectorize`` pass has been removed. It was fully replaced and no
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longer used back in 2014 but we didn't get around to removing it. Now it is
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gone. The SLP vectorizer is the suggested non-loop vectorization pass.
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.. NOTE
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If you would like to document a larger change, then you can add a
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subsection about it right here. You can copy the following boilerplate
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and un-indent it (the indentation causes it to be inside this comment).
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* A new tool opt-viewer.py has been added to visualize optimization remarks in
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HTML. The tool processes the YAML files produced by clang with the
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-fsave-optimization-record option.
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Special New Feature
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-------------------
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* A new CMake macro ``LLVM_REVERSE_ITERATION`` has been added. If enabled, all
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supported unordered LLVM containers would be iterated in reverse order. This
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is useful for uncovering non-determinism caused by iteration of unordered
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containers. Currently, it supports reverse iteration of SmallPtrSet and
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DenseMap.
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* A new tool ``llvm-dlltool`` has been added to create short import libraries
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from GNU style definition files. The tool utilizes the PE COFF SPEC Import
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Library Format and PE COFF Auxiliary Weak Externals Format to achieve
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compatibility with LLD and MSVC LINK.
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Makes programs 10x faster by doing Special New Thing.
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Changes to the LLVM IR
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----------------------
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* The datalayout string may now indicate an address space to use for
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the pointer type of alloca rather than the default of 0.
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the pointer type of ``alloca`` rather than the default of 0.
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* Added speculatable attribute indicating a function which does has no
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* Added ``speculatable`` attribute indicating a function which has no
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side-effects which could inhibit hoisting of calls.
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Changes to the Arm Targets
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@ -108,7 +98,41 @@ During this release the ARM target has:
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Changes to the MIPS Target
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--------------------------
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During this release ...
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* The microMIPS64R6 backend is deprecated and will be removed in the next
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release.
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* The MIPS backend now directly supports vector types for arguments and return
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values (previously this required ABI specific LLVM IR).
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* Added documentation for how the MIPS backend handles address lowering.
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* Added a GCC compatible option -m(no-)madd4 to control the generation of four
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operand multiply addition/subtraction instructions.
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* Added basic support for the XRay instrumentation system.
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* Added support for more assembly aliases and macros.
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* Added support for the ``micromips`` and ``nomicromips`` function attributes
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which control micromips code generation on a per function basis.
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* Added the ``long-calls`` feature for non-pic environments. This feature is
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used where the callee is out of range of the caller using a standard call
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sequence. It must be enabled specifically.
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* Added support for performing microMIPS code generation via function
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attributes.
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* Added experimental support for the static relocation model for the N64 ABI.
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* Added partial support for the MT ASE.
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* Added basic support for code size reduction for microMIPS.
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* Fixed numerous bugs including: multi-precision arithmetic support, various
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vectorization bugs, debug information for thread local variables, debug
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sections lacking the correct flags, crashing when disassembling sections
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whose size is not a multiple of two or four.
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Changes to the PowerPC Target
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@ -118,26 +142,24 @@ Changes to the PowerPC Target
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vabsduw, modsw, moduw, modsd, modud, lxv, stxv, vextublx, vextubrx, vextuhlx,
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vextuhrx, vextuwlx, vextuwrx, vextsb2w, vextsb2d, vextsh2w, vextsh2d, and
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vextsw2d
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* Implemented Optimal Code Sequences from The PowerPC Compiler Writer's Guide.
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* Enable -fomit-frame-pointer by default.
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* Improved handling of bit reverse intrinsic.
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* Improved handling of memcpy and memcmp functions.
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* Improved handling of branches with static branch hints.
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* Improved codegen for atomic load_acquire.
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* Improved block placement during code layout
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* Many improvements to instruction selection and code generation
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Changes to the X86 Target
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-------------------------
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@ -173,6 +195,9 @@ Changes to the X86 Target
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* Fixed many inline assembly bugs.
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* Preliminary support for tracing NetBSD processes and core files with a single
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thread in LLDB.
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Changes to the AMDGPU Target
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-----------------------------
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@ -187,22 +212,17 @@ required for compiling basic Rust programs.
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* Enable the branch relaxation pass so that we don't crash on large
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stack load/stores
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* Add support for lowering bit-rotations to the native `ror` and `rol`
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* Add support for lowering bit-rotations to the native ``ror`` and ``rol``
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instructions
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* Fix bug where function pointers were treated as pointers to RAM and not
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pointers to program memory
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* Fix broken code generaton for shift-by-variable expressions
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* Fix broken code generation for shift-by-variable expressions
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* Support zero-sized types in argument lists; this is impossible in C,
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but possible in Rust
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Changes to the OCaml bindings
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-----------------------------
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During this release ...
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Changes to the C API
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--------------------
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@ -1,11 +1,6 @@
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Overview
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========
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.. warning::
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If you are using a released version of LLVM, see `the download page
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<http://llvm.org/releases/>`_ to find your documentation.
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The LLVM compiler infrastructure supports a wide range of projects, from
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industrial strength compilers to specialized JIT applications to small
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research projects.
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@ -801,7 +801,8 @@ class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
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/// if DAG changes.
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static bool hasPredecessorHelper(const SDNode *N,
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SmallPtrSetImpl<const SDNode *> &Visited,
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SmallVectorImpl<const SDNode *> &Worklist) {
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SmallVectorImpl<const SDNode *> &Worklist,
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unsigned int MaxSteps = 0) {
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if (Visited.count(N))
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return true;
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while (!Worklist.empty()) {
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@ -816,6 +817,8 @@ class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
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}
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if (Found)
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return true;
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if (MaxSteps != 0 && Visited.size() >= MaxSteps)
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return false;
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}
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return false;
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}
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@ -23,8 +23,6 @@ using namespace llvm;
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#define DEBUG_TYPE "postdomtree"
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template class llvm::DominatorTreeBase<BasicBlock, true>; // PostDomTreeBase
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//===----------------------------------------------------------------------===//
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// PostDominatorTree Implementation
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//===----------------------------------------------------------------------===//
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@ -1118,22 +1118,30 @@ SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
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SDValue RV =
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DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, NN0, NN1));
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// New replace instances of N0 and N1
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if (Replace0 && N0 && N0.getOpcode() != ISD::DELETED_NODE && NN0 &&
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NN0.getOpcode() != ISD::DELETED_NODE) {
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// We are always replacing N0/N1's use in N and only need
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// additional replacements if there are additional uses.
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Replace0 &= !N0->hasOneUse();
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Replace1 &= (N0 != N1) && !N1->hasOneUse();
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// Combine Op here so it is presreved past replacements.
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CombineTo(Op.getNode(), RV);
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// If operands have a use ordering, make sur we deal with
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// predecessor first.
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if (Replace0 && Replace1 && N0.getNode()->isPredecessorOf(N1.getNode())) {
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std::swap(N0, N1);
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std::swap(NN0, NN1);
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}
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if (Replace0) {
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AddToWorklist(NN0.getNode());
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ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
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}
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if (Replace1 && N1 && N1.getOpcode() != ISD::DELETED_NODE && NN1 &&
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NN1.getOpcode() != ISD::DELETED_NODE) {
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if (Replace1) {
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AddToWorklist(NN1.getNode());
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ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
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}
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// Deal with Op being deleted.
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if (Op && Op.getOpcode() != ISD::DELETED_NODE)
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return RV;
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return Op;
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}
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return SDValue();
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}
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@ -12599,25 +12607,37 @@ void DAGCombiner::getStoreMergeCandidates(
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}
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}
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// We need to check that merging these stores does not cause a loop
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// in the DAG. Any store candidate may depend on another candidate
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// We need to check that merging these stores does not cause a loop in
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// the DAG. Any store candidate may depend on another candidate
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// indirectly through its operand (we already consider dependencies
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// through the chain). Check in parallel by searching up from
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// non-chain operands of candidates.
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bool DAGCombiner::checkMergeStoreCandidatesForDependencies(
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SmallVectorImpl<MemOpLink> &StoreNodes, unsigned NumStores) {
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// FIXME: We should be able to truncate a full search of
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// predecessors by doing a BFS and keeping tabs the originating
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// stores from which worklist nodes come from in a similar way to
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// TokenFactor simplfication.
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SmallPtrSet<const SDNode *, 16> Visited;
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SmallVector<const SDNode *, 8> Worklist;
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// search ops of store candidates
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unsigned int Max = 8192;
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// Search Ops of store candidates.
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for (unsigned i = 0; i < NumStores; ++i) {
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SDNode *n = StoreNodes[i].MemNode;
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// Potential loops may happen only through non-chain operands
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for (unsigned j = 1; j < n->getNumOperands(); ++j)
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Worklist.push_back(n->getOperand(j).getNode());
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}
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// search through DAG. We can stop early if we find a storenode
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// Search through DAG. We can stop early if we find a store node.
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for (unsigned i = 0; i < NumStores; ++i) {
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if (SDNode::hasPredecessorHelper(StoreNodes[i].MemNode, Visited, Worklist))
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if (SDNode::hasPredecessorHelper(StoreNodes[i].MemNode, Visited, Worklist,
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Max))
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return false;
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// Check if we ended early, failing conservatively if so.
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if (Visited.size() >= Max)
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return false;
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}
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return true;
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53
test/CodeGen/X86/pr34137.ll
Normal file
53
test/CodeGen/X86/pr34137.ll
Normal file
@ -0,0 +1,53 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
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@var_3 = external global i16, align 2
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@var_13 = external global i16, align 2
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@var_212 = external global i64, align 8
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define void @pr34127() {
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; CHECK-LABEL: pr34127:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: movzwl {{.*}}(%rip), %eax
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; CHECK-NEXT: movw {{.*}}(%rip), %cx
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; CHECK-NEXT: andw %ax, %cx
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; CHECK-NEXT: andl %eax, %ecx
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; CHECK-NEXT: movl %ecx, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: testw %cx, %cx
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; CHECK-NEXT: sete %dl
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; CHECK-NEXT: andl %eax, %edx
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; CHECK-NEXT: movq %rdx, {{.*}}(%rip)
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; CHECK-NEXT: movw $0, (%rax)
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; CHECK-NEXT: retq
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entry:
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%a = alloca i32, align 4
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%0 = load i16, i16* @var_3, align 2
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%conv = zext i16 %0 to i32
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%1 = load i16, i16* @var_3, align 2
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%conv1 = zext i16 %1 to i32
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%2 = load i16, i16* @var_13, align 2
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%conv2 = zext i16 %2 to i32
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%and = and i32 %conv1, %conv2
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%and3 = and i32 %conv, %and
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store i32 %and3, i32* %a, align 4
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%3 = load i16, i16* @var_3, align 2
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%conv4 = zext i16 %3 to i32
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%4 = load i16, i16* @var_3, align 2
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%conv5 = zext i16 %4 to i32
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%5 = load i16, i16* @var_13, align 2
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%conv6 = zext i16 %5 to i32
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%and7 = and i32 %conv5, %conv6
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%and8 = and i32 %conv4, %and7
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%tobool = icmp ne i32 %and8, 0
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%lnot = xor i1 %tobool, true
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%conv9 = zext i1 %lnot to i32
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%6 = load i16, i16* @var_3, align 2
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%conv10 = zext i16 %6 to i32
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%and11 = and i32 %conv9, %conv10
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%conv12 = sext i32 %and11 to i64
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store i64 %conv12, i64* @var_212, align 8
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%conv14 = zext i1 undef to i16
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store i16 %conv14, i16* undef, align 2
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ret void
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}
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