Pull in r282174 from upstream llvm trunk (by Krzysztof Parzyszek):
[PPC] Set SP after loading data from stack frame, if no red zone is present Follow-up to r280705: Make sure that the SP is only restored after all data is loaded from the stack frame, if there is no red zone. This completes the fix for https://llvm.org/bugs/show_bug.cgi?id=26519. Differential Revision: https://reviews.llvm.org/D24466 Reported by: Mark Millard PR: 214433
This commit is contained in:
parent
cdaf963483
commit
26aa2dc584
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=309147
@ -927,7 +927,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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}
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// Have we generated a STUX instruction to claim stack frame? If so,
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// the frame size will be placed in ScratchReg.
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// the negated frame size will be placed in ScratchReg.
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bool HasSTUX = false;
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// This condition must be kept in sync with canUseAsPrologue.
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@ -987,33 +987,88 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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if (!HasRedZone) {
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assert(!isPPC64 && "A red zone is always available on PPC64");
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if (HasSTUX) {
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// The frame size is in ScratchReg, and the SPReg has been advanced
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// (downwards) by the frame size: SPReg = old SPReg + ScratchReg.
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// Set ScratchReg to the original SPReg: ScratchReg = SPReg - ScratchReg.
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// The negated frame size is in ScratchReg, and the SPReg has been
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// decremented by the frame size: SPReg = old SPReg + ScratchReg.
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// Since FPOffset, PBPOffset, etc. are relative to the beginning of
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// the stack frame (i.e. the old SP), ideally, we would put the old
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// SP into a register and use it as the base for the stores. The
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// problem is that the only available register may be ScratchReg,
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// which could be R0, and R0 cannot be used as a base address.
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// First, set ScratchReg to the old SP. This may need to be modified
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// later.
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BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBF), ScratchReg)
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.addReg(ScratchReg, RegState::Kill)
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.addReg(SPReg);
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// Now that the stack frame has been allocated, save all the necessary
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// registers using ScratchReg as the base address.
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if (HasFP)
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BuildMI(MBB, MBBI, dl, StoreInst)
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.addReg(FPReg)
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.addImm(FPOffset)
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.addReg(ScratchReg);
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if (FI->usesPICBase())
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BuildMI(MBB, MBBI, dl, StoreInst)
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.addReg(PPC::R30)
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.addImm(PBPOffset)
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.addReg(ScratchReg);
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if (HasBP) {
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BuildMI(MBB, MBBI, dl, StoreInst)
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.addReg(BPReg)
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.addImm(BPOffset)
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.addReg(ScratchReg);
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BuildMI(MBB, MBBI, dl, OrInst, BPReg)
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.addReg(ScratchReg, RegState::Kill)
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.addReg(ScratchReg);
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if (ScratchReg == PPC::R0) {
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// R0 cannot be used as a base register, but it can be used as an
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// index in a store-indexed.
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int LastOffset = 0;
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if (HasFP) {
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// R0 += (FPOffset-LastOffset).
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// Need addic, since addi treats R0 as 0.
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BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
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.addReg(ScratchReg)
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.addImm(FPOffset-LastOffset);
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LastOffset = FPOffset;
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// Store FP into *R0.
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
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.addReg(FPReg, RegState::Kill) // Save FP.
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.addReg(PPC::ZERO)
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.addReg(ScratchReg); // This will be the index (R0 is ok here).
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}
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if (FI->usesPICBase()) {
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// R0 += (PBPOffset-LastOffset).
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BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
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.addReg(ScratchReg)
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.addImm(PBPOffset-LastOffset);
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LastOffset = PBPOffset;
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
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.addReg(PPC::R30, RegState::Kill) // Save PIC base pointer.
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.addReg(PPC::ZERO)
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.addReg(ScratchReg); // This will be the index (R0 is ok here).
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}
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if (HasBP) {
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// R0 += (BPOffset-LastOffset).
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BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
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.addReg(ScratchReg)
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.addImm(BPOffset-LastOffset);
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LastOffset = BPOffset;
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
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.addReg(BPReg, RegState::Kill) // Save BP.
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.addReg(PPC::ZERO)
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.addReg(ScratchReg); // This will be the index (R0 is ok here).
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// BP = R0-LastOffset
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BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), BPReg)
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.addReg(ScratchReg, RegState::Kill)
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.addImm(-LastOffset);
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}
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} else {
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// ScratchReg is not R0, so use it as the base register. It is
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// already set to the old SP, so we can use the offsets directly.
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// Now that the stack frame has been allocated, save all the necessary
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// registers using ScratchReg as the base address.
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if (HasFP)
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BuildMI(MBB, MBBI, dl, StoreInst)
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.addReg(FPReg)
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.addImm(FPOffset)
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.addReg(ScratchReg);
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if (FI->usesPICBase())
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BuildMI(MBB, MBBI, dl, StoreInst)
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.addReg(PPC::R30)
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.addImm(PBPOffset)
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.addReg(ScratchReg);
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if (HasBP) {
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BuildMI(MBB, MBBI, dl, StoreInst)
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.addReg(BPReg)
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.addImm(BPOffset)
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.addReg(ScratchReg);
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BuildMI(MBB, MBBI, dl, OrInst, BPReg)
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.addReg(ScratchReg, RegState::Kill)
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.addReg(ScratchReg);
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}
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}
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} else {
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// The frame size is a known 16-bit constant (fitting in the immediate
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@ -1191,6 +1246,7 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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// Do we have a frame pointer and/or base pointer for this function?
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bool HasFP = hasFP(MF);
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bool HasBP = RegInfo->hasBasePointer(MF);
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bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();
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unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
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unsigned BPReg = RegInfo->getBaseRegister(MF);
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@ -1203,6 +1259,8 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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: PPC::LWZ );
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const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
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: PPC::LIS );
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const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
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: PPC::OR );
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const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
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: PPC::ORI );
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const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
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@ -1224,10 +1282,9 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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if (HasFP) {
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if (isSVR4ABI) {
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MachineFrameInfo *FFI = MF.getFrameInfo();
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int FPIndex = FI->getFramePointerSaveIndex();
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assert(FPIndex && "No Frame Pointer Save Slot!");
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FPOffset = FFI->getObjectOffset(FPIndex);
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FPOffset = MFI->getObjectOffset(FPIndex);
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} else {
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FPOffset = getFramePointerSaveOffset();
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}
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@ -1236,10 +1293,9 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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int BPOffset = 0;
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if (HasBP) {
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if (isSVR4ABI) {
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MachineFrameInfo *FFI = MF.getFrameInfo();
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int BPIndex = FI->getBasePointerSaveIndex();
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assert(BPIndex && "No Base Pointer Save Slot!");
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BPOffset = FFI->getObjectOffset(BPIndex);
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BPOffset = MFI->getObjectOffset(BPIndex);
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} else {
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BPOffset = getBasePointerSaveOffset();
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}
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@ -1247,10 +1303,9 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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int PBPOffset = 0;
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if (FI->usesPICBase()) {
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MachineFrameInfo *FFI = MF.getFrameInfo();
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int PBPIndex = FI->getPICBasePointerSaveIndex();
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assert(PBPIndex && "No PIC Base Pointer Save Slot!");
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PBPOffset = FFI->getObjectOffset(PBPIndex);
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PBPOffset = MFI->getObjectOffset(PBPIndex);
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}
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bool IsReturnBlock = (MBBI != MBB.end() && MBBI->isReturn());
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@ -1283,9 +1338,25 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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// indexed into with a simple LD/LWZ immediate offset operand.
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bool isLargeFrame = !isInt<16>(FrameSize);
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// On targets without red zone, the SP needs to be restored last, so that
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// all live contents of the stack frame are upwards of the SP. This means
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// that we cannot restore SP just now, since there may be more registers
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// to restore from the stack frame (e.g. R31). If the frame size is not
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// a simple immediate value, we will need a spare register to hold the
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// restored SP. If the frame size is known and small, we can simply adjust
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// the offsets of the registers to be restored, and still use SP to restore
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// them. In such case, the final update of SP will be to add the frame
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// size to it.
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// To simplify the code, set RBReg to the base register used to restore
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// values from the stack, and set SPAdd to the value that needs to be added
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// to the SP at the end. The default values are as if red zone was present.
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unsigned RBReg = SPReg;
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unsigned SPAdd = 0;
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if (FrameSize) {
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// In the prologue, the loaded (or persistent) stack pointer value is offset
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// by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now.
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// In the prologue, the loaded (or persistent) stack pointer value is
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// offset by the STDU/STDUX/STWU/STWUX instruction. For targets with red
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// zone add this offset back now.
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// If this function contained a fastcc call and GuaranteedTailCallOpt is
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// enabled (=> hasFastCall()==true) the fastcc call might contain a tail
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@ -1293,8 +1364,10 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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// value of R31 in this case.
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if (FI->hasFastCall()) {
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assert(HasFP && "Expecting a valid frame pointer.");
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if (!HasRedZone)
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RBReg = FPReg;
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if (!isLargeFrame) {
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BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
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BuildMI(MBB, MBBI, dl, AddImmInst, RBReg)
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.addReg(FPReg).addImm(FrameSize);
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} else {
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BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
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@ -1303,27 +1376,55 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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.addReg(ScratchReg, RegState::Kill)
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.addImm(FrameSize & 0xFFFF);
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BuildMI(MBB, MBBI, dl, AddInst)
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.addReg(SPReg)
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.addReg(RBReg)
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.addReg(FPReg)
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.addReg(ScratchReg);
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}
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} else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) {
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BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
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.addReg(SPReg)
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.addImm(FrameSize);
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if (HasRedZone) {
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BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
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.addReg(SPReg)
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.addImm(FrameSize);
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} else {
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// Make sure that adding FrameSize will not overflow the max offset
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// size.
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assert(FPOffset <= 0 && BPOffset <= 0 && PBPOffset <= 0 &&
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"Local offsets should be negative");
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SPAdd = FrameSize;
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FPOffset += FrameSize;
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BPOffset += FrameSize;
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PBPOffset += FrameSize;
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}
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} else {
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BuildMI(MBB, MBBI, dl, LoadInst, SPReg)
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// We don't want to use ScratchReg as a base register, because it
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// could happen to be R0. Use FP instead, but make sure to preserve it.
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if (!HasRedZone) {
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// If FP is not saved, copy it to ScratchReg.
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if (!HasFP)
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BuildMI(MBB, MBBI, dl, OrInst, ScratchReg)
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.addReg(FPReg)
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.addReg(FPReg);
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RBReg = FPReg;
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}
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BuildMI(MBB, MBBI, dl, LoadInst, RBReg)
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.addImm(0)
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.addReg(SPReg);
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}
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}
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assert(RBReg != ScratchReg && "Should have avoided ScratchReg");
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// If there is no red zone, ScratchReg may be needed for holding a useful
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// value (although not the base register). Make sure it is not overwritten
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// too early.
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assert((isPPC64 || !MustSaveCR) &&
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"Epilogue CR restoring supported only in 64-bit mode");
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// If we need to save both the LR and the CR and we only have one available
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// scratch register, we must do them one at a time.
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// If we need to restore both the LR and the CR and we only have one
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// available scratch register, we must do them one at a time.
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if (MustSaveCR && SingleScratchReg && MustSaveLR) {
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// Here TempReg == ScratchReg, and in the absence of red zone ScratchReg
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// is live here.
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assert(HasRedZone && "Expecting red zone");
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BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
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.addImm(8)
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.addReg(SPReg);
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@ -1332,33 +1433,77 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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.addReg(TempReg, getKillRegState(i == e-1));
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}
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if (MustSaveLR)
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// Delay restoring of the LR if ScratchReg is needed. This is ok, since
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// LR is stored in the caller's stack frame. ScratchReg will be needed
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// if RBReg is anything other than SP. We shouldn't use ScratchReg as
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// a base register anyway, because it may happen to be R0.
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bool LoadedLR = false;
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if (MustSaveLR && RBReg == SPReg && isInt<16>(LROffset+SPAdd)) {
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BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
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.addImm(LROffset)
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.addReg(SPReg);
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.addImm(LROffset+SPAdd)
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.addReg(RBReg);
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LoadedLR = true;
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}
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if (MustSaveCR &&
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!(SingleScratchReg && MustSaveLR)) // will only occur for PPC64
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if (MustSaveCR && !(SingleScratchReg && MustSaveLR)) {
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// This will only occur for PPC64.
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assert(isPPC64 && "Expecting 64-bit mode");
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assert(RBReg == SPReg && "Should be using SP as a base register");
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BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
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.addImm(8)
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.addReg(SPReg);
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.addReg(RBReg);
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}
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if (HasFP)
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BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
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.addImm(FPOffset)
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.addReg(SPReg);
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if (HasFP) {
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// If there is red zone, restore FP directly, since SP has already been
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// restored. Otherwise, restore the value of FP into ScratchReg.
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if (HasRedZone || RBReg == SPReg)
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BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
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.addImm(FPOffset)
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.addReg(SPReg);
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else
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BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
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.addImm(FPOffset)
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.addReg(RBReg);
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}
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if (FI->usesPICBase())
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// FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
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BuildMI(MBB, MBBI, dl, LoadInst)
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.addReg(PPC::R30)
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.addImm(PBPOffset)
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.addReg(SPReg);
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.addReg(RBReg);
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if (HasBP)
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BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
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.addImm(BPOffset)
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.addReg(SPReg);
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.addReg(RBReg);
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// There is nothing more to be loaded from the stack, so now we can
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// restore SP: SP = RBReg + SPAdd.
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if (RBReg != SPReg || SPAdd != 0) {
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assert(!HasRedZone && "This should not happen with red zone");
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// If SPAdd is 0, generate a copy.
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if (SPAdd == 0)
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BuildMI(MBB, MBBI, dl, OrInst, SPReg)
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.addReg(RBReg)
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.addReg(RBReg);
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else
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BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
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.addReg(RBReg)
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.addImm(SPAdd);
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assert(RBReg != ScratchReg && "Should be using FP or SP as base register");
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if (RBReg == FPReg)
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BuildMI(MBB, MBBI, dl, OrInst, FPReg)
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.addReg(ScratchReg)
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.addReg(ScratchReg);
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// Now load the LR from the caller's stack frame.
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if (MustSaveLR && !LoadedLR)
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BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
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.addImm(LROffset)
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.addReg(SPReg);
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}
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if (MustSaveCR &&
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!(SingleScratchReg && MustSaveLR)) // will only occur for PPC64
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