retire cx,ctau drivers
The devices supported by these drivers are obsolete ISA cards, and the sync serial protocols they supported are essentially obsolete too. Sponsored by: The FreeBSD Foundation
This commit is contained in:
Ed Maste
parent
aad76399cf
commit
2733d8c96c
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=359178
@ -36,6 +36,10 @@
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# xargs -n1 | sort | uniq -d;
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# done
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# 20200320: cx and ctau drivers retired
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OLD_FILES+=usr/share/man/man4/ctau.4.gz
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OLD_FILES+=usr/share/man/man4/cx.4.gz
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# 20200318: host.conf was deprecated a long time ago.
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OLD_FILES+=etc/host.conf
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OLD_FILES+=etc/rc.d/nsswitch
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@ -4,8 +4,6 @@ MAN= apm.4 \
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ce.4 \
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cp.4 \
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CPU_ELAN.4 \
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ctau.4 \
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cx.4 \
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glxiic.4 \
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glxsb.4 \
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longrun.4 \
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@ -1,125 +0,0 @@
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.\" Copyright (c) 2004 Roman Kurakin <rik@cronyx.ru>
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.\" Copyright (c) 2004 Cronyx Engineering
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.\" All rights reserved.
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.\"
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.\" This software is distributed with NO WARRANTIES, not even the implied
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.\" warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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.\"
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.\" Authors grant any other persons or organisations a permission to use,
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.\" modify and redistribute this software in source and binary forms,
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.\" as long as this message is kept with the software, all derivative
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.\" works or modified versions.
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.\"
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.\" Cronyx Id: ct.4,v 1.1.2.6 2004/06/21 17:56:40 rik Exp $
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.\" $FreeBSD$
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.\"
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.Dd March 2, 2020
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.Dt CTAU 4 i386
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.Os
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.Sh NAME
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.Nm ctau
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.Nd driver for synchronous Cronyx Tau WAN adapters
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.Sh SYNOPSIS
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.Cd "device ctau"
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.Pp
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Additional options:
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.Cd "device sppp"
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.Cd "options NETGRAPH"
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.Cd "options NETGRAPH_CRONYX"
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.Pp
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In
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.Pa /boot/device.hints :
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.Cd hint.ctau.0.at="isa"
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.Cd hint.ctau.0.port="0x240"
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.Cd hint.ctau.0.irq="15"
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.Cd hint.ctau.0.drq="7"
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.Sh DEPRECATION NOTICE
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The
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.Nm
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driver is not present in
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.Fx 13.0
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and later.
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.Sh DESCRIPTION
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The
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.Nm
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driver needs either
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.Xr sppp 4
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or
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.Xr netgraph 4 .
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Which one to use is determined by the
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.Dv NETGRAPH_CRONYX
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option.
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If this option is present in your kernel configuration file, the
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.Nm
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driver will be compiled with
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.Xr netgraph 4
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support.
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Otherwise, it will be compiled with
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.Xr sppp 4
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support.
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.Pp
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The base I/O port address specified in
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.Pa /boot/device.hints
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must match the port address set by the jumpers on the board.
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The DMA I/O channel and interrupt request numbers are configured
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by software at adapter initialization.
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Legal values are:
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.Pp
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.Bl -tag -compact -width Port:
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.It Port :
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0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0,
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0x300, 0x320, 0x340, 0x360, 0x380, 0x3a0, 0x3c0, 0x3e0
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.It IRQ :
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3, 5, 7, 10, 11, 12, 15
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.It DMA :
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5, 6, 7
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.El
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.Pp
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The
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.Nm
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driver supports autodetection.
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As for all non-PNP hardware, using
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autodetection could lead to some potential problems with other devices during
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the hardware detection process.
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It is always better to specify hardware resources manually.
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.Pp
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Refer to
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.Xr sconfig 8
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for information about the
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.Nm
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adapter configuration.
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.Sh HARDWARE
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The
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.Nm
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driver supports the following cards:
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.Pp
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.Bl -bullet -compact
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.It
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Cronyx Tau (RS-232/V.35)
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.It
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Cronyx Tau/R (RS-530/RS-449)
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.It
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Cronyx Tau/E1 (fractional E1)
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.It
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Cronyx Tau/G703 (unframed E1)
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.El
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.Sh SEE ALSO
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.Xr cp 4 ,
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.Xr cx 4 ,
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.Xr sppp 4 ,
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.Xr ifconfig 8 ,
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.Xr sconfig 8 ,
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.Xr spppcontrol 8
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.Sh HISTORY
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The
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.Nm
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driver was added in
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.Fx 5.3
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and
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.Fx 4.10 .
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The
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.Nm
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driver for previous versions of
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.Fx
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is available from
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.Pa http://www.cronyx.ru/ .
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@ -1,145 +0,0 @@
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.\" Copyright (c) 2003-2004 Roman Kurakin <rik@cronyx.ru>
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.\" Copyright (c) 2003-2004 Cronyx Engineering
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.\" All rights reserved.
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.\"
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.\" This software is distributed with NO WARRANTIES, not even the implied
|
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.\" warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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.\"
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.\" Authors grant any other persons or organisations a permission to use,
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.\" modify and redistribute this software in source and binary forms,
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.\" as long as this message is kept with the software, all derivative
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.\" works or modified versions.
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.\"
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.\" Cronyx Id: cx.4,v 1.1.2.6 2004/06/21 17:56:40 rik Exp $
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.\" $FreeBSD$
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.\"
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.Dd March 2, 2020
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.Dt CX 4 i386
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.Os
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.Sh NAME
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.Nm cx
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.Nd "driver for synchronous/asynchronous Cronyx Sigma WAN adapters"
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.Sh SYNOPSIS
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To compile this driver into the kernel,
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place the following line in your
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kernel configuration file:
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.Bd -ragged -offset indent
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.Cd "device cx"
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.Ed
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.Pp
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Alternatively, to load the driver as a
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module at boot time, place the following line in
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.Xr loader.conf 5 :
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.Bd -literal -offset indent
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if_cx_load="YES"
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.Ed
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.Pp
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Additional options:
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.Cd "device sppp"
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.Cd "options NETGRAPH"
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.Cd "options NETGRAPH_CRONYX"
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.Pp
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In
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.Pa /boot/device.hints :
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.Cd hint.cx.0.at="isa"
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.Cd hint.cx.0.port="0x240"
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.Cd hint.cx.0.irq="15"
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.Cd hint.cx.0.drq="7"
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.Sh DEPRECATION NOTICE
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The
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.Nm
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driver is not present in
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.Fx 13.0
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and later.
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.Sh DESCRIPTION
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The
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.Nm
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driver needs either
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.Xr sppp 4
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or
|
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.Xr netgraph 4 .
|
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Which one to use is determined by the
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.Dv NETGRAPH_CRONYX
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option.
|
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If this option is present in your kernel configuration file, the
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.Nm
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driver will be compiled with
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.Xr netgraph 4
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support.
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Otherwise, it will be compiled with
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.Xr sppp 4
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support.
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.Pp
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The base I/O port address specified in
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.Pa /boot/device.hints
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must match the port address set by the jumpers on the board.
|
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The DMA I/O channel and interrupt request numbers are configured
|
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by software at adapter initialization.
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Legal values are:
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.Pp
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.Bl -tag -compact -width Port:
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.It Port :
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0x240, 0x260, 0x280, 0x300, 0x320, 0x380
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.It IRQ :
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3, 5, 7, 10, 11, 12, 15
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.It DMA :
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5, 6, 7
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.El
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.Pp
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The
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.Nm
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driver supports autodetection.
|
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As for all non-PNP hardware, using
|
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autodetection could lead to some potential problems with other devices during
|
||||
the hardware detection process.
|
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It is always better to specify hardware resources manually.
|
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.Pp
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Refer to
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.Xr sconfig 8
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for information about the
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.Nm
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adapter configuration.
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.Sh HARDWARE
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The
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.Nm
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driver supports the following cards:
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.Pp
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.Bl -bullet -compact
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.It
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Cronyx Sigma-22, Sigma-24
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.It
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Cronyx Sigma-100
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.It
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Cronyx Sigma-400, Sigma-401, Sigma-404, Sigma-410, Sigma-440
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.It
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Cronyx Sigma-500
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.It
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Cronyx Sigma-703
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.It
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Cronyx Sigma-800, Sigma-801, Sigma-810, Sigma-840
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.El
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.Sh SEE ALSO
|
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.Xr cp 4 ,
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.Xr ctau 4 ,
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.Xr sppp 4 ,
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.Xr ifconfig 8 ,
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.Xr sconfig 8 ,
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.Xr spppcontrol 8
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.Sh HISTORY
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The
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.Nm
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||||
driver was updated in
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.Fx 5.2
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and
|
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.Fx 4.10 .
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In most of the previous versions of
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.Fx
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the
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.Nm
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driver is out of date.
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The
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.Nm
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driver for previous versions of
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.Fx
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is available from
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.Pa http://www.cronyx.ru/ .
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@ -16,7 +16,6 @@ nodevice ti
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nodevice txp
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nodevice ce
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nodevice cp
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nodevice ctau
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nodevice ipwfw
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nodevice iwifw
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nodevice iwmfw
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@ -97,12 +97,6 @@ dev/ce/tau32-ddk.c optional ce \
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dev/cp/cpddk.c optional cp \
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compile-with "${NORMAL_C} ${NO_WMISLEADING_INDENTATION}"
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dev/cp/if_cp.c optional cp
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dev/ctau/ctau.c optional ctau
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dev/ctau/ctddk.c optional ctau
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dev/ctau/if_ct.c optional ctau
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dev/cx/csigma.c optional cx
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dev/cx/cxddk.c optional cx
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dev/cx/if_cx.c optional cx
|
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dev/glxiic/glxiic.c optional glxiic
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dev/glxsb/glxsb.c optional glxsb
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dev/glxsb/glxsb_hash.c optional glxsb
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@ -1,115 +0,0 @@
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/*-
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* AMD Am83C30 serial communication controller registers.
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*
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* Copyright (C) 1996 Cronyx Engineering.
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* Author: Serge Vakulenko, <vak@cronyx.ru>
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*
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* This software is distributed with NO WARRANTIES, not even the implied
|
||||
* warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* Authors grant any other persons or organisations permission to use
|
||||
* or modify this software as long as this message is kept with the software,
|
||||
* all derivative works or modified versions.
|
||||
*
|
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* Cronyx Id: am8530.h,v 1.1.2.2 2003/11/12 17:31:21 rik Exp $
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* $FreeBSD$
|
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*/
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|
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/*
|
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* Read/write registers.
|
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*/
|
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#define AM_IVR 2 /* rw2 - interrupt vector register */
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#define AM_DAT 8 /* rw8 - data buffer register */
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#define AM_TCL 12 /* rw12 - time constant low */
|
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#define AM_TCH 13 /* rw13 - time constant high */
|
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#define AM_SICR 15 /* rw15 - status interrupt control reg */
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|
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/*
|
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* Write only registers.
|
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*/
|
||||
#define AM_CR 0 /* w0 - command register */
|
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#define AM_IMR 1 /* w1 - interrupt mode register */
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#define AM_RCR 3 /* w3 - receive control register */
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#define AM_PMR 4 /* w4 - tx/rx parameters and modes reg */
|
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#define AM_TCR 5 /* w5 - transmit control register */
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#define AM_SAF 6 /* w6 - sync address field */
|
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#define AM_SFR 7 /* w7 - sync flag register */
|
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#define AM_MICR 9 /* w9 - master interrupt control reg */
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#define AM_MCR 10 /* w10 - misc control register */
|
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#define AM_CMR 11 /* w11 - clock mode register */
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#define AM_BCR 14 /* w14 - baud rate control register */
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/*
|
||||
* Read only registers.
|
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*/
|
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#define AM_SR 0 /* r0 - status register */
|
||||
#define AM_RSR 1 /* r1 - receive status register */
|
||||
#define AM_IPR 3 /* r3 - interrupt pending register */
|
||||
#define AM_MSR 10 /* r10 - misc status register */
|
||||
|
||||
/*
|
||||
* Enhanced mode registers.
|
||||
* In enhanced mode registers PMR(w4), TCR(w5) become readable.
|
||||
*/
|
||||
#define AM_FBCL 6 /* r6 - frame byte count low */
|
||||
#define AM_FBCH 7 /* r7 - frame byte count high */
|
||||
#define AM_RCR_R 9 /* r9 - read RCR(w3) */
|
||||
#define AM_MCR_R 11 /* r11 - read MCR(w10) */
|
||||
#define AM_SFR_R 14 /* r14 - read SFR(w7') */
|
||||
|
||||
#define AM_A 32 /* channel A offset */
|
||||
|
||||
/*
|
||||
* Interrupt vector register
|
||||
*/
|
||||
#define IVR_A 0x08 /* channel A status */
|
||||
#define IVR_REASON 0x06 /* interrupt reason mask */
|
||||
#define IVR_TXRDY 0x00 /* transmit buffer empty */
|
||||
#define IVR_STATUS 0x02 /* external status interrupt */
|
||||
#define IVR_RX 0x04 /* receive character available */
|
||||
#define IVR_RXERR 0x06 /* special receive condition */
|
||||
|
||||
/*
|
||||
* Interrupt mask register
|
||||
*/
|
||||
#define IMR_EXT 0x01 /* ext interrupt enable */
|
||||
#define IMR_TX 0x02 /* ext interrupt enable */
|
||||
#define IMR_PARITY 0x04 /* ext interrupt enable */
|
||||
|
||||
#define IMR_RX_FIRST 0x08 /* ext interrupt enable */
|
||||
#define IMR_RX_ALL 0x10 /* ext interrupt enable */
|
||||
#define IMR_RX_ERR 0x18 /* ext interrupt enable */
|
||||
|
||||
#define IMR_WD_RX 0x20 /* wait/request follows receiver fifo */
|
||||
#define IMR_WD_REQ 0x40 /* wait/request function as request */
|
||||
#define IMR_WD_ENABLE 0x80 /* wait/request pin enable */
|
||||
|
||||
/*
|
||||
* Master interrupt control register
|
||||
*/
|
||||
#define MICR_VIS 0x01 /* vector includes status */
|
||||
#define MICR_NV 0x02 /* no interrupt vector */
|
||||
#define MICR_DLC 0x04 /* disable lower chain */
|
||||
#define MICR_MIE 0x08 /* master interrupt enable */
|
||||
#define MICR_HIGH 0x10 /* status high */
|
||||
#define MICR_NINTACK 0x20 /* interrupt masking without INTACK */
|
||||
|
||||
#define MICR_RESET_A 0x80 /* channel reset A */
|
||||
#define MICR_RESET_B 0x40 /* channel reset B */
|
||||
#define MICR_RESET_HW 0xc0 /* force hardware reset */
|
||||
|
||||
/*
|
||||
* Receive status register
|
||||
*/
|
||||
#define RSR_FRME 0x10 /* framing error */
|
||||
#define RSR_RXOVRN 0x20 /* rx overrun error */
|
||||
|
||||
/*
|
||||
* Command register
|
||||
*/
|
||||
#define CR_RST_EXTINT 0x10 /* reset external/status irq */
|
||||
#define CR_TX_ABORT 0x18 /* send abort (SDLC) */
|
||||
#define CR_RX_NXTINT 0x20 /* enable irq on next rx character */
|
||||
#define CR_RST_TXINT 0x28 /* reset tx irq pending */
|
||||
#define CR_RST_ERROR 0x30 /* error reset */
|
||||
#define CR_RST_HIUS 0x38 /* reset highest irq under service */
|
||||
1796
sys/dev/ctau/ctau.c
1796
sys/dev/ctau/ctau.c
File diff suppressed because it is too large
Load Diff
@ -1,498 +0,0 @@
|
||||
/*
|
||||
* DO NOT EDIT MANUALLY!
|
||||
* This code was generated by mkfw utility
|
||||
* from the file `ctau2.dat'
|
||||
*
|
||||
* Cronyx Id: ctau2fw.h,v 1.1 2002/06/03 10:19:39 rik Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
long ctau2_fw_len = 98448;
|
||||
|
||||
const char *ctau2_fw_version = "1.0";
|
||||
const char *ctau2_fw_date = "22.08.01";
|
||||
const char *ctau2_fw_copyright = "Copyright (C) 2001 Cronyx Engineering.";
|
||||
|
||||
const unsigned char ctau2_fw_data[] = {
|
||||
79,231,255,255,98,255,57,0,0,255,255,255,255,255,255,255,255,255,255,
|
||||
255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,
|
||||
255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,
|
||||
255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,
|
||||
255,255,255,255,255,255,255,255,255,255,160,12,16,1,51,80,6,202,64,
|
||||
25,0,0,83,96,10,76,129,9,50,65,6,200,0,0,25,32,3,100,128,72,148,1,
|
||||
0,15,12,144,1,51,0,0,166,202,20,25,32,3,102,128,12,148,41,50,64,6,
|
||||
192,4,152,48,2,101,160,12,152,1,176,248,0,0,20,192,2,80,0,0,10,64,
|
||||
1,40,128,2,80,0,0,10,64,1,48,0,0,10,64,1,40,0,0,5,160,0,0,14,128,2,
|
||||
0,15,18,128,2,80,0,0,5,192,0,0,40,0,0,5,160,0,0,20,128,1,80,0,0,10,
|
||||
160,0,0,20,128,5,160,0,0,20,128,2,192,255,0,0,4,0,1,16,0,0,2,64,0,
|
||||
0,8,0,0,2,64,0,0,8,0,60,252,0,15,1,48,0,0,2,64,0,0,8,0,1,32,0,0,8,
|
||||
128,0,17,128,0,0,16,0,0,4,192,0,3,32,0,1,128,1,16,0,0,2,128,0,0,16,
|
||||
0,1,16,0,0,2,64,0,0,232,252,0,0,5,8,0,0,20,160,2,84,128,10,0,0,10,
|
||||
64,1,40,0,0,4,132,160,0,0,16,0,0,2,208,1,10,64,32,32,0,17,32,0,0,4,
|
||||
0,0,16,16,2,14,192,1,8,0,0,7,32,4,4,128,0,1,2,64,80,0,0,40,0,0,5,168,
|
||||
0,0,248,255,0,0,5,128,0,0,20,0,4,8,0,0,1,128,8,16,129,4,0,1,16,0,0,
|
||||
2,0,3,68,32,0,9,64,0,6,32,0,0,4,16,0,0,152,0,0,2,64,0,0,32,1,1,32,
|
||||
8,4,128,0,0,136,0,0,1,0,0,1,8,0,0,1,0,2,250,0,52,64,0,10,2,0,8,184,
|
||||
251,0,74,152,255,0,74,152,255,0,74,152,255,0,53,11,0,9,152,32,0,7,
|
||||
136,253,0,52,192,3,2,0,8,30,0,8,192,251,0,53,3,0,9,24,0,8,40,253,0,
|
||||
53,3,0,9,24,0,8,40,253,0,1,52,1,0,70,140,249,0,2,16,0,70,136,255,0,
|
||||
74,152,255,8,0,1,17,0,70,163,253,0,2,10,0,70,229,248,0,1,60,0,71,88,
|
||||
252,4,0,1,16,0,70,200,251,0,1,32,2,0,70,184,255,16,0,16,208,0,27,4,
|
||||
0,26,24,255,0,17,192,0,55,88,255,0,17,192,0,55,88,255,12,0,16,192,
|
||||
0,55,50,249,4,0,17,40,0,26,48,18,0,25,64,248,8,0,16,48,0,27,60,0,26,
|
||||
96,252,0,46,48,0,26,137,253,8,0,45,48,0,26,144,252,0,65,64,3,0,6,156,
|
||||
248,0,66,3,0,6,152,252,0,66,3,0,6,152,252,8,0,65,3,0,6,163,255,0,74,
|
||||
205,250,0,65,192,0,0,2,0,5,120,255,4,0,73,216,251,0,74,152,255,0,4,
|
||||
208,0,68,84,254,0,4,192,0,68,16,251,0,4,192,0,68,16,251,4,0,3,192,
|
||||
0,68,99,252,12,0,4,136,0,67,13,254,0,4,48,0,68,152,252,8,0,73,144,
|
||||
255,0,74,152,255,0,1,180,0,46,16,0,6,32,0,15,52,251,0,1,48,32,0,70,
|
||||
184,252,0,1,48,0,71,152,252,8,0,0,48,16,0,70,179,255,0,1,128,32,0,
|
||||
45,192,68,0,5,128,49,0,14,245,249,0,1,60,0,46,240,0,6,224,1,0,14,168,
|
||||
253,4,0,0,16,32,0,45,192,0,6,128,1,0,14,104,254,0,1,32,0,46,192,0,
|
||||
6,128,1,0,14,8,249,0,1,132,16,0,7,1,0,4,16,0,35,8,0,18,140,250,0,74,
|
||||
152,255,0,74,152,255,4,0,1,66,0,70,139,250,12,0,0,48,64,0,7,140,16,
|
||||
0,4,136,0,34,96,4,0,17,189,254,0,1,60,0,8,15,0,4,48,0,35,120,64,0,
|
||||
17,232,248,8,0,0,32,8,0,7,12,0,4,192,128,0,34,96,0,18,120,255,0,1,
|
||||
128,0,8,12,0,4,192,2,0,34,96,0,18,248,255,0,1,4,0,3,90,16,0,0,8,0,
|
||||
6,16,0,37,13,0,11,1,32,0,2,192,255,0,6,24,0,48,12,0,16,72,250,0,2,
|
||||
16,0,2,16,0,9,192,0,37,12,0,16,16,250,8,0,0,128,0,3,88,8,0,8,192,0,
|
||||
37,12,0,16,234,252,0,1,128,8,0,2,24,8,0,0,96,66,0,6,136,0,36,64,4,
|
||||
0,10,140,129,1,0,1,136,253,0,1,60,0,3,30,0,1,120,0,6,48,0,37,3,0,11,
|
||||
15,224,129,0,1,168,255,4,0,0,48,0,3,24,16,0,0,96,0,7,128,0,49,12,128,
|
||||
1,0,1,41,250,0,1,48,66,0,2,152,0,1,96,0,7,2,0,49,12,128,1,0,1,24,254,
|
||||
16,0,73,204,251,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,
|
||||
128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,15,32,0,0,4,128,0,0,16,
|
||||
0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,
|
||||
0,4,0,0,152,255,0,74,152,255,44,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,
|
||||
0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,15,32,0,0,
|
||||
4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,
|
||||
8,0,0,1,32,0,0,4,0,0,227,248,4,0,73,141,254,40,0,0,4,128,0,0,16,0,
|
||||
0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,
|
||||
4,0,15,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,
|
||||
0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,0,144,255,0,74,152,255,40,0,0,4,128,
|
||||
0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,
|
||||
1,32,0,0,4,0,15,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,
|
||||
128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,0,144,255,0,74,152,255,
|
||||
0,74,152,255,0,2,32,0,70,184,255,0,74,152,255,0,74,152,255,8,0,4,2,
|
||||
0,3,8,0,62,48,253,0,20,16,0,3,4,0,19,16,0,5,128,0,18,128,192,254,0,
|
||||
16,2,0,29,128,0,10,8,0,13,48,255,0,15,128,0,3,8,0,3,4,0,19,8,128,0,
|
||||
5,1,0,3,4,0,13,137,251,0,2,8,0,6,8,0,4,16,0,3,1,0,37,4,0,2,34,0,0,
|
||||
5,0,6,48,252,0,2,8,0,16,64,0,44,1,0,6,208,254,0,10,64,0,48,32,0,11,
|
||||
128,48,249,0,7,2,0,65,184,255,0,74,152,255,0,6,4,0,66,152,251,0,1,
|
||||
16,0,71,152,254,0,74,152,255,0,74,152,255,0,74,152,255,0,74,152,255,
|
||||
0,74,152,255,0,74,152,255,0,69,1,0,3,152,254,0,74,152,255,0,1,64,0,
|
||||
71,220,255,0,74,152,255,0,74,152,255,0,74,152,255,0,1,32,0,54,32,0,
|
||||
15,184,255,0,6,16,0,38,8,0,26,8,254,0,1,16,0,52,32,0,17,152,252,0,
|
||||
2,8,0,61,32,0,7,244,251,0,2,4,0,14,16,0,54,200,250,0,2,64,0,70,216,
|
||||
255,0,74,152,255,2,0,52,128,0,19,26,255,2,0,3,2,0,50,1,0,2,8,0,13,
|
||||
252,2,0,4,32,4,0,5,32,0,38,2,0,10,128,0,6,128,146,251,0,1,160,0,1,
|
||||
2,128,2,0,3,40,0,1,1,0,31,6,0,3,64,0,1,12,2,0,2,16,0,3,64,0,7,88,255,
|
||||
0,1,40,0,3,10,0,0,130,80,0,0,12,0,0,1,32,0,1,16,0,4,16,0,0,1,0,22,
|
||||
128,32,0,2,144,0,0,128,8,0,1,1,0,5,144,0,1,128,0,2,176,253,0,6,8,0,
|
||||
1,2,0,0,8,0,10,64,0,25,32,0,18,128,0,2,240,253,0,1,16,0,4,128,0,0,
|
||||
16,0,0,2,64,0,0,8,0,9,4,0,22,32,0,23,40,251,0,6,64,0,66,216,251,0,
|
||||
12,8,0,60,16,255,0,74,152,255,4,0,55,4,0,16,137,254,8,0,73,178,253,
|
||||
0,49,64,0,20,2,0,1,184,249,0,74,152,255,0,67,1,0,4,128,0,0,255,0,74,
|
||||
152,255,0,1,192,0,15,2,0,54,16,249,0,74,152,255,0,74,152,255,0,44,
|
||||
32,0,14,128,0,12,176,255,0,74,152,255,0,45,128,0,14,6,0,11,240,255,
|
||||
0,44,128,5,0,14,6,0,11,120,250,0,61,6,4,0,10,184,251,0,44,96,128,0,
|
||||
13,128,7,0,11,136,255,0,61,6,0,11,248,255,0,45,4,1,0,13,70,2,0,10,
|
||||
200,253,0,25,160,1,0,16,32,0,21,8,0,5,228,248,0,25,128,1,0,47,254,
|
||||
0,44,128,129,0,27,16,254,8,0,44,4,0,27,163,248,0,67,96,34,0,4,205,
|
||||
254,0,25,96,0,0,1,0,15,96,128,0,20,120,0,5,112,255,4,0,66,96,0,5,216,
|
||||
253,0,26,144,0,17,4,1,0,19,96,0,5,24,253,16,0,8,104,68,0,5,208,0,55,
|
||||
240,253,0,9,96,0,6,192,0,55,56,249,0,9,64,0,6,192,0,55,24,251,12,0,
|
||||
8,96,33,0,5,192,0,55,66,253,4,0,8,96,4,0,6,72,0,54,48,249,8,0,8,120,
|
||||
64,0,5,48,0,55,88,252,0,9,96,64,0,62,233,252,8,0,8,96,2,0,62,208,249,
|
||||
16,0,0,52,0,6,104,68,0,8,64,35,4,0,36,128,194,0,11,224,251,0,1,48,
|
||||
0,6,96,0,63,248,250,0,1,48,0,6,64,0,50,2,0,11,248,248,12,0,0,48,0,
|
||||
6,96,33,0,9,32,4,0,37,64,4,0,10,162,252,4,0,1,33,0,5,96,4,0,9,32,0,
|
||||
38,32,4,0,10,168,248,8,0,0,12,0,6,120,64,0,8,192,3,2,0,36,128,5,0,
|
||||
11,16,255,0,9,96,64,0,49,6,0,11,137,252,8,0,8,96,2,0,9,10,1,0,37,38,
|
||||
1,0,10,56,248,16,0,19,64,35,4,0,36,128,0,12,228,250,0,74,152,255,0,
|
||||
62,4,0,10,216,251,12,0,20,32,4,0,37,22,0,11,227,251,4,0,20,32,0,38,
|
||||
70,2,0,10,169,254,0,20,192,3,2,0,36,128,7,0,11,102,250,0,61,6,0,11,
|
||||
248,255,16,0,20,10,1,0,37,6,8,0,10,120,253,16,0,6,64,3,0,1,1,0,34,
|
||||
128,0,3,64,0,6,128,0,12,32,253,0,8,3,0,64,168,252,0,8,3,0,1,12,0,49,
|
||||
2,0,10,192,250,12,0,7,3,0,1,128,8,0,34,64,8,0,2,35,4,0,5,16,0,11,26,
|
||||
248,4,0,7,32,2,0,0,12,0,35,32,2,0,2,16,1,0,5,32,0,11,160,252,8,0,6,
|
||||
192,0,2,15,4,0,33,128,7,0,2,192,0,6,128,1,4,0,10,48,255,0,8,3,0,1,
|
||||
12,4,0,60,241,253,8,0,7,83,0,1,12,0,35,32,8,0,2,16,4,0,5,6,8,0,10,
|
||||
96,254,0,24,1,32,0,25,64,0,3,32,0,0,4,128,34,16,0,10,132,248,0,25,
|
||||
128,1,0,34,4,0,10,64,250,0,25,128,1,0,25,3,0,6,2,1,0,11,252,4,0,24,
|
||||
128,5,2,0,24,32,4,0,5,64,0,11,19,255,12,0,23,44,128,1,0,25,16,1,0,
|
||||
1,128,49,48,1,16,200,16,0,9,17,254,0,24,15,232,1,1,0,23,192,0,3,224,
|
||||
1,60,144,5,240,0,10,94,255,8,0,23,12,128,1,0,29,128,1,48,0,0,6,192,
|
||||
0,10,8,250,0,24,12,128,145,0,25,16,4,0,1,128,1,48,0,0,38,193,0,10,
|
||||
144,253,0,6,2,0,3,1,0,1,4,0,9,160,48,0,16,32,0,0,4,0,3,2,64,3,8,0,
|
||||
3,4,128,38,0,2,64,0,2,1,32,0,0,4,0,0,192,254,0,26,1,0,25,3,0,7,2,0,
|
||||
10,152,255,0,26,129,0,17,128,0,6,3,0,6,6,1,0,10,64,252,8,0,25,17,0,
|
||||
17,4,0,6,3,0,0,132,0,4,16,0,11,74,250,0,6,24,1,0,2,76,0,1,176,0,10,
|
||||
5,1,0,17,48,2,0,2,24,16,136,96,34,0,2,48,34,66,0,3,35,4,0,0,76,144,
|
||||
17,48,64,168,249,0,6,30,8,0,2,15,8,0,0,60,32,0,8,224,0,17,96,128,60,
|
||||
32,0,2,30,192,0,0,24,0,3,60,128,7,4,0,1,192,3,0,1,15,224,129,60,0,
|
||||
0,8,250,4,0,5,24,0,3,12,0,1,48,0,9,128,64,0,16,128,129,48,0,3,24,0,
|
||||
6,48,0,0,6,4,0,2,3,0,1,12,128,1,48,0,0,193,253,0,6,24,0,3,12,0,1,48,
|
||||
0,9,128,0,19,48,0,3,24,0,2,130,0,2,48,0,0,38,0,3,3,0,1,12,128,1,48,
|
||||
0,0,176,255,16,0,73,204,251,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,
|
||||
1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,15,32,0,0,4,
|
||||
128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,
|
||||
0,0,1,32,0,0,4,0,0,152,255,0,74,152,255,44,0,0,4,128,0,0,16,0,0,2,
|
||||
64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,
|
||||
15,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,
|
||||
0,2,64,0,0,8,0,0,1,32,0,0,4,0,0,227,248,4,0,73,201,250,32,0,0,4,128,
|
||||
0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,
|
||||
1,32,0,0,4,0,15,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,
|
||||
128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,0,254,249,4,0,73,216,251,
|
||||
32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,
|
||||
64,0,0,8,0,0,1,32,0,0,4,0,15,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,
|
||||
0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,0,152,255,
|
||||
0,6,32,0,66,184,253,0,74,152,255,0,74,152,255,12,0,48,8,0,3,4,128,
|
||||
0,5,4,0,10,152,251,0,73,32,152,253,0,62,16,0,3,2,0,5,168,255,2,0,10,
|
||||
4,0,2,128,0,3,16,0,3,36,0,19,8,8,0,7,2,0,12,2,0,2,40,249,0,3,4,0,11,
|
||||
2,0,7,8,0,29,8,0,9,8,0,5,176,251,0,0,3,0,0,134,0,4,6,0,1,2,0,2,128,
|
||||
1,0,2,8,0,3,76,0,1,8,0,16,8,24,0,7,3,0,9,8,0,1,4,0,3,249,0,0,3,0,2,
|
||||
128,0,0,16,0,3,160,3,0,2,16,0,2,64,1,0,5,1,0,16,68,1,0,8,128,0,2,2,
|
||||
16,1,0,4,64,0,3,216,254,0,12,2,0,7,1,0,34,64,0,2,2,0,10,128,52,252,
|
||||
142,0,3,128,0,0,16,0,4,8,0,59,128,232,248,0,71,2,0,1,184,253,0,74,
|
||||
152,255,0,10,32,0,13,32,0,22,4,0,3,2,64,0,17,216,249,0,21,2,0,51,152,
|
||||
253,0,61,4,0,11,216,255,0,74,152,255,0,12,2,0,30,128,0,28,24,253,0,
|
||||
73,128,50,253,0,27,2,0,45,152,253,0,74,152,255,0,57,32,0,0,32,0,13,
|
||||
152,253,0,10,1,0,62,136,255,0,74,220,251,0,70,16,0,1,128,16,254,0,
|
||||
22,1,0,23,16,0,25,152,255,0,45,64,0,27,216,251,0,61,128,1,0,11,254,
|
||||
16,0,8,64,0,11,2,0,2,128,0,46,74,249,0,26,1,0,33,2,0,11,168,254,0,
|
||||
25,2,0,32,128,0,6,32,0,5,56,253,0,73,128,16,255,0,7,64,0,2,16,0,32,
|
||||
2,0,14,1,0,11,152,249,0,61,16,0,11,152,254,0,11,2,0,31,64,0,28,248,
|
||||
253,0,1,8,32,0,0,2,0,3,64,0,10,128,0,23,8,16,0,3,64,0,0,16,0,1,64,
|
||||
0,2,1,0,10,16,128,251,18,0,2,128,0,46,8,0,0,2,0,4,8,0,1,4,0,9,128,
|
||||
234,249,0,1,8,16,0,0,6,0,3,16,0,11,1,0,0,4,0,20,24,16,0,2,2,192,0,
|
||||
0,16,0,0,132,193,0,0,20,0,0,3,4,0,8,160,16,224,254,0,1,32,0,3,2,0,
|
||||
0,64,5,0,0,5,85,2,0,1,4,0,1,16,0,1,64,16,0,0,128,0,19,132,0,0,128,
|
||||
128,0,0,82,128,0,2,32,0,1,20,0,0,18,0,0,40,0,0,66,0,2,2,64,2,128,0,
|
||||
1,252,0,11,8,0,10,64,0,0,128,0,32,8,0,0,2,0,0,32,0,9,80,253,0,1,32,
|
||||
0,5,128,0,2,2,0,2,1,0,1,4,0,1,16,0,25,33,0,0,4,0,12,2,0,7,120,250,
|
||||
0,10,1,0,62,136,255,2,0,16,32,0,54,128,16,253,0,60,128,0,12,144,255,
|
||||
8,0,73,178,253,8,0,73,144,255,0,2,4,0,11,8,0,57,80,251,0,74,152,255,
|
||||
2,0,73,184,253,0,62,10,0,10,176,253,0,8,8,0,12,4,0,1,128,0,21,2,0,
|
||||
3,1,32,0,5,128,0,11,224,254,0,26,32,0,23,64,0,21,248,251,0,74,152,
|
||||
255,160,1,0,15,192,136,146,0,3,13,0,48,88,250,0,1,1,0,17,4,0,2,12,
|
||||
0,48,64,255,0,17,240,0,1,4,0,2,15,0,48,160,252,128,1,1,0,14,16,2,1,
|
||||
1,0,2,13,0,48,144,248,128,8,0,18,4,0,2,128,2,0,47,248,251,96,1,1,0,
|
||||
14,224,0,0,6,0,3,2,0,48,104,252,0,0,65,0,18,4,0,52,152,254,128,8,0,
|
||||
15,192,0,5,1,0,48,80,254,0,17,208,68,18,1,0,35,160,49,0,14,68,250,
|
||||
0,19,8,4,0,52,88,251,0,18,64,14,0,36,128,1,0,14,32,251,8,0,16,192,
|
||||
0,0,18,0,37,128,0,14,203,253,0,17,64,8,16,0,36,128,0,15,73,255,0,17,
|
||||
176,64,8,0,36,224,1,1,0,13,230,250,4,0,16,128,0,0,8,0,36,128,1,0,14,
|
||||
192,251,0,17,64,36,16,0,36,128,41,0,14,96,250,16,0,3,192,4,0,10,192,
|
||||
4,2,0,4,128,17,1,0,27,13,0,16,112,254,0,5,64,0,11,64,0,36,12,0,16,
|
||||
208,255,0,4,240,64,0,10,240,0,0,22,0,4,224,129,0,28,12,0,16,144,250,
|
||||
12,0,3,16,4,0,10,16,2,11,0,4,32,0,29,12,0,16,90,248,4,0,18,12,0,35,
|
||||
128,1,0,15,152,250,8,0,3,224,0,11,224,0,0,16,0,4,192,1,0,28,3,0,16,
|
||||
80,254,0,17,16,0,0,16,0,53,153,255,8,0,3,192,0,11,192,0,0,8,0,4,128,
|
||||
1,0,46,192,250,176,80,0,17,2,0,33,8,0,18,208,250,0,0,1,0,72,152,254,
|
||||
0,0,1,0,17,22,0,53,248,255,12,9,1,0,16,10,0,53,202,248,4,9,2,0,16,
|
||||
12,0,33,96,1,0,17,192,252,224,0,18,16,0,33,120,64,0,17,128,253,132,
|
||||
128,0,17,16,0,33,96,0,18,33,253,128,8,0,17,8,0,33,96,0,18,112,249,
|
||||
16,0,16,16,66,2,0,53,188,253,0,74,152,255,0,17,48,32,22,0,53,232,252,
|
||||
12,0,16,16,0,0,10,0,53,83,248,4,0,18,12,0,53,9,250,8,0,16,176,64,16,
|
||||
0,53,66,248,0,17,192,32,16,0,53,120,252,8,0,16,208,8,8,0,53,106,253,
|
||||
0,14,4,0,1,192,136,2,0,1,8,0,0,1,0,26,64,0,20,56,254,0,74,152,255,
|
||||
0,17,240,0,0,22,0,1,96,64,0,49,72,248,4,0,14,4,0,0,16,8,11,0,2,2,0,
|
||||
49,242,255,12,0,14,18,0,2,12,0,2,2,64,8,0,26,19,4,0,18,192,249,0,14,
|
||||
12,0,1,224,0,0,16,0,1,120,32,3,0,26,192,3,0,19,40,249,8,0,13,48,0,
|
||||
3,16,0,3,12,8,0,26,3,0,19,137,248,0,14,128,32,0,0,192,0,0,8,0,1,96,
|
||||
10,76,0,27,3,0,19,168,250,128,17,1,0,12,128,0,0,16,34,2,0,3,13,0,38,
|
||||
2,0,8,168,250,0,24,12,0,48,16,251,224,129,0,15,128,128,22,0,3,3,0,
|
||||
48,152,252,44,4,0,16,4,10,0,3,1,0,48,65,251,4,0,15,22,0,0,8,12,0,4,
|
||||
2,0,37,152,16,0,7,251,248,192,1,0,13,128,7,50,128,16,0,3,3,0,38,30,
|
||||
0,8,216,255,4,0,15,6,0,1,16,0,43,24,0,8,26,249,128,1,0,14,6,0,0,130,
|
||||
8,0,3,32,4,0,37,24,0,8,16,255,128,17,1,0,9,160,1,0,2,16,0,0,18,64,
|
||||
0,2,1,0,18,32,0,14,128,0,0,16,0,1,64,0,7,40,253,0,12,128,1,0,4,8,0,
|
||||
54,255,224,1,0,10,128,1,0,3,128,22,0,3,15,0,48,128,248,36,0,0,2,0,
|
||||
9,128,1,0,3,2,10,0,3,13,0,48,202,254,12,0,12,4,0,4,12,0,0,35,2,0,0,
|
||||
12,2,0,17,128,137,0,14,22,194,2,0,1,35,2,0,5,120,255,192,1,0,10,96,
|
||||
128,0,2,240,64,16,192,3,0,1,14,0,18,224,1,0,13,128,7,240,64,0,0,192,
|
||||
3,0,6,160,254,8,0,11,128,1,0,3,32,8,0,0,3,0,1,13,2,0,17,128,1,0,14,
|
||||
6,192,0,2,3,0,6,177,248,128,1,0,10,128,9,1,0,2,8,16,0,0,3,0,1,13,0,
|
||||
18,128,1,0,14,6,192,0,2,3,0,6,176,250,16,0,23,32,2,0,47,204,249,32,
|
||||
0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,1,128,2,64,0,
|
||||
0,8,0,1,32,0,0,4,0,15,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,
|
||||
0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,0,128,254,0,25,4,
|
||||
0,47,216,255,44,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,
|
||||
0,2,3,64,0,0,8,0,0,32,32,0,0,4,0,15,32,0,0,4,128,0,0,16,0,0,2,64,0,
|
||||
0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,0,195,
|
||||
251,4,8,0,17,1,2,0,3,2,8,0,46,29,252,0,0,128,4,128,0,1,64,2,64,0,0,
|
||||
8,0,0,1,32,0,0,4,128,0,2,2,64,0,0,8,0,0,1,0,0,128,4,0,15,32,0,0,4,
|
||||
128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,
|
||||
0,0,1,32,0,0,4,0,0,96,252,4,0,0,1,0,15,128,0,0,8,0,3,4,0,47,136,251,
|
||||
32,16,4,128,0,1,132,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,8,64,64,0,
|
||||
0,8,0,0,32,32,8,5,0,15,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,
|
||||
0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,0,200,253,0,74,152,
|
||||
255,0,1,2,0,71,184,255,0,0,64,0,2,32,0,8,4,0,1,64,1,0,54,216,252,0,
|
||||
0,128,1,0,12,8,0,57,8,255,0,4,128,0,11,128,0,55,144,255,8,0,73,144,
|
||||
255,0,0,1,16,4,0,1,64,0,1,2,0,7,2,0,1,64,0,5,4,32,0,30,8,0,12,80,253,
|
||||
0,3,2,0,11,2,0,7,2,0,18,128,0,0,32,0,5,32,0,18,144,255,68,0,0,8,144,
|
||||
20,0,0,64,0,0,128,6,0,4,96,128,20,2,20,0,0,128,96,0,1,64,9,5,8,16,
|
||||
0,16,1,32,12,0,4,8,0,4,16,0,5,192,0,5,104,249,0,1,208,0,0,16,0,11,
|
||||
16,0,0,32,2,4,165,0,31,32,1,0,3,1,0,7,8,0,3,208,248,2,0,0,16,0,15,
|
||||
32,0,0,4,129,0,31,32,0,18,180,253,0,69,8,0,2,128,220,251,0,74,152,
|
||||
255,0,19,1,0,33,4,0,18,136,251,0,74,152,255,0,13,128,0,3,32,0,54,48,
|
||||
253,2,0,17,16,0,3,1,32,0,31,32,0,14,128,48,253,2,0,72,128,48,253,128,
|
||||
0,60,2,0,11,56,255,20,0,73,234,249,0,18,2,1,0,53,136,253,2,0,73,184,
|
||||
253,0,0,1,0,16,128,0,6,1,0,45,128,76,251,0,5,1,0,11,64,0,54,200,250,
|
||||
0,74,152,255,0,74,152,255,0,74,152,255,0,13,1,0,9,8,1,0,31,128,0,14,
|
||||
152,255,0,74,152,255,0,44,128,0,28,24,255,0,74,152,255,0,16,4,0,0,
|
||||
1,0,5,64,0,35,128,0,1,2,0,7,120,248,2,0,17,64,8,0,3,4,0,47,128,240,
|
||||
253,0,17,32,128,0,2,8,0,50,48,255,0,74,152,255,0,0,4,0,12,8,0,2,2,
|
||||
0,6,4,0,29,32,0,15,240,255,40,0,0,8,0,1,2,0,3,64,0,1,8,0,0,8,16,0,
|
||||
2,2,0,0,128,0,41,4,0,7,128,32,250,10,0,21,64,0,20,64,0,0,4,0,11,8,
|
||||
0,12,128,48,249,64,0,0,8,0,1,2,0,3,16,0,1,4,0,0,8,16,2,0,1,4,0,1,9,
|
||||
0,20,32,3,4,0,11,4,0,0,192,128,2,84,0,8,232,255,32,0,0,16,0,1,128,
|
||||
0,5,4,129,0,1,40,10,0,1,34,0,0,18,0,0,64,9,0,0,1,0,16,128,0,8,2,0,
|
||||
4,8,0,0,80,2,0,0,128,0,7,64,248,0,1,32,0,8,8,128,0,1,8,2,0,26,128,
|
||||
0,14,32,0,0,32,0,10,176,255,0,4,32,0,6,8,0,6,128,0,2,4,64,0,47,144,
|
||||
253,0,56,1,0,16,136,254,0,21,8,0,43,8,0,6,152,255,2,0,57,2,0,13,128,
|
||||
16,253,0,74,152,255,0,73,128,16,255,0,74,152,255,0,74,152,255,8,0,
|
||||
73,144,255,64,128,0,20,64,0,50,208,251,0,0,32,0,3,64,0,10,64,16,2,
|
||||
0,5,128,0,27,16,0,17,8,253,0,74,152,255,0,74,152,255,0,15,128,32,4,
|
||||
0,6,160,81,0,46,24,250,0,26,1,0,46,136,254,0,16,6,0,7,224,0,47,112,
|
||||
249,0,16,70,2,0,6,32,5,1,0,45,136,255,0,16,38,2,0,6,128,1,0,46,64,
|
||||
254,0,15,128,3,0,7,192,1,1,0,45,56,251,0,16,6,0,7,128,1,0,46,96,254,
|
||||
0,16,166,0,7,128,17,1,0,45,248,253,0,14,52,0,6,8,0,3,4,0,35,2,0,8,
|
||||
12,251,0,14,48,0,58,168,255,0,22,24,0,3,48,0,45,40,253,8,0,21,8,0,
|
||||
3,48,0,45,19,255,0,14,48,10,0,5,96,33,0,3,32,0,34,24,3,0,7,245,255,
|
||||
0,14,60,0,6,120,0,3,12,0,35,30,0,8,8,249,4,0,13,48,16,0,5,96,0,4,8,
|
||||
0,34,24,0,8,248,253,0,14,48,1,0,5,96,0,40,24,0,8,40,249,16,0,24,32,
|
||||
0,19,176,16,0,7,44,4,0,0,4,0,13,56,250,0,25,128,1,0,47,254,0,25,96,
|
||||
64,0,18,60,32,0,7,15,0,16,64,253,12,0,24,32,16,0,18,4,2,0,7,33,8,0,
|
||||
1,33,0,12,26,251,20,0,24,128,9,2,0,31,64,0,12,24,252,0,25,224,1,0,
|
||||
18,56,0,8,14,0,1,12,0,13,160,249,0,74,137,254,0,26,40,0,18,48,0,8,
|
||||
12,0,1,176,64,0,12,8,252,0,14,48,34,0,40,32,0,15,168,253,0,57,128,
|
||||
1,0,14,128,255,0,14,60,0,42,128,0,14,104,251,8,0,13,4,32,0,41,16,0,
|
||||
14,225,249,0,59,1,0,13,187,253,0,14,56,0,41,96,0,15,192,249,4,0,73,
|
||||
250,249,0,14,48,0,43,1,0,13,184,254,0,4,192,66,0,2,96,33,0,2,48,34,
|
||||
0,5,104,68,0,0,160,16,0,46,8,253,0,22,64,0,3,1,0,45,152,250,0,4,240,
|
||||
128,0,2,120,32,0,2,60,0,6,96,32,0,0,224,0,47,184,249,8,0,3,16,2,0,
|
||||
2,8,2,0,2,4,34,0,5,96,4,0,0,32,72,0,46,97,249,0,22,96,2,0,0,128,5,
|
||||
0,46,83,253,0,4,224,0,3,112,0,3,56,0,6,120,64,0,0,192,129,0,46,128,
|
||||
252,4,0,21,96,0,50,250,255,0,4,192,0,3,96,0,3,48,0,6,96,36,0,1,17,
|
||||
2,0,45,32,252,0,12,160,1,4,0,6,104,0,0,77,40,144,0,24,64,0,2,1,0,12,
|
||||
32,0,2,168,251,0,12,128,1,48,0,6,96,0,50,176,249,0,12,224,1,0,0,8,
|
||||
0,6,64,12,224,1,0,25,3,0,17,1,0,0,8,248,12,0,11,160,1,0,0,2,0,6,4,
|
||||
132,176,145,0,25,3,0,15,128,5,0,1,81,254,4,0,12,68,48,8,0,6,2,8,132,
|
||||
69,0,25,3,0,1,140,0,13,48,0,1,171,252,0,12,96,0,0,60,0,6,120,32,15,
|
||||
224,0,25,192,3,1,0,0,15,8,0,11,96,0,2,104,252,4,0,13,48,0,8,8,128,
|
||||
1,0,28,12,0,12,128,129,0,1,138,253,0,14,48,16,0,6,128,76,132,73,0,
|
||||
26,4,0,0,12,0,12,128,5,0,1,240,250,16,0,0,4,0,1,192,2,0,7,4,1,0,5,
|
||||
104,1,0,0,32,144,4,0,25,96,33,0,2,4,0,8,13,0,3,220,252,0,5,128,0,8,
|
||||
8,0,6,32,0,44,12,0,3,56,251,0,4,240,0,8,48,0,6,96,0,30,120,0,13,12,
|
||||
0,3,80,253,12,0,3,16,2,1,0,6,48,16,0,5,32,10,0,1,144,0,26,8,64,0,3,
|
||||
33,0,7,12,0,3,123,248,4,0,0,48,32,0,11,33,0,5,64,18,0,0,128,137,48,
|
||||
2,0,30,64,0,7,140,16,0,2,57,255,0,1,60,0,1,224,0,8,12,0,6,120,0,1,
|
||||
224,0,0,60,16,0,24,112,0,3,12,0,8,15,0,3,152,253,4,0,0,48,0,11,32,
|
||||
8,0,5,64,0,2,64,0,31,48,0,13,17,253,0,1,48,0,1,192,0,8,128,0,6,96,
|
||||
34,0,1,4,0,0,33,0,24,96,0,3,128,64,0,7,64,4,0,2,96,252,32,0,3,16,0,
|
||||
8,52,0,3,2,64,0,0,8,0,1,160,1,4,0,19,32,210,0,5,1,32,0,0,52,0,13,120,
|
||||
253,0,14,48,0,9,128,1,0,20,6,0,9,48,0,14,248,128,1,1,0,1,192,128,0,
|
||||
12,6,0,1,96,0,1,128,129,48,0,18,128,1,0,8,128,48,0,13,112,255,132,
|
||||
17,0,2,192,8,0,12,2,0,1,96,33,0,0,128,1,48,18,0,17,128,6,4,132,0,5,
|
||||
128,17,48,0,13,90,250,140,1,0,2,192,0,8,176,0,3,24,1,32,96,18,0,1,
|
||||
68,48,2,0,18,6,0,1,1,0,3,44,0,1,1,10,0,12,8,255,96,128,0,2,48,64,0,
|
||||
7,60,16,0,2,28,208,0,0,25,0,1,224,1,12,8,0,18,1,48,0,5,15,104,0,0,
|
||||
12,0,13,16,253,136,1,0,2,192,0,8,48,0,3,24,0,0,3,98,0,1,128,1,48,0,
|
||||
19,6,0,6,12,0,16,249,255,128,17,2,0,1,192,8,1,0,6,176,32,0,2,24,0,
|
||||
0,35,96,10,0,0,128,73,48,5,0,20,2,1,0,3,12,0,1,1,0,13,120,248,16,0,
|
||||
73,204,251,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,
|
||||
0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,15,32,0,0,4,128,0,0,16,0,0,2,
|
||||
64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,
|
||||
0,152,255,0,74,152,255,44,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,
|
||||
0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,15,32,0,0,4,128,0,
|
||||
0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,
|
||||
32,0,0,4,0,0,227,248,20,0,4,128,0,3,65,0,3,6,0,3,1,0,4,8,1,0,17,128,
|
||||
32,16,4,0,4,65,32,8,0,15,17,253,40,0,0,4,128,0,2,2,64,0,2,1,0,2,128,
|
||||
0,0,16,0,0,2,72,0,2,1,0,1,4,0,15,32,0,3,16,0,0,2,64,0,3,32,0,0,4,128,
|
||||
0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,0,168,251,0,5,128,0,3,64,0,
|
||||
3,16,0,3,8,0,1,16,0,1,128,0,19,16,0,0,2,0,4,32,0,0,4,0,15,177,253,
|
||||
32,0,0,4,128,0,1,8,2,64,0,1,4,1,32,136,4,128,0,0,16,0,0,64,64,0,0,
|
||||
8,1,1,0,0,4,4,0,15,32,0,3,16,0,0,2,64,0,3,32,0,0,4,128,0,0,16,0,0,
|
||||
2,64,0,0,8,0,0,1,32,0,0,4,0,0,120,252,0,4,64,0,3,32,0,4,8,4,0,8,1,
|
||||
32,0,17,16,0,6,32,0,0,4,0,12,128,0,2,168,253,0,22,96,0,33,2,0,15,152,
|
||||
251,0,1,128,0,3,1,0,1,16,0,3,4,0,11,128,0,45,72,251,0,0,2,0,20,128,
|
||||
0,0,16,0,21,4,0,1,64,0,8,16,0,12,16,249,0,22,64,0,50,152,251,0,48,
|
||||
2,0,24,152,253,0,0,1,0,0,4,0,3,64,0,5,32,0,6,2,0,1,8,64,0,18,16,0,
|
||||
8,4,0,8,128,0,6,20,255,0,17,1,128,0,5,130,0,20,32,0,18,64,0,3,32,0,
|
||||
0,40,248,64,0,1,16,0,1,24,0,0,128,0,0,192,0,3,8,0,0,160,4,128,0,2,
|
||||
1,0,0,64,45,168,0,17,48,168,32,0,7,42,0,1,160,0,6,9,0,3,4,0,0,208,
|
||||
252,0,15,8,0,2,8,0,3,64,0,1,16,8,0,16,32,0,9,32,0,7,16,0,1,4,0,0,1,
|
||||
0,1,96,254,0,15,8,0,2,2,0,6,32,8,0,39,8,0,3,9,252,8,0,45,4,0,23,1,
|
||||
0,1,132,250,0,15,16,0,32,2,0,4,32,0,0,4,0,15,168,248,0,74,152,255,
|
||||
0,14,64,0,4,8,0,0,32,0,2,128,0,23,1,0,7,64,0,12,16,248,0,25,32,0,47,
|
||||
152,253,0,5,2,0,3,8,0,35,4,128,0,5,8,0,0,1,0,11,32,32,0,1,208,250,
|
||||
0,69,16,0,3,136,254,0,74,152,255,6,0,53,2,0,18,248,251,0,5,16,0,67,
|
||||
136,255,0,13,2,0,59,184,255,8,0,13,8,0,10,64,0,46,216,255,0,14,32,
|
||||
0,7,64,0,45,8,0,2,120,255,0,74,152,255,0,74,152,255,0,74,152,255,0,
|
||||
26,33,0,46,168,254,0,74,152,255,0,27,2,0,45,152,253,0,27,64,0,29,4,
|
||||
0,14,152,251,0,0,32,0,3,16,0,3,8,0,2,8,0,0,128,0,5,8,0,0,65,0,1,16,
|
||||
0,16,8,0,0,1,0,4,16,0,0,2,128,0,15,8,250,16,0,18,40,0,0,4,0,0,16,2,
|
||||
128,0,47,178,249,0,5,1,0,67,136,254,0,74,152,255,0,14,128,0,7,1,0,
|
||||
49,8,254,8,0,0,4,160,0,10,4,8,0,4,1,0,2,128,0,1,8,0,14,32,0,8,32,0,
|
||||
6,4,0,9,128,60,248,26,0,21,16,0,22,4,0,26,194,254,128,0,0,8,16,163,
|
||||
0,9,104,21,0,3,128,0,0,40,0,1,64,5,0,0,21,0,14,64,0,0,4,0,6,80,1,0,
|
||||
2,160,0,1,2,0,3,64,1,0,3,5,88,250,0,0,5,16,0,0,48,16,0,4,16,18,2,64,
|
||||
8,5,0,4,9,8,0,0,4,136,4,4,1,0,18,2,32,0,2,128,0,0,164,2,64,2,128,0,
|
||||
7,1,0,3,1,72,249,0,1,32,0,7,64,0,0,8,64,0,6,1,0,1,1,128,0,21,2,0,3,
|
||||
128,0,19,24,255,128,0,14,32,0,57,56,253,0,64,2,0,8,184,255,2,0,72,
|
||||
128,48,253,16,0,73,204,251,0,1,2,0,3,1,0,7,8,0,5,8,0,1,16,64,4,0,24,
|
||||
4,0,19,176,255,0,74,220,251,0,15,128,0,57,144,255,0,74,152,255,10,
|
||||
0,73,176,253,0,50,128,0,6,128,0,0,32,0,12,176,253,0,5,32,0,8,4,2,0,
|
||||
3,64,0,2,128,128,0,45,128,88,255,0,74,152,255,0,74,152,255,0,19,2,
|
||||
0,43,2,0,8,152,255,0,64,24,0,8,24,254,0,19,30,0,44,16,0,7,104,254,
|
||||
0,19,26,0,43,152,0,8,48,255,0,19,24,1,0,42,88,16,0,7,152,250,0,19,
|
||||
28,8,0,42,6,0,8,48,254,0,19,24,0,43,24,8,0,7,144,255,0,19,152,4,0,
|
||||
42,24,0,8,80,251,0,14,52,0,58,232,251,0,14,48,0,58,168,255,0,14,48,
|
||||
16,0,57,184,254,8,0,13,48,2,0,57,177,252,0,15,18,0,57,187,255,0,14,
|
||||
60,0,58,224,251,4,0,13,48,32,0,57,234,251,0,14,48,2,0,57,168,253,16,
|
||||
0,73,136,255,0,74,152,255,0,74,152,255,12,0,73,242,249,20,0,73,200,
|
||||
251,8,0,73,144,255,0,74,137,254,0,74,152,255,0,64,26,0,8,124,250,0,
|
||||
64,24,0,8,24,254,0,64,24,16,0,7,8,254,8,0,63,152,0,8,171,253,0,64,
|
||||
88,16,0,7,25,251,0,64,30,0,8,120,254,4,0,63,24,8,0,7,65,251,0,74,152,
|
||||
255,0,1,52,17,0,42,4,0,26,220,249,0,1,32,0,71,152,253,0,1,48,0,43,
|
||||
48,0,26,152,255,4,0,0,176,64,0,42,128,32,0,25,139,251,12,0,0,128,32,
|
||||
0,43,2,0,25,73,248,0,1,60,0,43,12,32,0,25,184,252,8,0,0,48,16,0,70,
|
||||
145,253,0,1,48,0,44,17,0,25,152,253,0,9,8,0,6,208,0,2,16,0,23,4,0,
|
||||
11,4,0,13,208,250,0,17,192,0,2,3,1,0,50,72,252,0,10,32,0,5,192,0,1,
|
||||
192,0,38,32,0,12,184,255,8,0,9,2,0,5,192,0,1,64,35,4,0,22,128,32,0,
|
||||
11,1,0,12,203,252,0,10,4,0,5,192,16,0,1,3,0,24,2,0,11,1,0,12,57,255,
|
||||
0,9,24,32,0,5,240,0,1,128,0,24,12,32,0,10,12,32,0,12,248,250,4,0,20,
|
||||
3,0,36,48,32,0,12,217,251,0,9,96,10,0,6,8,1,0,25,48,17,0,11,2,0,12,
|
||||
192,249,16,0,1,128,0,13,16,0,3,104,32,0,49,184,249,0,22,96,0,50,152,
|
||||
249,0,4,4,0,11,240,0,3,64,0,50,40,251,12,0,16,208,0,3,96,33,0,49,3,
|
||||
255,4,0,2,70,2,0,12,16,0,2,96,2,0,49,153,253,0,2,128,1,0,12,32,0,3,
|
||||
120,32,0,49,152,249,4,0,3,2,0,12,64,0,2,96,64,0,49,233,248,0,3,16,
|
||||
0,13,4,0,2,96,2,0,49,168,254,176,1,4,128,0,0,16,0,0,2,0,4,32,0,1,128,
|
||||
0,0,208,0,5,13,32,0,0,4,0,22,2,64,3,0,1,13,0,1,52,0,4,64,0,7,192,248,
|
||||
128,1,0,15,192,0,5,12,0,27,3,1,0,0,12,4,0,0,48,16,0,12,8,249,128,1,
|
||||
0,4,24,0,4,128,1,0,3,32,0,4,12,0,27,2,0,1,8,0,1,32,0,13,56,251,140,
|
||||
17,2,0,3,24,0,4,128,1,0,2,192,0,5,12,0,27,11,1,0,0,44,4,0,0,176,16,
|
||||
0,12,122,255,132,17,176,32,22,194,8,24,0,5,32,0,1,70,194,16,0,4,64,
|
||||
0,0,136,48,1,0,21,152,8,99,0,1,140,1,0,0,48,6,0,4,35,1,0,5,56,248,
|
||||
224,129,60,128,7,240,128,30,8,0,3,96,0,1,128,7,240,0,5,3,100,0,0,60,
|
||||
32,0,21,30,192,3,0,1,15,0,1,60,0,4,192,3,0,6,208,252,132,1,48,0,0,
|
||||
6,192,0,7,128,0,1,6,192,64,0,5,128,129,48,0,22,24,0,0,3,2,0,0,12,8,
|
||||
0,0,48,32,0,4,3,0,6,249,249,0,0,40,48,0,0,6,192,0,0,64,16,0,4,8,0,
|
||||
1,6,192,4,0,5,128,9,48,0,22,24,0,0,19,0,1,76,0,1,48,1,0,4,3,0,6,248,
|
||||
251,0,74,152,255,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,
|
||||
128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,15,32,0,0,4,128,0,0,16,
|
||||
0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,
|
||||
0,4,0,0,152,255,0,74,152,255,40,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,
|
||||
0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,15,32,0,0,
|
||||
4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,
|
||||
8,0,0,1,32,0,0,4,0,0,129,254,0,18,34,0,0,8,0,52,131,252,32,0,0,4,128,
|
||||
0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,3,9,0,0,1,32,0,0,
|
||||
4,0,15,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,
|
||||
0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,0,232,255,4,0,17,64,0,0,8,0,0,2,0,
|
||||
50,146,253,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,
|
||||
1,2,66,0,0,32,8,0,0,1,32,0,0,4,0,15,32,0,0,4,128,0,0,16,0,0,2,64,0,
|
||||
0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,0,232,
|
||||
251,0,74,152,255,0,74,152,255,0,74,152,255,0,14,16,0,58,136,255,0,
|
||||
21,2,0,51,152,253,0,74,152,255,0,5,64,0,2,16,0,3,4,0,9,8,128,0,19,
|
||||
128,0,17,1,0,5,128,145,250,0,25,4,0,18,128,0,0,32,4,0,17,8,0,5,112,
|
||||
251,0,5,64,0,2,16,0,3,104,0,4,4,0,3,12,128,0,18,1,160,1,0,15,128,0,
|
||||
0,8,0,5,16,251,0,15,8,0,33,16,16,2,0,3,128,0,7,13,0,1,8,0,3,56,251,
|
||||
10,0,14,8,0,40,64,0,7,1,0,6,120,248,8,0,49,128,16,16,0,15,8,0,2,128,
|
||||
17,254,0,2,4,0,70,216,251,0,3,16,0,17,4,0,50,200,254,0,9,16,0,1,64,
|
||||
0,3,32,0,55,232,250,0,1,2,0,12,4,0,2,1,0,32,4,0,1,16,0,1,64,0,13,184,
|
||||
255,2,0,4,64,0,15,64,0,23,16,0,3,64,0,2,1,0,1,4,0,12,128,48,248,4,
|
||||
0,73,201,250,0,74,152,255,0,74,152,255,0,74,152,255,0,6,32,0,66,184,
|
||||
253,8,0,21,16,0,50,144,254,0,21,4,0,51,152,251,0,3,2,0,59,64,0,8,152,
|
||||
249,32,0,8,8,0,1,32,0,3,16,0,56,253,0,74,152,255,0,47,8,0,11,4,0,12,
|
||||
144,251,0,19,4,0,3,8,64,0,33,8,0,3,2,0,7,248,249,0,22,64,0,29,2,0,
|
||||
1,8,0,1,32,0,13,144,249,0,23,1,0,28,8,0,1,32,0,1,128,0,13,2,252,0,
|
||||
74,152,255,0,0,2,0,7,128,0,6,64,0,0,40,0,53,80,255,0,7,4,0,5,8,0,30,
|
||||
64,0,16,4,0,8,144,251,4,0,1,64,0,70,152,251,8,0,50,8,0,21,24,255,64,
|
||||
0,7,1,0,4,8,16,0,8,64,0,1,16,0,16,4,16,0,8,1,0,15,196,255,8,0,3,32,
|
||||
0,21,8,0,18,8,0,25,118,251,64,0,0,16,8,2,16,0,1,128,0,0,192,0,3,24,
|
||||
16,0,0,64,0,3,32,0,1,64,0,0,4,16,0,16,8,48,0,4,6,0,2,4,0,15,136,249,
|
||||
128,0,0,164,128,0,0,16,0,2,8,0,0,160,0,2,128,128,8,128,2,0,1,128,144,
|
||||
0,0,4,0,0,1,4,0,18,4,0,0,128,0,0,4,64,0,0,136,0,1,32,2,0,0,80,0,2,
|
||||
36,0,8,144,253,32,0,20,128,0,1,1,0,48,176,254,0,1,32,0,14,32,0,6,128,
|
||||
0,20,8,0,0,128,0,23,176,253,0,74,152,255,0,74,152,255,8,0,73,178,253,
|
||||
0,74,152,255,0,73,128,16,255,0,16,1,0,47,128,0,7,8,255,0,74,220,251,
|
||||
0,1,8,0,0,1,0,69,24,254,0,28,8,0,44,24,255,0,1,16,0,18,64,0,2,128,
|
||||
0,47,80,250,0,74,152,255,0,74,152,255,0,74,152,255,0,74,152,255,0,
|
||||
74,152,255,0,74,152,255,0,74,152,255,0,74,152,255,0,74,152,255,0,74,
|
||||
152,255,0,14,4,0,58,216,251,0,74,152,255,0,74,152,255,8,0,73,129,254,
|
||||
0,14,48,34,0,57,187,252,0,14,60,0,58,224,251,4,0,13,48,0,58,202,249,
|
||||
0,14,48,0,58,168,255,16,0,71,4,0,0,136,251,0,74,152,255,0,73,32,152,
|
||||
253,12,0,71,176,0,0,202,250,4,0,71,48,1,248,248,16,0,71,60,8,176,248,
|
||||
0,72,48,0,0,185,253,0,72,48,18,136,253,0,19,26,0,51,4,0,0,56,250,0,
|
||||
19,24,0,52,16,24,255,0,74,152,255,8,0,71,128,16,137,255,0,19,64,8,
|
||||
0,51,17,179,249,0,19,6,0,51,60,0,0,64,248,4,0,19,16,0,50,32,0,0,202,
|
||||
251,0,20,1,0,50,16,33,136,253,0,24,41,0,46,52,0,1,251,0,25,8,0,45,
|
||||
32,32,56,255,0,24,8,0,46,48,0,0,32,252,4,0,23,128,4,0,45,32,64,146,
|
||||
255,12,0,71,16,2,224,250,0,24,7,8,0,45,60,32,160,253,8,0,23,12,4,0,
|
||||
47,73,250,0,24,140,0,46,16,65,24,254,0,27,4,0,30,4,0,11,4,33,200,249,
|
||||
0,74,152,255,0,72,32,8,56,253,4,0,71,16,2,202,248,12,0,26,48,0,30,
|
||||
48,0,12,17,192,249,0,27,60,16,0,29,60,16,0,10,60,0,0,240,251,8,0,26,
|
||||
48,0,30,48,0,11,32,0,0,161,255,0,27,48,0,30,48,0,11,48,18,136,254,
|
||||
0,7,64,0,2,1,0,6,2,0,31,64,8,1,0,16,148,8,56,250,0,19,24,0,53,24,254,
|
||||
0,19,24,0,51,16,32,8,253,4,0,18,152,8,0,31,11,1,0,17,1,225,249,12,
|
||||
0,7,99,0,1,140,4,0,5,88,8,0,31,17,1,0,16,128,64,251,250,0,7,192,3,
|
||||
0,1,15,0,6,30,0,31,192,2,0,17,44,0,0,184,254,8,0,7,3,0,1,12,0,6,24,
|
||||
16,0,31,3,2,0,16,48,0,0,90,249,0,8,3,0,1,12,0,6,24,1,0,31,34,0,17,
|
||||
48,66,96,253,0,1,4,128,0,0,16,0,0,2,64,0,11,64,0,24,4,128,0,0,16,0,
|
||||
11,16,0,1,64,0,0,8,0,0,5,8,0,0,20,32,152,251,0,74,152,255,0,69,4,0,
|
||||
1,16,0,0,136,250,8,0,68,32,8,0,0,128,8,154,255,0,1,48,2,70,200,72,
|
||||
24,2,19,0,11,19,1,0,22,176,16,38,200,64,0,10,192,0,2,19,96,33,128,
|
||||
0,2,16,56,255,0,1,60,160,7,240,0,0,30,192,3,1,0,9,192,3,0,23,60,128,
|
||||
7,240,0,11,240,64,0,0,192,3,122,0,0,11,4,0,0,44,0,0,232,248,4,0,0,
|
||||
48,0,0,6,192,0,0,24,0,0,3,0,11,3,0,23,48,0,0,6,192,0,11,192,0,2,3,
|
||||
96,0,0,12,0,1,48,0,0,25,249,0,1,48,0,0,6,192,0,0,24,0,0,3,0,11,3,0,
|
||||
23,48,0,0,6,192,0,11,192,0,2,3,96,0,0,140,16,0,0,48,66,96,249,0,74,
|
||||
220,251,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,
|
||||
16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,15,32,0,0,4,128,0,0,16,0,0,2,64,
|
||||
0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,0,
|
||||
152,255,0,74,152,255,36,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,
|
||||
0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,15,32,0,0,4,128,0,0,
|
||||
16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,
|
||||
0,0,4,0,0,235,248,12,0,73,193,250,32,0,0,4,128,0,0,16,0,0,2,64,0,0,
|
||||
8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,15,32,
|
||||
0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,
|
||||
0,0,8,0,0,1,32,0,0,4,0,0,186,253,8,0,73,212,251,32,0,0,4,128,0,0,16,
|
||||
0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,
|
||||
0,4,0,15,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,
|
||||
16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,0,152,255,0,74,152,255,0,24,4,0,
|
||||
46,48,0,0,168,248,0,74,152,255,0,74,152,255,0,24,8,0,46,32,0,0,48,
|
||||
253,0,53,1,0,19,136,254,0,2,128,0,41,128,0,0,128,0,25,144,255,0,47,
|
||||
32,0,25,184,255,0,3,1,0,16,10,0,4,96,0,16,128,0,0,32,1,0,24,88,251,
|
||||
0,0,1,0,6,2,0,3,32,0,0,8,0,4,8,0,23,32,0,2,16,0,7,32,0,1,64,0,10,200,
|
||||
252,0,15,8,0,45,16,0,10,85,250,8,1,0,6,2,0,4,1,0,30,4,0,2,128,0,7,
|
||||
32,0,13,64,253,0,8,2,0,36,16,0,26,184,252,0,14,128,0,58,24,255,0,74,
|
||||
152,255,0,19,32,0,51,64,16,216,248,0,67,32,0,5,152,253,0,74,152,255,
|
||||
0,74,152,255,0,74,152,255,0,74,152,255,0,70,16,0,1,64,152,250,8,0,
|
||||
65,128,0,6,152,255,0,74,152,255,0,73,4,216,255,0,74,152,255,0,74,152,
|
||||
255,0,53,64,0,19,216,255,0,49,32,0,22,32,152,255,0,20,2,0,27,8,0,2,
|
||||
2,0,18,164,208,253,0,2,16,0,15,8,0,32,1,0,19,24,254,0,11,2,0,12,2,
|
||||
0,36,1,0,9,152,252,0,69,16,0,3,136,254,0,74,152,255,0,7,64,0,65,152,
|
||||
251,0,74,152,255,10,0,45,4,0,5,2,0,0,32,2,0,16,240,255,0,17,32,0,6,
|
||||
2,0,21,1,0,19,2,64,0,0,8,128,152,248,0,0,3,0,2,128,2,80,0,0,10,32,
|
||||
0,0,128,1,0,3,16,0,0,80,0,4,8,0,19,8,128,0,0,64,0,1,128,10,0,0,32,
|
||||
2,0,11,1,32,0,0,164,0,0,208,252,64,2,32,0,0,9,0,0,2,72,64,8,0,0,1,
|
||||
0,8,64,0,2,8,0,0,144,34,0,17,16,128,8,0,0,2,0,0,2,1,32,0,4,208,8,0,
|
||||
1,34,0,1,72,8,1,32,2,0,1,176,254,0,6,4,0,38,16,0,4,128,0,0,16,0,19,
|
||||
251,0,1,8,0,21,2,0,1,8,0,23,2,0,13,16,8,0,4,184,252,0,74,152,255,2,
|
||||
0,20,1,0,36,64,0,12,128,112,252,0,72,8,80,16,250,2,0,24,4,0,46,128,
|
||||
112,253,26,0,72,128,10,255,0,4,32,0,68,152,253,0,74,152,255,0,4,4,
|
||||
0,64,2,0,2,248,255,0,69,32,0,1,128,0,0,176,253,0,74,152,255,0,74,152,
|
||||
255,0,6,2,0,19,64,0,45,216,249,32,4,16,128,20,64,0,0,8,0,0,1,32,1,
|
||||
4,0,40,128,0,0,17,36,32,0,0,4,128,0,0,16,0,0,18,0,0,1,96,1,36,128,
|
||||
4,132,0,0,152,254,0,0,1,32,0,0,128,128,0,0,16,0,0,2,64,0,0,8,0,40,
|
||||
2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,240,2,10,64,11,40,0,0,5,160,0,0,
|
||||
48,248,0,0,2,64,0,0,64,0,0,1,32,0,0,4,128,0,0,16,0,61,176,250,0,53,
|
||||
4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,0,0,1,4,128,4,16,0,0,2,64,0,0,136,
|
||||
252,0,0,20,128,2,56,0,0,10,64,1,40,0,0,5,160,0,0,45,160,2,84,128,10,
|
||||
80,1,42,64,5,168,0,0,21,160,2,0,15,21,160,2,84,128,10,208,2,40,0,0,
|
||||
5,160,0,0,20,128,2,80,0,0,10,192,0,0,40,0,0,3,160,0,0,20,128,2,224,
|
||||
255,192,12,148,1,34,99,6,204,64,25,40,3,101,160,225,52,129,38,224,
|
||||
4,154,64,19,112,2,77,160,9,56,1,0,14,192,9,56,1,39,208,4,26,86,25,
|
||||
40,3,102,192,12,148,1,51,80,6,204,148,25,40,83,102,192,12,152,1,88,
|
||||
249,255,255,};
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,848 +0,0 @@
|
||||
/*
|
||||
* DO NOT EDIT MANUALLY!
|
||||
* This code was generated by mkfw utility
|
||||
* from the file `ctau.dat'
|
||||
*
|
||||
* Cronyx Id: ctaufw.h,v 1.1 2002/06/03 10:19:40 rik Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
long ctau_fw_len = 131234;
|
||||
|
||||
const char *ctau_fw_version = "1.1";
|
||||
const char *ctau_fw_date = "18.02.97";
|
||||
const char *ctau_fw_copyright = "Copyright (C) 1997 Cronyx Engineering.";
|
||||
|
||||
const cr_dat_tst_t ctau_fw_tvec[] = {
|
||||
{ 65066, 66278}, { 66314, 67526}, { 67562, 68774}, { 68810, 70022},
|
||||
{ 70058, 71270}, { 71306, 72518}, { 72554, 73766}, { 73802, 75014},
|
||||
{ 75050, 76262}, { 76298, 77510}, { 77546, 78758}, { 78794, 80006},
|
||||
{ 80042, 81254}, { 81290, 82502}, { 82538, 83750}, { 83786, 84998},
|
||||
{ 85034, 86246}, { 86282, 87494}, { 87530, 88742}, { 88778, 89990},
|
||||
{ 90026, 91238}, { 91274, 92486}, { 92522, 93734}, { 93770, 94982},
|
||||
{ 95018, 96230}, { 96266, 97478}, { 97514, 98726}, { 98762, 99974},
|
||||
{100010,101222}, {101258,102470}, {102506,103718}, {103754,104966},
|
||||
{105002,106214}, {106250,107462}, {107498,108710}, {108746,109958},
|
||||
{109994,111206}, {111242,112454}, {112490,113702}, {113738,114950},
|
||||
{114986,116198}, {116234,117446}, {117482,118694}, {118730,119942},
|
||||
{119978,121190}, {121226,122438}, {122474,123686}, {123722,124934},
|
||||
{124970,126182}, {126218,127430}, {127466,128678}, {128714,129926},
|
||||
{129962,131174}, {131234,131234},
|
||||
};
|
||||
|
||||
const unsigned char ctau_fw_data[] = {
|
||||
155,153,97,92,102,33,49,48,49,49,113,112,112,112,96,101,97,52,100,
|
||||
52,100,100,100,48,36,48,100,100,52,116,100,48,52,112,97,33,49,37,116,
|
||||
100,100,100,112,53,33,49,49,37,37,37,37,116,32,33,97,97,97,97,100,
|
||||
100,48,113,116,97,100,100,97,97,113,96,97,53,97,112,112,112,48,49,
|
||||
49,113,100,53,49,49,97,49,97,112,112,96,101,49,52,52,52,100,100,36,
|
||||
113,36,52,100,100,52,52,52,52,52,48,96,33,37,37,37,49,49,49,117,53,
|
||||
33,49,49,37,37,37,37,37,116,112,96,97,97,97,100,100,100,101,33,49,
|
||||
49,49,96,97,97,101,112,116,116,100,100,37,48,49,49,113,53,59,57,97,
|
||||
96,97,100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,97,37,49,48,
|
||||
49,49,49,32,112,112,96,37,37,100,52,112,49,49,49,33,37,52,100,100,
|
||||
52,52,52,52,112,117,97,33,37,37,37,49,49,97,116,48,33,49,49,37,37,
|
||||
101,33,37,36,37,97,97,97,97,100,100,100,97,101,96,100,100,113,100,
|
||||
96,97,33,48,101,112,112,112,48,49,49,100,37,49,48,49,53,112,112,112,
|
||||
112,96,112,48,52,52,52,100,100,100,52,53,32,100,100,52,52,52,52,52,
|
||||
48,52,36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,53,97,113,97,100,
|
||||
100,96,97,100,100,100,49,76,68,36,97,48,49,49,37,37,37,37,37,116,116,
|
||||
96,97,100,97,100,100,36,49,36,49,49,49,96,101,36,97,33,53,113,48,113,
|
||||
96,101,100,100,36,96,117,101,100,36,112,112,112,96,117,37,37,52,52,
|
||||
52,100,100,36,49,100,36,49,49,33,52,52,37,52,48,52,36,37,37,37,49,
|
||||
49,49,117,53,33,49,49,101,49,33,37,37,96,52,97,97,97,97,100,100,48,
|
||||
53,100,96,100,116,96,97,97,97,33,33,52,112,112,112,48,49,49,113,52,
|
||||
100,48,49,113,112,112,112,112,96,48,49,52,52,52,100,100,100,52,116,
|
||||
36,100,100,52,52,52,116,36,101,37,49,49,33,37,49,49,49,53,16,177,177,
|
||||
97,36,100,100,100,52,52,52,52,112,113,33,37,49,37,49,49,49,116,48,
|
||||
33,49,49,49,117,37,37,37,116,112,96,100,33,53,49,49,49,96,101,96,100,
|
||||
100,100,97,97,33,117,53,52,112,112,112,48,49,49,100,37,49,48,49,113,
|
||||
112,112,52,112,112,101,48,52,52,52,100,100,100,52,37,52,100,100,112,
|
||||
100,36,52,52,112,113,36,37,37,37,49,49,97,116,117,32,49,49,37,37,37,
|
||||
37,37,36,37,97,97,97,97,100,100,100,97,101,96,100,100,97,97,97,97,
|
||||
33,97,97,112,112,112,48,49,49,113,32,100,100,100,100,36,112,112,49,
|
||||
52,53,100,100,36,52,100,100,100,52,32,179,51,32,49,48,49,49,113,112,
|
||||
112,112,96,101,37,52,100,52,100,100,100,48,49,32,100,100,52,116,100,
|
||||
48,52,112,97,33,49,37,116,100,100,100,96,33,96,100,100,32,37,37,37,
|
||||
116,117,112,96,97,97,97,100,100,48,97,112,53,49,49,96,97,113,96,33,
|
||||
97,97,112,112,112,48,49,49,113,36,49,49,49,33,52,48,112,112,96,101,
|
||||
49,52,52,52,100,100,36,113,97,36,100,100,52,52,52,52,52,48,52,36,37,
|
||||
37,37,49,49,49,101,32,32,49,49,37,37,37,37,37,36,37,97,97,97,97,100,
|
||||
100,100,97,101,96,100,100,97,97,97,101,112,116,48,49,49,112,48,49,
|
||||
49,113,37,110,108,116,101,100,100,100,97,97,97,97,33,53,117,113,48,
|
||||
113,48,49,49,97,37,49,48,49,113,112,113,113,112,112,112,37,100,52,
|
||||
112,49,49,49,33,116,36,100,100,52,100,52,52,112,117,97,33,37,37,37,
|
||||
49,49,97,116,48,33,49,49,37,37,101,33,37,117,36,97,97,97,97,100,100,
|
||||
100,97,101,96,100,36,101,100,96,97,33,53,101,112,112,112,48,49,49,
|
||||
52,100,100,48,49,53,112,112,112,112,96,112,48,52,52,52,100,100,100,
|
||||
52,116,36,100,100,100,52,52,52,52,48,52,36,37,37,37,49,49,49,37,52,
|
||||
48,49,49,37,49,37,53,97,113,97,100,100,96,97,100,100,100,113,77,68,
|
||||
116,113,37,49,49,37,37,37,37,37,37,97,96,97,100,97,100,100,36,97,33,
|
||||
49,49,49,96,101,36,97,97,97,53,48,113,96,101,100,100,36,100,32,100,
|
||||
100,36,112,112,112,96,117,37,37,52,52,52,100,100,36,49,96,36,100,100,
|
||||
100,52,52,37,52,48,52,36,37,37,37,49,49,49,37,52,36,49,49,52,49,33,
|
||||
49,37,116,52,97,97,97,97,100,100,48,101,101,100,100,36,53,96,97,97,
|
||||
33,33,52,112,112,112,48,49,49,113,113,96,100,100,36,112,112,112,112,
|
||||
96,112,53,52,52,52,100,100,100,52,116,36,100,100,52,52,52,116,36,101,
|
||||
37,49,49,33,37,49,49,49,53,21,177,177,97,36,100,100,52,52,52,52,52,
|
||||
112,113,33,37,49,37,49,49,49,116,48,33,49,49,37,37,53,36,37,116,112,
|
||||
96,100,33,53,49,49,49,96,101,96,100,100,97,97,100,33,117,53,52,112,
|
||||
112,112,48,49,49,100,113,48,100,100,36,112,112,52,112,96,112,48,52,
|
||||
52,52,100,100,100,52,116,36,100,100,112,100,36,52,52,112,113,36,37,
|
||||
37,37,49,49,97,116,48,33,49,113,33,37,37,37,37,36,37,97,97,97,97,100,
|
||||
100,100,97,101,96,100,100,97,100,97,97,33,100,97,112,112,112,48,49,
|
||||
49,113,100,32,100,100,36,112,48,113,49,52,53,100,100,36,52,100,100,
|
||||
100,52,52,230,102,49,49,100,100,36,112,112,112,112,112,48,36,52,100,
|
||||
52,100,100,100,112,36,52,100,100,52,116,100,48,52,112,33,32,49,37,
|
||||
116,100,100,100,32,52,48,49,49,37,37,37,37,116,117,112,96,97,97,97,
|
||||
100,100,48,101,96,97,100,100,97,97,113,96,33,53,52,112,112,48,49,49,
|
||||
49,113,112,49,48,49,97,113,100,37,48,97,101,97,100,52,52,100,100,100,
|
||||
37,97,100,100,100,49,52,52,52,52,48,52,36,37,37,37,49,49,49,37,53,
|
||||
33,49,49,37,37,37,37,37,36,37,97,97,97,97,100,100,100,113,96,97,100,
|
||||
100,97,97,97,100,100,97,32,49,49,113,48,49,49,113,117,58,57,49,100,
|
||||
96,100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,97,37,49,48,49,
|
||||
113,112,49,97,112,96,37,37,100,52,112,49,49,49,33,116,36,100,100,52,
|
||||
52,52,100,112,117,97,33,37,37,37,49,49,97,116,48,33,49,49,37,37,101,
|
||||
33,37,36,37,97,97,97,97,100,100,100,33,53,96,100,36,53,32,53,96,33,
|
||||
53,101,112,112,112,48,49,49,112,37,49,48,49,53,112,112,112,112,96,
|
||||
112,48,52,52,52,100,100,100,52,97,52,100,100,52,52,52,100,52,48,52,
|
||||
36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,53,97,113,97,100,100,
|
||||
96,97,100,100,100,49,73,68,52,97,117,100,100,32,37,37,37,37,116,116,
|
||||
96,97,100,97,100,100,36,53,100,96,100,100,97,101,36,97,33,53,52,48,
|
||||
113,96,101,100,100,36,101,113,49,49,113,112,112,112,96,117,37,37,52,
|
||||
52,52,100,100,36,113,97,36,100,100,52,52,52,37,52,112,97,33,37,37,
|
||||
49,49,49,49,37,53,33,49,49,52,49,33,37,49,116,52,100,100,97,97,100,
|
||||
100,48,49,101,96,100,116,96,97,97,97,33,97,97,112,112,112,48,49,49,
|
||||
113,112,49,48,49,113,112,112,112,112,96,112,48,52,52,52,100,100,100,
|
||||
52,116,36,100,100,52,52,52,52,100,52,36,48,49,49,37,49,49,49,53,4,
|
||||
177,177,97,36,100,100,52,52,52,52,52,52,36,33,37,49,37,49,49,49,116,
|
||||
117,32,49,49,37,53,49,36,37,116,32,96,100,33,53,49,49,49,96,101,96,
|
||||
100,100,97,97,97,33,117,53,52,48,113,112,48,49,49,116,116,37,48,49,
|
||||
113,112,112,52,112,96,112,48,52,52,52,100,100,100,52,37,100,100,100,
|
||||
112,52,113,33,52,112,113,36,37,37,37,49,49,113,33,53,33,49,113,53,
|
||||
37,37,37,37,36,37,97,97,97,97,100,100,100,49,97,100,100,100,97,97,
|
||||
97,97,36,97,97,112,112,112,48,49,49,113,96,37,48,49,113,112,112,48,
|
||||
100,49,53,100,100,36,52,100,100,100,52,112,179,51,32,49,48,49,113,
|
||||
112,112,112,112,96,101,37,52,100,100,100,100,100,48,116,33,100,100,
|
||||
52,116,100,48,52,112,97,33,49,49,116,100,100,100,100,37,32,49,49,37,
|
||||
37,37,37,116,117,112,96,100,97,97,100,100,112,49,100,96,100,100,97,
|
||||
97,113,96,33,33,52,112,112,112,48,49,49,113,52,112,48,49,97,101,116,
|
||||
37,48,97,101,97,100,52,52,100,100,36,49,101,53,100,100,37,52,52,52,
|
||||
52,48,52,36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,37,37,36,37,
|
||||
97,97,97,97,100,100,100,97,101,96,100,100,97,97,97,97,100,97,32,49,
|
||||
49,113,48,49,49,113,101,111,108,116,97,48,49,49,96,97,97,97,33,53,
|
||||
53,112,48,113,48,49,49,97,37,49,48,49,113,112,49,97,112,96,37,37,100,
|
||||
52,52,100,100,100,52,116,36,100,100,52,52,52,52,112,37,113,36,37,37,
|
||||
37,49,49,97,52,33,49,49,49,37,37,101,33,37,116,37,97,97,97,100,100,
|
||||
100,100,97,101,96,100,36,101,100,96,97,33,53,101,112,112,112,48,49,
|
||||
49,36,36,49,48,49,53,112,112,112,112,112,101,53,52,52,52,100,100,100,
|
||||
52,37,37,100,100,52,52,52,52,52,48,52,48,37,37,37,49,49,49,101,33,
|
||||
49,49,49,37,37,37,53,97,113,97,100,100,96,97,100,100,100,113,72,68,
|
||||
52,48,33,49,49,37,37,37,37,37,96,116,96,97,100,97,100,100,36,33,100,
|
||||
96,100,100,97,101,36,97,33,53,52,48,49,49,49,49,49,49,100,49,48,49,
|
||||
113,112,112,112,96,117,37,37,52,52,52,100,100,36,113,97,36,100,100,
|
||||
52,52,52,37,52,112,97,33,37,37,37,49,49,49,37,53,33,49,49,52,49,33,
|
||||
37,49,116,52,97,97,97,97,100,100,48,97,100,48,49,97,96,97,97,97,97,
|
||||
53,117,112,112,112,48,49,49,113,112,49,48,49,113,112,112,112,112,96,
|
||||
112,48,52,52,52,100,100,100,52,116,36,100,100,52,52,52,116,36,49,36,
|
||||
49,49,33,37,49,49,49,53,1,177,177,52,33,49,49,33,52,52,52,52,112,49,
|
||||
116,32,49,37,49,49,49,52,96,96,100,100,32,53,49,36,37,116,112,96,100,
|
||||
33,53,49,49,49,96,101,96,100,100,97,97,97,33,112,53,116,36,48,113,
|
||||
48,49,49,97,97,48,49,49,113,112,112,52,112,96,112,48,52,52,100,100,
|
||||
100,100,52,37,49,100,100,112,100,36,52,52,112,113,48,49,37,37,49,49,
|
||||
97,116,48,33,49,113,33,37,37,37,37,36,37,97,97,97,97,100,100,100,33,
|
||||
101,101,100,100,97,97,97,97,33,97,97,48,113,112,48,49,49,113,52,100,
|
||||
48,49,113,112,112,112,49,52,53,100,100,36,52,100,100,100,52,36,178,
|
||||
51,32,49,48,49,113,112,112,112,112,96,101,37,52,100,52,100,100,100,
|
||||
52,117,100,100,100,52,116,100,48,52,112,97,33,49,49,116,100,100,100,
|
||||
96,116,49,49,49,37,37,37,37,116,117,112,49,96,100,97,100,100,36,53,
|
||||
100,96,100,100,97,97,113,96,33,33,52,112,112,112,48,49,49,113,112,
|
||||
49,48,49,97,49,49,112,112,96,101,49,100,52,52,100,100,36,49,36,117,
|
||||
49,49,36,52,52,52,52,116,49,36,37,37,37,49,49,49,37,53,33,49,49,37,
|
||||
37,37,37,37,36,37,97,97,97,97,100,100,100,49,100,100,100,100,97,97,
|
||||
97,101,48,117,48,49,49,112,48,49,49,113,53,106,108,116,52,53,49,49,
|
||||
96,97,97,97,33,53,53,112,48,113,48,49,49,97,37,49,48,49,113,112,49,
|
||||
97,112,96,37,37,100,52,32,49,49,49,33,116,36,100,100,52,52,52,52,112,
|
||||
37,113,36,37,37,37,49,49,97,52,97,36,49,49,37,37,101,33,37,116,37,
|
||||
97,97,97,97,100,100,100,49,100,97,100,36,101,100,96,97,33,53,37,113,
|
||||
112,112,48,49,49,100,37,49,48,49,53,112,112,112,112,96,112,53,52,52,
|
||||
52,100,100,100,52,32,117,49,49,33,52,52,52,52,48,52,36,37,49,37,49,
|
||||
49,49,37,53,33,49,49,37,37,37,53,97,113,97,100,100,96,97,100,100,100,
|
||||
49,8,17,33,48,33,49,49,37,37,37,37,37,116,52,97,97,100,97,100,100,
|
||||
100,52,100,100,100,100,97,101,36,97,33,53,52,48,113,96,101,100,100,
|
||||
100,33,49,48,49,113,112,112,112,96,117,37,37,52,52,52,100,100,36,113,
|
||||
116,100,100,100,52,52,52,37,52,112,97,33,37,37,37,49,49,49,53,116,
|
||||
37,49,49,52,49,33,37,37,116,52,97,97,97,97,100,100,48,33,100,96,100,
|
||||
116,96,97,97,97,33,97,33,49,113,112,48,49,49,113,37,96,48,49,113,112,
|
||||
112,112,112,96,112,48,52,52,52,100,100,100,52,49,49,100,100,52,52,
|
||||
52,52,37,101,37,52,49,33,37,49,49,49,53,0,228,228,32,33,100,100,52,
|
||||
52,52,100,100,112,113,33,37,49,37,49,49,49,116,48,33,49,49,37,53,49,
|
||||
36,37,116,112,96,100,33,48,49,49,49,32,97,48,49,49,96,97,97,33,117,
|
||||
53,52,112,48,113,48,49,49,100,37,49,48,49,113,112,112,52,112,96,112,
|
||||
48,52,52,52,100,100,100,52,116,36,100,100,112,100,36,52,52,52,100,
|
||||
32,37,37,37,49,49,97,52,37,97,100,36,33,37,37,37,37,36,37,97,97,97,
|
||||
97,100,100,100,97,101,96,100,100,97,97,97,97,33,100,97,112,112,112,
|
||||
48,49,49,113,112,49,48,49,113,112,112,112,49,52,53,100,100,36,52,100,
|
||||
100,100,52,96,178,51,113,49,48,49,113,112,112,112,112,96,101,37,52,
|
||||
100,52,100,100,100,112,36,97,100,100,52,116,100,48,52,112,97,33,49,
|
||||
37,116,100,100,100,48,113,37,49,49,37,37,37,37,116,117,32,96,97,97,
|
||||
97,100,100,48,53,100,96,100,100,97,97,113,96,33,97,97,112,112,112,
|
||||
48,49,49,113,37,49,100,100,116,49,49,112,112,96,101,49,52,52,52,100,
|
||||
100,36,49,96,36,100,100,37,52,52,52,52,112,53,36,37,37,37,49,49,49,
|
||||
101,97,48,49,49,37,37,37,37,37,36,37,97,97,97,97,100,100,100,97,101,
|
||||
96,100,100,97,97,97,97,33,53,101,96,117,37,48,49,49,113,37,107,108,
|
||||
52,52,100,100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,33,36,49,
|
||||
48,49,113,112,48,113,112,96,37,37,100,52,112,49,49,49,33,116,36,100,
|
||||
100,52,52,52,52,112,117,97,33,37,37,37,49,49,97,116,101,101,100,100,
|
||||
32,37,101,33,37,48,37,97,97,97,97,100,100,100,97,101,96,100,36,101,
|
||||
100,96,97,97,97,36,112,112,112,48,49,49,100,113,32,48,49,53,112,112,
|
||||
112,112,96,112,48,52,52,52,100,100,100,52,116,36,100,100,52,52,52,
|
||||
52,52,96,52,36,37,37,37,49,49,49,101,36,49,49,49,37,37,37,53,117,113,
|
||||
97,113,117,49,96,100,100,100,113,9,17,97,48,100,100,100,32,37,37,37,
|
||||
37,96,116,96,97,100,97,100,100,36,113,112,96,100,100,97,113,113,49,
|
||||
32,53,52,48,113,96,101,100,100,36,101,96,100,100,36,112,112,112,96,
|
||||
117,37,37,52,52,52,100,100,36,113,52,33,49,49,33,52,52,37,52,48,52,
|
||||
36,37,37,37,49,49,49,117,96,117,100,100,53,49,33,37,37,37,33,97,97,
|
||||
97,97,100,100,48,101,48,97,100,116,96,97,97,97,33,100,97,112,112,112,
|
||||
48,49,49,113,117,49,48,49,113,112,112,112,112,96,112,48,52,52,100,
|
||||
100,100,100,52,32,116,100,100,52,52,52,116,113,100,37,113,100,116,
|
||||
32,49,49,49,53,5,228,228,116,36,100,100,52,52,52,52,52,112,113,33,
|
||||
37,49,37,49,49,49,116,48,33,49,49,37,53,49,36,37,116,112,96,100,33,
|
||||
53,49,49,49,96,101,96,100,100,97,97,97,33,117,53,32,112,112,112,48,
|
||||
49,49,100,37,49,48,49,113,48,113,52,112,96,112,48,52,52,52,100,100,
|
||||
100,52,116,36,100,100,112,100,36,52,52,112,49,37,37,37,37,49,49,97,
|
||||
116,48,33,49,113,33,37,37,37,37,36,37,97,97,97,97,100,100,100,33,32,
|
||||
100,100,100,97,97,97,97,33,97,97,112,112,112,48,49,49,113,112,49,48,
|
||||
49,113,112,112,112,49,52,53,100,100,36,52,100,100,100,52,116,231,102,
|
||||
33,49,48,49,113,112,112,112,112,96,101,49,52,100,52,100,100,100,112,
|
||||
100,113,49,49,33,116,113,48,52,112,97,33,49,37,116,100,100,100,112,
|
||||
32,36,49,49,37,37,37,37,116,117,112,96,97,97,97,100,100,48,37,48,48,
|
||||
49,49,96,97,113,96,33,97,97,112,112,112,48,49,49,113,100,100,48,49,
|
||||
97,49,49,112,112,96,101,49,52,52,52,100,100,36,113,52,33,49,49,36,
|
||||
52,52,52,52,48,52,36,37,37,37,49,49,49,117,53,33,49,49,37,37,37,37,
|
||||
37,36,37,97,97,97,97,100,100,100,117,101,96,100,100,97,97,97,101,112,
|
||||
116,48,49,49,112,48,49,49,113,117,63,57,33,36,53,49,49,96,100,100,
|
||||
100,36,53,53,48,49,113,48,49,49,97,37,49,48,49,113,112,49,97,112,96,
|
||||
37,37,100,52,112,49,49,49,33,116,36,100,100,52,52,52,52,112,117,97,
|
||||
33,37,37,49,49,49,97,116,48,33,49,49,37,37,113,33,37,36,37,97,97,97,
|
||||
97,100,100,100,97,101,96,100,36,101,100,96,97,33,53,101,112,48,113,
|
||||
48,49,49,100,37,49,48,49,53,112,48,113,112,96,112,48,52,100,52,100,
|
||||
100,100,52,37,52,100,100,52,100,52,52,52,48,52,36,37,37,49,49,49,49,
|
||||
101,117,36,49,49,37,37,37,53,100,113,97,100,52,53,96,100,100,100,49,
|
||||
93,68,52,48,33,49,49,37,37,37,37,37,116,52,97,97,100,97,100,100,36,
|
||||
37,49,100,100,100,97,53,37,97,33,53,52,48,113,96,101,100,100,36,112,
|
||||
49,48,49,113,112,112,112,96,117,37,37,52,52,52,100,100,36,113,96,100,
|
||||
100,100,52,52,52,37,52,48,52,36,37,37,49,49,49,49,117,53,33,49,49,
|
||||
52,49,33,37,37,116,52,97,97,100,97,100,100,48,37,48,48,49,97,96,97,
|
||||
97,97,33,97,97,112,112,112,48,49,49,113,97,117,48,49,113,112,112,112,
|
||||
112,112,101,48,52,52,52,100,100,100,52,116,36,100,100,52,52,52,116,
|
||||
116,101,37,49,49,33,37,49,49,49,53,84,177,177,96,37,100,100,52,52,
|
||||
100,100,100,112,113,33,49,49,37,49,49,49,116,48,33,49,49,37,53,116,
|
||||
37,37,116,112,96,100,33,53,49,49,49,112,49,53,49,49,96,97,97,33,117,
|
||||
53,52,112,112,112,48,49,49,49,113,49,48,49,113,112,112,52,112,96,112,
|
||||
48,52,52,52,100,100,100,52,117,49,100,100,112,100,36,52,52,112,113,
|
||||
36,37,37,37,49,49,97,116,48,33,49,113,33,49,37,37,37,36,37,97,97,97,
|
||||
100,100,100,100,97,101,96,100,100,97,97,97,97,33,97,97,112,112,112,
|
||||
48,49,49,113,52,32,100,100,36,112,112,112,49,52,53,100,100,36,52,100,
|
||||
100,100,52,48,178,51,32,49,48,49,113,112,112,112,112,96,101,49,52,
|
||||
100,52,100,100,100,112,117,48,100,100,52,116,100,48,52,112,97,33,49,
|
||||
37,116,100,100,100,112,48,32,49,49,37,37,37,37,116,117,112,96,97,97,
|
||||
97,100,100,96,49,33,96,100,100,97,97,33,53,32,97,97,112,112,112,48,
|
||||
49,49,113,32,112,49,49,97,49,49,112,112,96,101,49,52,52,52,100,100,
|
||||
36,113,52,32,100,100,37,52,52,52,52,48,52,36,37,37,37,49,49,49,117,
|
||||
48,97,100,100,32,37,37,37,37,36,37,97,97,97,97,100,100,100,49,113,
|
||||
101,100,100,97,97,97,101,112,116,48,49,49,112,48,49,49,113,101,106,
|
||||
108,116,117,96,100,100,97,97,97,100,36,53,53,48,49,113,48,49,49,97,
|
||||
37,49,48,49,113,112,97,117,112,96,37,37,100,52,112,49,49,49,33,116,
|
||||
36,100,100,52,52,52,52,112,117,97,33,37,37,37,49,49,113,33,53,33,49,
|
||||
49,37,37,101,48,37,36,117,97,97,97,97,100,100,100,97,101,96,100,36,
|
||||
101,100,96,97,33,53,101,112,48,113,48,49,49,100,37,49,48,49,53,112,
|
||||
112,112,112,96,112,48,52,52,52,100,100,100,100,116,36,100,100,52,52,
|
||||
52,52,52,116,49,36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,53,33,
|
||||
36,116,100,100,96,97,100,100,100,113,92,68,52,37,117,100,100,32,37,
|
||||
37,37,37,116,116,96,97,100,97,100,100,36,33,100,96,100,100,97,101,
|
||||
36,97,33,53,52,48,113,96,101,100,100,36,117,49,48,49,113,112,112,112,
|
||||
96,117,37,37,52,52,52,100,100,36,49,52,48,49,49,33,52,52,49,52,48,
|
||||
52,36,37,37,37,49,49,49,117,53,33,49,49,52,49,33,37,37,116,52,97,97,
|
||||
97,100,100,100,48,53,100,96,100,116,96,97,97,97,33,33,52,112,112,112,
|
||||
48,49,49,113,37,116,101,100,36,112,112,112,112,112,101,48,52,52,52,
|
||||
100,100,100,52,37,49,100,100,52,52,52,116,36,96,112,97,97,33,37,49,
|
||||
49,49,53,81,177,177,97,36,100,100,52,52,52,100,100,112,113,36,49,49,
|
||||
37,49,49,49,52,33,37,49,49,37,53,49,48,37,96,112,96,100,33,53,49,49,
|
||||
49,48,48,48,49,49,96,97,97,33,112,53,52,112,112,112,48,49,49,48,36,
|
||||
49,48,49,113,112,112,32,36,96,112,53,52,52,52,100,100,100,52,53,36,
|
||||
49,49,117,100,36,52,52,112,113,36,37,37,37,49,49,97,52,33,49,49,113,
|
||||
33,37,37,37,37,36,37,97,97,97,97,100,100,100,97,101,96,100,100,97,
|
||||
97,97,97,33,97,97,112,112,112,48,49,49,113,112,49,48,49,113,112,112,
|
||||
112,49,52,53,112,49,116,33,100,100,100,52,100,227,102,33,49,48,49,
|
||||
113,112,112,112,112,96,101,37,52,100,52,100,100,100,48,96,36,100,100,
|
||||
52,116,100,48,100,112,97,33,49,37,116,100,100,100,48,32,117,100,100,
|
||||
32,37,37,37,116,117,112,96,97,97,97,100,100,48,100,32,97,100,100,97,
|
||||
97,113,96,33,97,97,112,112,112,48,49,49,113,112,49,48,49,97,49,49,
|
||||
112,112,96,101,49,52,52,52,100,100,100,37,116,36,100,100,37,52,52,
|
||||
52,52,48,96,33,37,37,37,49,49,49,117,53,33,49,49,37,37,37,37,37,36,
|
||||
37,97,97,97,97,100,100,100,100,101,96,100,100,97,97,97,101,112,116,
|
||||
112,100,100,37,48,49,49,113,53,47,57,113,96,101,100,100,97,97,97,97,
|
||||
36,53,101,112,48,113,48,49,49,97,53,32,49,49,113,112,49,97,112,96,
|
||||
37,37,100,52,112,49,49,49,33,116,36,100,100,52,52,52,52,112,117,97,
|
||||
33,37,37,37,49,49,97,33,53,33,49,49,37,37,101,33,37,36,37,97,97,97,
|
||||
97,100,100,100,52,97,100,100,36,101,49,53,96,36,53,101,112,112,112,
|
||||
48,49,49,100,97,48,49,49,53,112,112,112,112,96,112,48,52,52,52,100,
|
||||
100,100,52,53,36,49,49,33,52,52,52,52,48,52,36,37,37,37,49,49,49,37,
|
||||
116,117,100,100,32,37,37,53,97,113,97,100,100,96,97,100,100,100,49,
|
||||
28,68,52,48,33,49,49,37,37,37,37,37,116,116,96,97,100,97,100,100,36,
|
||||
49,101,96,100,100,97,101,36,97,33,53,52,48,113,96,101,100,100,36,112,
|
||||
49,48,49,113,112,112,112,112,96,37,37,52,52,52,100,100,36,113,97,36,
|
||||
100,100,52,52,52,112,33,48,52,36,37,37,37,49,49,49,101,53,49,49,49,
|
||||
52,116,116,32,49,116,52,97,97,97,97,100,100,48,53,100,96,100,116,96,
|
||||
97,97,97,33,33,52,112,112,112,48,49,49,113,117,49,48,49,113,112,112,
|
||||
112,112,96,32,37,52,52,52,100,100,100,52,37,117,100,100,52,52,52,116,
|
||||
36,101,37,49,49,33,37,49,49,49,53,80,176,177,96,100,100,100,52,52,
|
||||
52,52,52,112,113,36,37,49,37,49,49,49,116,48,33,49,49,37,53,49,36,
|
||||
37,116,112,49,49,32,53,49,49,49,48,52,100,100,100,97,97,97,33,117,
|
||||
53,52,112,112,112,48,49,49,100,117,53,100,100,36,112,112,52,112,96,
|
||||
112,48,52,52,52,100,100,100,52,116,36,100,100,112,100,36,52,52,112,
|
||||
113,36,37,37,37,49,49,113,100,97,36,49,113,33,37,37,37,37,36,37,97,
|
||||
97,97,97,100,100,100,113,49,48,49,49,96,97,97,97,33,97,97,112,112,
|
||||
112,48,49,49,113,112,49,48,49,113,112,112,112,49,52,53,36,101,36,52,
|
||||
100,100,100,52,32,226,102,37,113,101,100,36,112,112,112,112,96,101,
|
||||
49,52,100,52,100,100,100,112,97,36,100,100,52,116,100,48,52,112,97,
|
||||
33,49,37,116,100,100,100,48,37,100,100,100,32,37,37,37,37,116,112,
|
||||
96,97,97,97,100,100,48,53,100,96,100,100,97,97,49,97,33,97,97,112,
|
||||
112,112,48,49,49,113,49,52,48,49,97,49,49,112,112,96,101,49,52,52,
|
||||
52,100,100,100,100,96,48,49,49,36,52,52,52,52,48,52,36,37,37,37,49,
|
||||
49,49,117,53,33,49,49,37,37,37,37,37,36,37,97,97,97,97,100,100,100,
|
||||
33,48,96,100,100,97,97,97,101,112,116,48,113,100,37,48,49,49,113,37,
|
||||
42,57,49,100,96,100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,97,
|
||||
37,49,48,49,113,112,49,97,112,96,37,37,100,52,112,49,49,49,33,116,
|
||||
36,100,100,52,52,52,52,112,117,97,33,37,37,37,49,49,97,52,100,48,49,
|
||||
49,37,37,101,33,37,36,37,97,97,97,97,100,100,100,97,101,96,100,36,
|
||||
101,36,97,97,33,53,101,112,112,112,48,49,49,100,37,49,48,49,53,112,
|
||||
112,48,113,96,112,48,52,52,52,100,100,100,52,32,33,100,100,52,52,100,
|
||||
52,52,48,52,36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,53,97,113,
|
||||
97,36,101,96,97,100,100,100,113,29,68,100,48,33,49,49,37,37,37,37,
|
||||
37,116,116,96,97,100,97,100,100,36,53,100,96,100,100,97,101,36,97,
|
||||
33,53,52,48,113,96,101,100,100,36,112,49,48,49,113,112,112,112,96,
|
||||
117,37,37,52,52,52,100,100,36,113,97,36,100,100,52,52,52,117,52,48,
|
||||
52,36,37,37,37,49,49,49,37,53,33,49,49,52,49,33,37,37,116,52,97,97,
|
||||
97,97,100,100,48,49,36,49,49,97,96,97,97,97,33,97,100,112,112,112,
|
||||
48,49,49,113,112,49,48,49,113,112,112,112,112,96,112,48,52,52,52,100,
|
||||
100,100,52,49,97,100,100,52,52,52,116,36,101,37,49,52,36,37,49,49,
|
||||
49,53,85,176,177,97,36,100,100,52,52,52,52,52,112,113,33,37,49,37,
|
||||
49,49,49,116,48,33,49,49,37,53,49,36,37,116,112,96,100,33,53,49,49,
|
||||
49,96,101,96,100,100,97,97,97,33,117,53,52,112,112,112,48,49,49,100,
|
||||
49,96,101,100,36,112,112,52,112,96,112,48,52,52,52,100,100,100,52,
|
||||
37,37,100,100,112,100,36,52,52,112,113,36,37,37,37,49,49,33,117,48,
|
||||
33,49,113,33,37,37,37,37,36,37,97,97,97,97,100,100,100,97,101,96,100,
|
||||
100,97,97,97,97,33,97,97,112,112,112,48,49,49,113,112,49,48,49,113,
|
||||
112,112,112,49,52,53,100,116,117,52,100,100,100,52,52,227,102,36,49,
|
||||
48,49,113,112,112,112,112,96,101,37,52,100,52,100,100,100,112,97,36,
|
||||
100,100,52,116,100,48,52,112,97,33,49,37,116,100,100,100,32,53,33,
|
||||
49,49,37,37,37,37,116,117,112,96,97,97,97,100,100,48,101,33,96,100,
|
||||
100,97,97,113,96,33,97,97,112,112,112,48,49,49,113,96,32,48,49,97,
|
||||
49,113,113,112,96,101,49,52,52,52,100,100,36,49,96,36,100,100,37,52,
|
||||
52,52,52,48,100,36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,37,37,
|
||||
36,37,97,97,97,97,100,100,100,33,53,49,49,49,96,97,97,101,112,116,
|
||||
48,49,113,113,48,49,49,113,117,46,57,49,100,96,100,100,97,97,97,97,
|
||||
33,53,53,112,48,113,48,49,49,97,37,49,48,49,113,112,49,97,112,96,37,
|
||||
37,100,52,112,49,49,49,33,116,36,100,100,52,52,52,52,112,117,97,33,
|
||||
37,37,37,49,49,97,116,48,33,49,49,37,37,101,33,49,36,37,97,97,100,
|
||||
97,100,100,100,97,101,96,100,36,101,100,96,97,33,48,101,112,112,112,
|
||||
48,49,49,100,113,36,100,100,48,112,112,112,112,96,112,48,52,52,52,
|
||||
100,100,100,52,116,36,100,100,52,52,52,52,52,48,52,36,37,37,37,49,
|
||||
49,49,37,53,33,49,49,37,37,37,53,97,113,97,100,36,97,97,100,100,100,
|
||||
49,25,68,100,48,33,49,49,37,37,37,37,37,116,116,96,97,100,97,100,100,
|
||||
36,53,100,96,100,100,97,101,36,97,33,53,52,48,113,96,101,100,100,36,
|
||||
112,49,48,49,113,112,112,112,96,117,37,37,52,52,52,100,100,36,113,
|
||||
101,48,49,49,33,52,52,37,52,48,52,36,37,37,37,49,49,49,117,116,32,
|
||||
49,49,52,49,33,37,37,116,52,97,97,97,97,100,100,48,33,100,96,100,116,
|
||||
96,97,97,97,33,97,97,112,112,112,48,49,49,113,112,49,48,49,113,112,
|
||||
112,112,112,96,112,48,52,52,52,100,100,100,52,116,36,100,100,52,52,
|
||||
52,116,36,101,37,49,49,33,37,49,49,49,97,65,176,177,97,36,100,100,
|
||||
52,52,52,52,52,112,113,33,37,49,37,49,49,49,116,48,33,49,49,37,53,
|
||||
49,36,37,116,112,96,100,33,53,49,49,49,96,101,96,100,100,97,97,97,
|
||||
33,117,53,52,112,112,112,48,49,49,100,37,49,48,49,113,112,112,52,112,
|
||||
96,112,96,52,52,52,100,100,100,52,116,36,100,100,112,36,112,33,52,
|
||||
112,113,36,37,37,37,49,49,97,52,48,116,100,36,33,37,37,37,49,36,37,
|
||||
97,97,97,97,100,100,100,97,101,96,100,100,97,97,97,97,33,97,97,112,
|
||||
112,112,48,49,49,113,100,100,48,49,113,112,112,112,49,52,53,100,100,
|
||||
36,52,100,100,100,52,112,226,102,36,49,48,49,113,112,112,112,112,96,
|
||||
101,37,52,100,52,100,100,100,112,97,36,100,100,52,116,100,48,52,112,
|
||||
97,33,49,37,116,100,100,100,32,53,33,49,49,37,37,37,37,116,117,112,
|
||||
96,97,97,97,100,100,48,37,32,96,100,100,97,97,113,96,33,97,97,112,
|
||||
112,112,48,49,49,113,101,113,49,49,97,49,49,112,112,96,101,49,52,52,
|
||||
52,100,100,36,49,96,36,100,100,37,52,52,52,52,48,52,36,37,37,37,49,
|
||||
49,49,37,53,33,49,49,37,37,37,37,37,36,37,97,97,97,97,100,100,100,
|
||||
113,101,100,100,100,97,97,97,101,112,96,48,49,49,112,48,49,49,113,
|
||||
101,43,57,49,100,96,100,100,97,97,97,97,33,53,53,112,48,113,48,49,
|
||||
49,97,37,49,48,49,113,112,49,97,112,96,37,37,100,52,112,49,49,49,33,
|
||||
116,36,100,100,52,52,52,52,112,117,97,33,37,37,37,49,49,97,116,48,
|
||||
33,49,49,37,37,101,33,37,36,37,97,100,97,97,100,100,100,97,101,96,
|
||||
100,36,101,100,101,97,33,53,101,112,112,112,48,49,49,100,33,53,48,
|
||||
49,53,112,112,112,48,97,112,48,52,52,52,100,100,100,52,116,36,100,
|
||||
100,52,52,52,52,52,48,52,36,37,37,37,49,49,49,37,53,33,49,49,37,37,
|
||||
37,53,97,113,97,100,100,96,97,100,100,100,113,24,68,100,48,33,49,49,
|
||||
37,37,37,37,37,116,116,96,97,100,97,100,100,36,53,100,96,100,100,97,
|
||||
101,36,97,33,53,52,48,113,96,101,100,100,36,112,49,48,49,113,112,112,
|
||||
112,96,117,37,37,52,52,52,100,100,36,113,36,49,100,100,52,52,52,37,
|
||||
52,48,100,36,37,37,37,49,49,49,37,53,33,49,49,52,49,33,37,37,116,52,
|
||||
97,97,97,97,100,100,48,33,100,96,100,116,96,97,97,97,33,97,97,112,
|
||||
112,112,48,49,49,113,112,49,48,49,113,112,112,112,112,96,112,48,52,
|
||||
52,52,100,100,100,52,33,32,100,100,52,52,52,116,36,101,37,49,49,33,
|
||||
37,49,49,49,53,65,176,177,97,36,100,100,52,52,52,52,52,112,113,33,
|
||||
37,49,37,49,49,49,116,48,33,49,49,37,53,49,36,37,116,112,96,100,33,
|
||||
53,49,49,49,96,101,96,100,100,97,97,97,33,117,53,52,112,112,112,48,
|
||||
49,49,100,37,49,48,49,113,112,112,52,112,96,112,48,52,52,52,100,100,
|
||||
100,52,116,36,100,100,112,100,36,52,52,112,113,36,37,37,37,49,49,97,
|
||||
52,117,33,49,113,33,37,37,37,49,36,37,97,97,97,97,100,100,100,97,101,
|
||||
96,100,100,97,97,97,97,33,97,97,112,112,112,48,49,49,113,112,49,48,
|
||||
49,113,112,112,112,49,52,53,100,100,36,100,100,100,100,52,36,183,51,
|
||||
49,49,49,49,113,112,112,112,112,48,49,33,52,100,52,36,48,49,49,49,
|
||||
49,49,49,33,52,113,53,52,100,100,32,49,37,37,33,100,100,100,100,100,
|
||||
100,100,32,37,37,37,37,49,49,96,97,97,97,32,49,49,49,49,49,49,49,96,
|
||||
97,49,97,97,100,36,112,112,112,48,96,100,100,100,100,100,100,36,100,
|
||||
100,112,112,48,49,33,52,52,52,36,48,49,49,49,49,49,49,33,52,52,52,
|
||||
52,100,100,32,37,37,37,33,100,100,100,100,100,100,100,32,37,37,37,
|
||||
37,37,49,96,97,97,97,32,49,49,49,49,49,49,49,96,97,97,49,49,100,36,
|
||||
100,100,112,48,96,100,100,97,127,108,100,100,100,100,100,97,100,100,
|
||||
100,100,97,100,100,100,36,53,96,100,100,100,100,100,100,36,112,53,
|
||||
49,49,113,32,100,52,36,32,36,48,49,49,49,49,49,49,97,117,117,117,101,
|
||||
52,100,100,112,117,33,112,49,49,49,49,49,49,49,117,37,37,49,49,49,
|
||||
49,49,49,49,96,32,49,49,49,49,49,49,49,96,100,100,97,100,97,36,112,
|
||||
112,53,32,48,49,49,49,49,49,49,113,48,49,49,49,113,48,97,37,32,52,
|
||||
52,100,100,100,100,100,100,100,52,100,100,36,112,32,100,52,52,52,32,
|
||||
117,49,49,49,49,49,49,49,33,52,52,32,117,49,49,116,117,117,100,32,
|
||||
49,49,33,88,17,49,49,49,49,49,49,117,117,117,117,49,49,116,117,117,
|
||||
100,97,100,100,100,100,100,100,36,48,49,33,117,117,100,36,117,53,113,
|
||||
53,49,49,49,49,49,49,49,49,49,49,49,113,53,49,97,101,100,100,100,100,
|
||||
100,100,100,100,100,100,100,52,52,100,113,101,100,112,117,117,49,49,
|
||||
49,49,49,49,49,49,49,49,113,116,49,113,48,49,49,49,33,100,100,100,
|
||||
100,100,100,100,100,100,100,117,117,117,117,100,100,100,36,112,112,
|
||||
48,49,49,49,49,49,49,113,112,117,53,49,49,49,49,49,49,97,101,100,100,
|
||||
100,100,100,100,100,100,100,100,32,49,49,49,49,49,49,117,49,49,49,
|
||||
97,85,229,228,100,100,100,100,100,36,112,112,112,48,49,49,33,116,101,
|
||||
36,48,49,49,49,49,49,49,113,48,49,113,48,49,49,101,32,52,100,52,100,
|
||||
100,100,100,100,100,100,100,100,100,100,100,100,100,97,32,37,49,37,
|
||||
49,49,49,49,49,49,49,113,117,53,101,53,49,97,117,49,48,96,100,100,
|
||||
100,100,100,100,100,100,97,100,100,97,100,100,36,112,112,48,49,49,
|
||||
49,49,49,49,49,49,113,113,36,37,52,100,100,100,100,97,97,49,100,100,
|
||||
100,100,100,100,100,49,96,53,49,49,49,49,49,49,49,49,49,49,49,49,49,
|
||||
49,49,49,49,49,49,37,49,49,49,49,49,97,101,97,100,100,96,183,51,49,
|
||||
49,49,49,97,37,100,100,100,36,49,117,33,49,37,112,49,49,49,49,49,49,
|
||||
49,117,117,117,97,53,100,100,32,52,33,116,117,100,100,100,100,100,
|
||||
100,100,117,117,117,117,112,49,49,32,117,117,117,53,49,49,49,49,49,
|
||||
49,113,53,96,33,53,96,100,36,112,112,101,117,101,100,100,100,100,100,
|
||||
100,116,117,37,96,117,101,100,112,117,117,117,117,49,49,49,49,49,49,
|
||||
49,117,33,52,52,116,96,100,117,117,32,37,48,100,100,100,100,100,100,
|
||||
100,97,117,117,117,117,100,36,117,117,117,100,53,49,49,49,49,49,49,
|
||||
113,117,117,117,117,53,49,97,117,117,37,96,101,100,100,49,127,76,100,
|
||||
28,102,97,110,108,32,100,96,100,100,100,97,97,97,33,53,37,113,48,113,
|
||||
48,49,49,97,48,96,48,49,113,112,49,97,112,96,37,37,100,52,112,49,49,
|
||||
49,97,117,36,100,100,52,52,52,52,112,33,36,36,37,37,37,49,49,97,100,
|
||||
113,37,49,49,37,37,101,33,37,117,36,97,97,97,97,100,100,100,49,117,
|
||||
100,100,36,101,36,97,97,33,53,101,112,112,112,48,49,49,100,49,112,
|
||||
48,49,113,112,112,112,112,96,32,37,52,52,52,100,100,100,116,117,36,
|
||||
100,100,52,52,52,52,52,112,97,33,37,37,37,49,49,49,53,37,100,100,100,
|
||||
32,37,37,53,97,113,113,49,49,53,96,100,100,100,117,76,102,32,59,57,
|
||||
97,96,97,100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,97,37,49,
|
||||
48,49,49,49,32,112,112,96,37,37,100,52,112,49,49,49,33,37,52,100,100,
|
||||
52,52,52,52,112,117,97,33,37,37,37,49,49,97,116,48,33,49,49,37,37,
|
||||
101,33,37,36,37,97,97,97,97,100,100,100,97,101,96,100,100,113,100,
|
||||
96,97,33,48,101,112,112,112,48,49,49,100,37,49,48,49,53,112,112,112,
|
||||
112,96,112,48,52,52,52,100,100,100,52,53,32,100,100,52,52,52,52,52,
|
||||
48,52,36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,53,97,113,97,100,
|
||||
100,96,97,100,100,100,49,76,102,117,110,108,116,48,100,100,100,97,
|
||||
97,97,97,33,53,53,112,48,113,48,49,49,97,36,97,100,100,36,112,49,97,
|
||||
112,96,101,52,100,52,112,49,49,49,33,112,117,49,49,33,52,52,52,112,
|
||||
117,97,33,37,37,37,49,49,97,36,49,97,100,100,32,37,101,33,37,36,37,
|
||||
97,97,97,97,100,100,100,117,101,96,100,100,113,100,96,97,33,48,101,
|
||||
112,112,112,48,49,49,100,37,49,48,49,53,112,112,112,112,96,32,37,52,
|
||||
52,52,100,100,100,52,37,49,100,100,52,52,52,52,52,48,100,36,37,37,
|
||||
37,49,49,49,37,53,33,49,49,37,37,37,53,97,113,97,100,100,96,97,100,
|
||||
100,100,37,76,102,52,110,108,100,101,96,100,100,100,97,97,97,33,53,
|
||||
53,112,48,113,48,49,49,97,37,49,48,49,49,113,117,112,112,96,37,37,
|
||||
100,52,112,49,49,49,33,116,36,100,100,100,52,52,52,112,117,97,33,37,
|
||||
37,37,49,49,97,116,48,33,49,49,37,37,101,33,37,117,36,97,97,97,97,
|
||||
100,100,100,113,96,97,100,36,101,100,96,97,33,53,101,112,112,112,48,
|
||||
49,49,100,117,37,48,49,113,112,112,112,112,96,112,48,52,52,52,100,
|
||||
100,100,52,116,36,100,100,52,52,52,52,52,48,52,36,37,37,37,49,49,49,
|
||||
37,96,100,100,100,100,32,37,53,97,113,97,100,100,96,97,100,100,100,
|
||||
33,24,51,48,110,108,32,100,96,100,100,100,97,97,97,33,53,53,112,48,
|
||||
113,48,49,49,97,100,32,48,49,113,112,49,97,112,96,37,37,100,52,112,
|
||||
49,49,49,33,37,32,49,49,33,52,52,52,112,117,97,33,37,37,37,49,49,97,
|
||||
36,97,117,100,100,32,37,101,33,37,36,37,97,97,97,97,100,100,100,49,
|
||||
100,100,100,36,112,96,96,97,33,53,101,112,112,112,48,49,49,100,37,
|
||||
49,48,49,113,112,112,112,112,96,112,48,52,52,52,100,100,100,52,33,
|
||||
32,100,100,52,52,52,52,52,48,52,36,37,37,37,49,49,49,37,53,33,49,49,
|
||||
37,37,37,53,97,113,97,100,100,96,97,100,100,100,53,24,51,117,59,57,
|
||||
97,101,100,100,100,97,97,97,97,33,53,117,113,48,113,48,49,49,97,37,
|
||||
49,48,49,113,112,113,113,112,112,112,37,100,52,112,49,49,49,33,116,
|
||||
36,100,100,52,100,52,52,112,117,97,33,37,37,37,49,49,97,116,48,33,
|
||||
49,49,37,37,101,33,37,117,36,97,97,97,97,100,100,100,97,101,96,100,
|
||||
36,101,100,96,97,33,53,101,112,112,112,48,49,49,52,100,100,48,49,53,
|
||||
112,112,112,112,96,112,48,52,52,52,100,100,100,52,116,36,100,100,100,
|
||||
52,52,52,52,48,52,36,37,37,37,49,49,49,37,52,48,49,49,37,49,37,53,
|
||||
97,113,97,100,100,96,97,100,100,100,113,77,102,37,110,108,112,116,
|
||||
97,100,100,97,97,97,97,97,97,48,112,48,113,48,49,49,97,112,96,100,
|
||||
100,36,112,49,97,112,112,112,37,100,52,112,49,49,49,33,49,32,49,49,
|
||||
33,52,52,52,112,117,97,33,37,37,37,49,49,97,36,48,33,49,49,49,37,101,
|
||||
33,37,36,37,97,97,97,97,100,100,100,33,37,97,100,36,101,100,96,100,
|
||||
33,53,101,112,112,112,48,49,49,100,113,49,49,49,97,37,112,112,112,
|
||||
96,32,37,52,52,52,100,100,100,116,52,48,49,49,33,52,52,52,52,48,116,
|
||||
37,37,37,37,49,49,49,37,53,33,49,49,37,37,37,53,97,113,97,100,100,
|
||||
96,97,100,100,100,101,77,102,36,58,57,49,100,96,100,100,97,97,97,97,
|
||||
33,53,53,112,48,113,48,49,49,97,37,49,48,49,113,112,112,97,112,96,
|
||||
37,37,100,52,112,49,49,49,33,116,36,100,100,52,52,100,52,112,117,97,
|
||||
33,37,37,37,49,49,97,52,37,97,100,100,32,37,101,33,37,36,37,97,97,
|
||||
97,97,100,100,100,97,101,96,100,36,101,100,96,97,33,53,101,112,112,
|
||||
112,48,49,49,100,37,49,48,49,53,112,112,112,112,96,112,48,52,52,52,
|
||||
100,100,100,52,116,36,100,100,52,100,52,52,52,96,52,36,37,37,37,49,
|
||||
49,49,101,36,96,100,100,32,37,49,53,97,113,97,100,100,96,97,100,100,
|
||||
100,97,73,102,33,58,57,101,100,48,49,49,96,97,97,97,97,97,48,112,48,
|
||||
113,48,49,49,97,49,112,48,49,113,112,49,97,112,96,37,32,100,52,112,
|
||||
49,49,49,33,112,96,100,100,52,52,52,52,112,117,97,33,37,37,37,49,49,
|
||||
97,52,33,37,49,49,37,37,101,33,37,116,112,96,97,97,100,100,100,100,
|
||||
97,101,96,100,36,101,49,53,96,36,53,37,49,113,112,48,49,49,53,36,49,
|
||||
49,49,101,112,112,112,112,96,112,48,52,52,52,100,100,100,52,116,36,
|
||||
100,100,52,52,52,52,52,48,52,36,37,37,37,49,49,49,101,33,37,49,49,
|
||||
37,37,37,49,49,37,33,100,100,100,97,100,100,100,117,73,102,96,58,57,
|
||||
49,100,96,100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,97,37,49,
|
||||
48,49,113,112,49,97,112,96,37,37,100,52,112,49,49,49,33,116,36,100,
|
||||
100,52,52,52,100,112,117,97,33,37,37,37,49,49,97,116,48,33,49,49,37,
|
||||
37,101,33,37,36,37,97,97,97,97,100,100,100,33,53,96,100,36,53,32,53,
|
||||
96,33,53,101,112,112,112,48,49,49,112,37,49,48,49,53,112,112,112,112,
|
||||
96,112,48,52,52,52,100,100,100,52,97,52,100,100,52,52,52,100,52,48,
|
||||
52,36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,53,97,113,97,100,100,
|
||||
96,97,100,100,100,49,73,102,53,58,57,101,112,53,49,49,96,97,97,97,
|
||||
33,53,53,112,48,113,48,49,49,97,37,49,48,49,113,112,49,97,112,96,37,
|
||||
37,100,52,112,49,49,49,97,113,116,100,100,52,52,52,52,112,117,97,33,
|
||||
37,37,37,49,49,97,116,48,33,49,49,37,37,101,33,37,116,112,96,97,97,
|
||||
100,100,100,100,97,101,96,100,36,101,100,96,97,36,53,37,49,113,112,
|
||||
48,49,49,100,100,49,48,49,53,112,112,112,112,96,112,48,52,52,52,100,
|
||||
100,100,52,116,36,100,100,52,52,52,52,52,48,52,36,37,37,37,49,49,49,
|
||||
37,53,33,49,49,37,37,37,37,49,37,33,100,100,100,97,100,100,100,37,
|
||||
73,102,116,111,108,100,101,96,100,100,97,97,97,97,97,97,48,112,48,
|
||||
113,48,49,49,97,117,37,48,49,113,112,49,97,112,96,37,32,100,52,112,
|
||||
49,49,49,33,116,36,100,100,52,52,52,52,112,117,97,33,49,37,37,49,49,
|
||||
97,101,117,32,49,49,37,37,101,33,37,36,37,97,97,97,97,100,100,100,
|
||||
113,96,100,100,36,101,49,53,96,33,53,101,112,112,112,48,49,49,53,112,
|
||||
49,48,49,117,113,112,112,112,96,112,48,52,52,52,100,100,100,52,49,
|
||||
100,100,100,52,52,52,52,100,48,52,36,37,37,37,49,49,49,37,116,32,49,
|
||||
49,37,37,37,97,52,113,97,100,100,96,97,100,100,100,33,29,51,112,111,
|
||||
108,32,100,96,100,100,97,97,97,97,33,53,53,112,48,49,49,49,49,97,112,
|
||||
37,48,49,113,112,49,97,112,96,37,37,100,100,112,49,49,49,49,53,32,
|
||||
100,100,52,52,52,52,112,117,97,33,49,37,37,49,49,97,101,48,33,49,49,
|
||||
37,37,101,33,37,36,112,96,97,97,97,100,100,100,113,96,97,100,36,53,
|
||||
113,53,96,36,53,37,49,113,112,48,49,49,100,52,117,48,49,53,112,112,
|
||||
112,112,96,112,48,52,52,52,100,100,100,52,116,36,100,100,52,52,52,
|
||||
52,52,48,52,36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,37,49,37,
|
||||
33,100,100,100,97,100,100,100,53,29,51,53,58,57,97,97,48,49,49,96,
|
||||
97,97,97,33,53,53,112,48,113,48,49,49,97,37,49,48,49,113,112,49,97,
|
||||
112,96,37,37,100,52,52,100,100,100,52,116,36,100,100,52,52,52,52,112,
|
||||
37,113,36,37,37,37,49,49,97,52,33,49,49,49,37,37,101,33,37,116,37,
|
||||
97,97,97,100,100,100,100,97,101,96,100,36,101,100,96,97,33,53,101,
|
||||
112,112,112,48,49,49,36,36,49,48,49,53,112,112,112,112,112,101,53,
|
||||
52,52,52,100,100,100,52,37,37,100,100,52,52,52,52,52,48,52,48,37,37,
|
||||
37,49,49,49,101,33,49,49,49,37,37,37,53,97,113,97,100,100,96,97,100,
|
||||
100,100,113,72,102,101,111,108,32,100,96,100,100,97,97,97,97,33,48,
|
||||
53,112,48,113,48,49,49,97,32,49,48,49,113,112,49,97,112,96,37,37,100,
|
||||
100,100,100,100,100,36,113,36,100,100,52,52,52,52,112,117,97,33,37,
|
||||
37,37,49,49,97,116,48,33,49,49,37,37,101,33,37,116,112,96,97,97,97,
|
||||
100,100,100,97,101,96,100,36,101,100,96,97,36,53,101,112,112,112,48,
|
||||
49,49,100,48,49,100,100,48,112,112,112,112,112,101,53,52,52,52,100,
|
||||
100,100,52,116,36,100,100,52,52,52,52,52,48,52,36,37,37,37,49,49,49,
|
||||
37,53,33,49,49,37,37,37,53,97,36,97,100,100,96,97,100,100,100,101,
|
||||
72,102,100,107,108,116,49,48,49,49,96,97,97,97,33,53,97,37,48,113,
|
||||
48,49,49,97,33,36,100,100,36,112,49,97,112,96,37,37,100,52,112,49,
|
||||
49,49,33,116,36,100,100,52,52,52,52,32,117,97,101,32,49,37,49,49,49,
|
||||
52,36,49,49,49,37,37,101,33,37,36,37,97,97,97,100,100,100,100,113,
|
||||
48,97,100,36,101,100,96,97,33,53,37,49,113,112,48,49,49,100,37,49,
|
||||
48,49,53,112,112,112,112,96,112,48,52,52,52,100,100,100,52,112,116,
|
||||
100,100,52,52,52,52,52,48,52,36,49,37,37,49,49,49,101,97,36,49,49,
|
||||
37,37,37,53,97,113,97,100,100,96,97,100,100,100,97,8,51,96,107,108,
|
||||
32,100,96,100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,113,116,
|
||||
49,49,49,113,112,49,97,112,96,37,37,100,100,112,49,49,49,33,113,101,
|
||||
100,100,52,52,52,52,112,117,97,101,32,49,37,49,49,49,116,48,33,49,
|
||||
49,37,37,101,33,37,36,112,96,97,97,97,100,100,100,97,101,96,100,36,
|
||||
101,100,96,97,33,53,101,48,113,112,48,49,49,100,48,116,101,100,48,
|
||||
112,112,112,112,112,101,48,52,52,52,100,100,100,52,116,36,100,100,
|
||||
52,52,52,52,52,48,52,36,37,37,37,49,49,49,101,48,49,49,49,37,37,37,
|
||||
53,97,116,97,100,100,96,97,100,100,100,117,8,51,37,106,108,116,52,
|
||||
53,49,49,96,97,97,97,33,53,53,112,48,113,48,49,49,97,37,49,48,49,113,
|
||||
112,49,97,112,96,37,37,100,52,32,49,49,49,33,116,36,100,100,52,52,
|
||||
52,52,112,37,113,36,37,37,37,49,49,97,52,97,36,49,49,37,37,101,33,
|
||||
37,116,37,97,97,97,97,100,100,100,49,100,97,100,36,101,100,96,97,33,
|
||||
53,37,113,112,112,48,49,49,100,37,49,48,49,53,112,112,112,112,96,112,
|
||||
53,52,52,52,100,100,100,52,32,117,49,49,33,52,52,52,52,48,52,36,37,
|
||||
49,37,49,49,49,37,53,33,49,49,37,37,37,53,97,113,97,100,100,96,97,
|
||||
100,100,100,49,8,51,116,107,108,32,100,96,100,100,97,97,97,97,33,53,
|
||||
101,112,48,113,48,49,49,49,37,49,49,49,113,112,49,97,112,96,37,37,
|
||||
100,52,112,49,49,49,113,96,36,100,100,52,52,52,52,112,117,97,33,37,
|
||||
37,37,49,49,97,52,53,49,49,49,37,37,101,33,37,116,112,96,97,97,97,
|
||||
100,100,100,37,117,97,100,36,101,100,96,97,33,53,101,112,112,112,48,
|
||||
49,49,100,32,49,48,49,53,112,112,112,112,96,112,96,100,52,52,100,100,
|
||||
100,116,33,48,100,100,52,52,52,52,52,48,52,36,37,37,37,49,49,49,101,
|
||||
100,36,49,49,37,37,37,101,97,113,33,101,100,96,97,100,100,100,37,8,
|
||||
51,33,107,108,36,48,96,100,100,97,97,97,100,36,53,53,112,48,113,48,
|
||||
49,49,97,37,49,48,49,113,112,49,97,112,96,37,37,100,52,32,49,49,49,
|
||||
33,48,36,49,49,33,52,52,52,112,117,97,33,37,49,37,49,49,97,116,48,
|
||||
33,49,49,37,37,101,33,37,36,37,97,97,97,97,100,100,100,97,101,96,100,
|
||||
36,101,100,96,97,97,97,36,112,112,112,48,49,49,100,113,48,100,100,
|
||||
48,112,112,112,112,96,112,48,52,52,52,100,100,100,52,116,36,100,100,
|
||||
52,52,52,52,52,96,52,36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,
|
||||
53,97,113,97,100,100,96,97,100,100,100,33,12,51,48,107,108,100,101,
|
||||
96,100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,97,49,36,49,49,
|
||||
113,112,49,97,112,96,37,37,100,52,112,49,49,49,97,100,53,100,100,52,
|
||||
52,52,52,112,117,33,32,37,37,37,49,49,97,116,48,33,49,49,37,37,101,
|
||||
33,37,36,37,97,97,97,97,100,100,100,53,100,48,49,113,101,100,96,97,
|
||||
33,53,101,112,112,112,48,49,49,100,32,49,48,49,53,112,112,112,112,
|
||||
96,117,48,52,52,52,100,100,100,52,37,97,100,100,52,52,52,52,52,48,
|
||||
52,36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,37,37,116,52,33,117,
|
||||
53,96,100,100,100,53,12,51,117,106,108,52,52,100,100,100,97,97,97,
|
||||
97,33,53,53,112,48,113,48,49,49,33,36,49,48,49,113,112,48,113,112,
|
||||
96,37,37,100,52,112,49,49,49,33,116,36,100,100,52,52,52,52,112,117,
|
||||
97,33,37,37,37,49,49,97,116,101,101,100,100,32,37,101,33,37,48,37,
|
||||
97,97,97,97,100,100,100,97,101,96,100,36,101,100,96,97,97,97,36,112,
|
||||
112,112,48,49,49,100,113,32,48,49,53,112,112,112,112,96,112,48,52,
|
||||
52,52,100,100,100,52,116,36,100,100,52,52,52,52,52,96,52,36,37,37,
|
||||
37,49,49,49,101,36,49,49,49,37,37,37,53,117,113,97,113,117,49,96,100,
|
||||
100,100,113,9,51,36,107,108,48,36,49,49,49,96,97,97,97,33,48,53,112,
|
||||
48,113,48,49,49,97,52,52,48,49,113,112,116,116,36,96,37,37,100,52,
|
||||
112,49,49,49,97,49,48,49,49,33,52,52,52,112,117,97,33,37,37,37,49,
|
||||
49,97,52,101,96,100,100,32,37,101,33,37,36,37,97,97,97,97,100,100,
|
||||
100,53,112,53,49,113,101,100,96,97,97,97,96,112,112,112,48,49,49,100,
|
||||
49,100,48,49,53,112,112,112,112,32,113,48,52,52,52,100,100,100,116,
|
||||
117,36,100,100,52,52,52,52,52,48,52,36,37,37,49,49,49,49,37,32,53,
|
||||
49,49,37,37,37,117,52,113,97,52,49,53,96,100,100,100,101,9,51,113,
|
||||
63,57,49,100,96,100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,97,
|
||||
37,49,48,49,113,112,49,97,112,96,37,37,100,52,112,49,49,49,33,116,
|
||||
36,100,100,52,52,52,52,112,117,33,32,37,37,37,49,49,97,116,48,33,49,
|
||||
49,37,49,101,33,37,36,37,97,97,97,97,100,100,100,97,101,96,100,36,
|
||||
101,100,96,97,33,53,113,112,112,112,48,49,49,100,37,49,48,49,53,112,
|
||||
112,112,112,96,112,48,52,52,52,100,100,100,52,32,96,100,100,52,52,
|
||||
52,52,52,48,52,36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,53,97,
|
||||
113,97,100,100,96,97,100,100,100,97,93,102,33,63,57,37,100,96,100,
|
||||
100,97,97,97,97,33,53,101,112,48,113,48,49,49,97,49,101,101,100,36,
|
||||
112,101,97,112,96,37,37,100,52,112,49,49,49,97,33,48,100,100,52,52,
|
||||
52,52,112,117,97,33,37,37,37,49,49,97,52,96,96,100,100,32,37,101,33,
|
||||
37,36,37,97,97,97,97,100,100,100,49,49,97,100,36,101,100,96,97,33,
|
||||
53,101,112,112,112,48,49,49,100,113,36,100,100,48,112,112,112,112,
|
||||
96,112,48,52,52,52,100,100,100,116,117,36,100,100,52,52,52,52,52,48,
|
||||
52,36,37,37,37,49,49,49,117,53,33,49,49,37,37,37,53,97,113,97,100,
|
||||
100,96,97,100,100,100,117,93,102,96,63,57,33,36,53,49,49,96,100,100,
|
||||
100,36,53,53,48,49,113,48,49,49,97,37,49,48,49,113,112,49,97,112,96,
|
||||
37,37,100,52,112,49,49,49,33,116,36,100,100,52,52,52,52,112,117,97,
|
||||
33,37,37,49,49,49,97,116,48,33,49,49,37,37,113,33,37,36,37,97,97,97,
|
||||
97,100,100,100,97,101,96,100,36,101,100,96,97,33,53,101,112,48,113,
|
||||
48,49,49,100,37,49,48,49,53,112,48,113,112,96,112,48,52,100,52,100,
|
||||
100,100,52,37,52,100,100,52,100,52,52,52,48,52,36,37,37,49,49,49,49,
|
||||
101,117,36,49,49,37,37,37,53,100,113,97,100,52,53,96,100,100,100,49,
|
||||
93,102,53,63,57,37,100,96,100,100,97,97,97,97,33,53,101,112,48,113,
|
||||
48,49,49,97,97,36,49,49,113,112,101,97,112,96,37,37,100,52,112,49,
|
||||
49,49,33,116,36,100,100,52,52,52,52,112,117,97,33,37,37,37,49,49,97,
|
||||
52,48,49,49,49,37,37,101,33,37,36,37,97,97,97,100,100,100,100,117,
|
||||
101,96,100,36,101,100,96,97,33,53,101,112,48,113,48,49,49,100,33,36,
|
||||
100,100,48,112,112,112,112,96,112,48,52,52,52,100,100,100,116,112,
|
||||
53,100,100,52,52,52,52,52,116,49,36,37,37,37,49,49,49,37,53,33,49,
|
||||
49,37,37,37,53,117,113,97,100,100,96,97,100,100,100,37,93,102,116,
|
||||
106,108,52,116,96,100,100,97,97,100,100,36,53,53,48,49,113,48,49,49,
|
||||
97,37,49,48,49,113,112,97,117,112,96,37,37,100,52,112,49,49,49,33,
|
||||
53,113,49,49,33,52,52,52,112,117,97,33,37,37,37,49,49,49,49,53,33,
|
||||
49,49,37,37,101,33,37,36,37,97,97,97,97,100,100,100,113,53,97,100,
|
||||
36,101,100,96,97,33,53,101,112,112,112,48,49,49,100,37,49,48,49,53,
|
||||
48,113,112,112,96,112,48,52,52,100,100,100,100,52,116,36,100,100,52,
|
||||
52,52,52,52,48,52,36,37,37,37,49,49,49,101,33,96,100,100,32,37,37,
|
||||
53,97,113,97,100,100,96,97,100,100,100,33,9,51,112,106,108,32,100,
|
||||
96,100,100,97,97,97,97,33,53,101,112,48,113,48,49,49,97,117,97,48,
|
||||
49,113,112,49,97,112,96,37,37,100,52,112,49,49,49,97,97,32,100,100,
|
||||
52,52,52,52,112,117,97,33,37,37,37,49,49,33,101,36,32,49,49,37,37,
|
||||
37,116,32,36,37,97,97,97,97,100,100,100,33,96,101,100,36,101,100,96,
|
||||
97,33,53,101,112,112,112,48,49,49,100,113,32,48,49,53,112,112,112,
|
||||
112,96,112,48,52,52,52,100,100,100,116,97,36,49,49,33,52,52,52,52,
|
||||
48,52,36,37,37,37,49,49,49,101,100,53,49,49,37,37,37,53,97,113,97,
|
||||
100,100,96,97,100,100,100,53,9,51,53,63,57,97,117,96,100,100,97,97,
|
||||
97,100,36,53,53,48,49,113,48,49,49,97,37,49,48,49,113,112,97,117,112,
|
||||
96,37,37,100,52,112,49,49,49,33,116,36,100,100,52,52,52,52,112,117,
|
||||
97,33,37,37,37,49,49,113,33,53,33,49,49,37,37,101,48,37,36,117,97,
|
||||
97,97,97,100,100,100,97,101,96,100,36,101,100,96,97,33,53,101,112,
|
||||
48,113,48,49,49,100,37,49,48,49,53,112,112,112,112,96,112,48,52,52,
|
||||
52,100,100,100,100,116,36,100,100,52,52,52,52,52,116,49,36,37,37,37,
|
||||
49,49,49,37,53,33,49,49,37,37,37,53,33,36,116,100,100,96,97,100,100,
|
||||
100,113,92,102,101,106,108,96,97,53,49,49,96,97,97,97,33,53,53,112,
|
||||
48,113,48,49,49,97,32,49,48,49,113,112,49,97,112,96,37,37,100,52,112,
|
||||
49,49,49,97,117,36,100,100,52,52,52,52,112,117,97,33,37,37,37,49,49,
|
||||
97,36,37,100,100,100,32,37,101,36,37,36,37,97,97,97,97,100,100,100,
|
||||
117,101,96,100,36,101,100,96,97,33,53,101,112,112,48,49,49,49,100,
|
||||
37,49,48,49,53,112,112,112,112,96,32,37,52,52,52,100,100,100,116,33,
|
||||
117,49,49,33,52,52,52,52,116,49,36,37,37,37,49,49,49,101,97,36,49,
|
||||
49,37,37,37,53,33,48,116,112,112,96,97,100,100,100,101,92,102,100,
|
||||
42,57,49,100,96,100,100,97,97,97,100,36,53,101,48,49,113,48,49,49,
|
||||
97,49,112,48,49,113,112,49,33,113,32,36,37,100,52,112,49,49,49,33,
|
||||
33,33,49,49,33,52,52,52,32,117,97,33,37,37,37,49,49,33,97,48,33,49,
|
||||
49,37,37,37,96,32,36,117,97,97,97,97,100,100,100,113,97,48,49,113,
|
||||
101,100,96,97,33,53,101,112,112,112,48,49,49,100,49,48,49,49,53,112,
|
||||
112,112,112,96,112,48,52,52,52,100,100,100,52,116,36,100,100,52,52,
|
||||
52,52,52,48,52,36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,53,97,
|
||||
113,33,53,97,53,96,100,100,100,97,28,102,97,42,57,37,100,96,100,100,
|
||||
97,97,97,97,33,53,53,112,48,113,48,49,49,97,32,49,48,49,113,112,49,
|
||||
97,48,97,37,37,100,52,112,49,49,49,97,32,116,49,49,33,52,52,52,112,
|
||||
117,97,33,37,37,37,49,49,97,48,33,36,49,49,37,37,101,33,37,36,37,97,
|
||||
97,97,97,100,100,100,97,101,96,100,36,101,100,96,97,33,53,101,112,
|
||||
112,112,48,49,49,53,112,49,48,49,53,112,112,112,112,96,32,37,52,52,
|
||||
52,100,100,100,116,117,36,100,100,52,52,52,52,52,48,52,36,37,37,37,
|
||||
49,49,49,49,53,33,49,49,37,37,37,53,97,113,97,49,49,53,96,100,100,
|
||||
100,117,28,102,32,47,57,113,96,101,100,100,97,97,97,97,36,53,101,112,
|
||||
48,113,48,49,49,97,53,32,49,49,113,112,49,97,112,96,37,37,100,52,112,
|
||||
49,49,49,33,116,36,100,100,52,52,52,52,112,117,97,33,37,37,37,49,49,
|
||||
97,33,53,33,49,49,37,37,101,33,37,36,37,97,97,97,97,100,100,100,52,
|
||||
97,100,100,36,101,49,53,96,36,53,101,112,112,112,48,49,49,100,97,48,
|
||||
49,49,53,112,112,112,112,96,112,48,52,52,52,100,100,100,52,53,36,49,
|
||||
49,33,52,52,52,52,48,52,36,37,37,37,49,49,49,37,116,117,100,100,32,
|
||||
37,37,53,97,113,97,100,100,96,97,100,100,100,49,28,102,117,42,57,37,
|
||||
100,96,100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,97,100,49,
|
||||
48,49,113,112,49,97,112,96,37,37,100,52,112,49,49,49,33,116,36,100,
|
||||
100,52,52,52,52,52,112,97,33,37,37,37,49,49,97,116,48,33,49,49,37,
|
||||
37,37,116,32,36,37,97,97,97,97,100,100,100,113,101,100,100,36,37,53,
|
||||
53,96,36,53,101,112,112,112,48,49,49,100,37,49,48,49,53,112,112,112,
|
||||
112,96,32,37,52,52,52,100,100,100,116,117,36,100,100,52,52,52,52,52,
|
||||
48,96,33,37,37,37,49,49,49,101,97,53,49,49,37,37,37,53,97,113,97,100,
|
||||
100,96,97,100,100,100,37,28,102,52,42,57,33,100,100,100,100,97,97,
|
||||
97,97,33,53,101,112,48,113,48,49,49,97,37,49,48,49,113,112,49,97,112,
|
||||
96,37,53,49,33,112,49,49,49,33,97,97,100,100,52,52,52,52,112,117,97,
|
||||
33,37,37,37,49,49,97,116,117,97,100,100,32,37,101,33,37,36,37,97,97,
|
||||
97,97,100,100,100,97,101,96,100,36,101,100,96,97,33,53,101,112,112,
|
||||
112,48,49,49,101,52,100,48,49,53,112,112,112,112,96,112,48,52,52,52,
|
||||
100,100,100,52,53,33,49,49,33,52,52,52,52,48,52,36,37,37,37,49,49,
|
||||
49,37,53,33,49,49,37,37,37,53,97,113,97,112,100,96,97,100,100,100,
|
||||
33,8,102,49,42,57,53,100,53,49,49,96,97,97,97,33,53,101,112,48,113,
|
||||
48,49,49,97,37,49,48,49,113,112,49,97,112,96,37,37,100,52,112,49,49,
|
||||
49,97,52,48,49,49,33,52,52,52,52,112,97,33,37,37,37,49,49,97,116,48,
|
||||
33,49,49,37,37,101,36,37,36,37,97,97,97,97,100,100,100,101,112,96,
|
||||
100,36,101,100,96,97,33,53,101,112,112,112,48,49,49,49,33,97,100,100,
|
||||
48,112,112,112,112,96,112,48,52,52,52,100,100,100,116,117,36,100,100,
|
||||
52,52,52,52,52,48,52,36,37,37,37,49,49,49,37,96,32,49,49,37,37,37,
|
||||
53,97,113,97,100,49,53,96,100,100,100,53,8,102,112,47,57,49,100,96,
|
||||
100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,97,37,49,48,49,113,
|
||||
112,49,97,112,96,37,37,100,52,112,49,49,49,33,116,36,100,100,52,52,
|
||||
52,52,112,117,97,33,37,37,37,49,49,97,52,100,48,49,49,37,37,101,33,
|
||||
37,36,37,97,97,97,97,100,100,100,97,101,96,100,36,101,36,97,97,33,
|
||||
53,101,112,112,112,48,49,49,100,37,49,48,49,53,112,112,48,113,96,112,
|
||||
48,52,52,52,100,100,100,52,32,33,100,100,52,52,100,52,52,48,52,36,
|
||||
37,37,37,49,49,49,37,53,33,49,49,37,37,37,53,97,113,97,36,101,96,97,
|
||||
100,100,100,113,29,102,37,42,57,49,100,96,100,100,97,97,97,97,33,53,
|
||||
53,112,48,113,48,49,49,97,37,49,48,49,113,112,49,97,112,96,37,37,100,
|
||||
52,112,49,49,49,33,116,36,100,100,52,52,52,52,112,117,97,33,37,37,
|
||||
37,49,49,97,116,48,33,49,49,37,37,101,53,37,36,37,97,97,97,97,100,
|
||||
100,100,97,101,96,100,36,101,100,96,97,33,53,101,112,112,112,48,49,
|
||||
49,100,36,97,100,100,48,112,112,112,112,96,48,49,52,52,52,100,100,
|
||||
100,52,116,36,100,100,52,52,52,52,52,48,52,36,37,37,37,49,49,49,101,
|
||||
100,48,49,49,37,37,37,53,97,113,97,36,37,97,97,100,100,100,101,29,
|
||||
102,36,46,57,49,100,96,100,100,97,97,97,97,33,53,53,112,48,113,48,
|
||||
49,49,97,37,49,48,49,113,112,49,97,112,96,37,37,100,52,112,49,49,49,
|
||||
33,116,36,100,100,52,52,52,52,112,117,97,33,37,37,37,49,49,97,52,33,
|
||||
116,100,100,32,37,101,33,37,36,37,97,97,97,97,100,100,100,113,112,
|
||||
96,100,36,101,100,96,97,33,53,101,112,112,112,48,49,49,112,37,49,48,
|
||||
49,53,112,112,112,112,96,112,48,52,52,52,100,100,100,52,116,36,100,
|
||||
100,52,52,52,52,52,48,52,36,37,37,37,49,49,49,37,53,33,49,49,37,37,
|
||||
37,53,97,113,97,100,117,101,97,100,100,100,97,25,102,33,46,57,49,100,
|
||||
96,100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,97,37,49,48,49,
|
||||
113,112,49,97,112,96,37,37,100,52,112,49,49,49,33,116,36,100,100,52,
|
||||
52,52,52,112,117,97,33,37,37,37,49,49,97,52,37,32,49,49,37,37,101,
|
||||
33,37,36,37,97,97,97,97,100,100,100,33,33,96,100,36,101,100,101,97,
|
||||
33,53,101,112,112,112,48,49,49,100,32,49,48,49,53,112,112,112,112,
|
||||
96,48,49,52,52,52,100,100,100,52,116,36,100,100,52,52,52,52,52,48,
|
||||
52,36,37,37,37,49,49,49,37,116,100,100,100,32,37,37,53,97,113,97,100,
|
||||
100,101,97,100,100,100,117,25,102,96,46,57,49,100,96,100,100,97,97,
|
||||
97,97,33,53,53,112,48,113,48,49,49,97,37,49,48,49,113,112,49,97,112,
|
||||
96,37,37,100,52,112,49,49,49,33,116,36,100,100,52,52,52,52,112,117,
|
||||
97,33,37,37,37,49,49,97,116,48,33,49,49,37,37,101,33,49,36,37,97,97,
|
||||
100,97,100,100,100,97,101,96,100,36,101,100,96,97,33,48,101,112,112,
|
||||
112,48,49,49,100,113,36,100,100,48,112,112,112,112,96,112,48,52,52,
|
||||
52,100,100,100,52,116,36,100,100,52,52,52,52,52,48,52,36,37,37,37,
|
||||
49,49,49,37,53,33,49,49,37,37,37,53,97,113,97,100,36,97,97,100,100,
|
||||
100,49,25,102,53,46,57,49,100,96,100,100,97,97,97,97,33,53,53,112,
|
||||
48,113,48,49,49,97,37,49,48,49,113,112,49,97,112,96,37,37,100,52,112,
|
||||
49,49,49,33,116,36,100,100,52,52,52,52,112,117,97,33,37,37,37,49,49,
|
||||
97,116,49,100,100,100,32,37,101,33,37,36,37,97,97,97,97,100,100,100,
|
||||
53,53,96,100,36,101,100,96,97,33,53,101,112,112,112,48,49,49,100,32,
|
||||
49,48,49,53,112,112,112,112,96,112,48,52,52,52,100,100,100,52,116,
|
||||
36,100,100,52,52,52,52,52,48,52,36,37,37,37,49,49,49,37,53,33,49,49,
|
||||
37,37,37,53,97,113,97,100,100,96,97,100,100,100,112,24,102,116,43,
|
||||
57,49,100,96,100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,97,37,
|
||||
49,48,49,113,112,49,97,112,96,37,37,100,52,112,49,49,49,33,116,36,
|
||||
100,100,52,52,52,52,112,117,97,33,37,37,37,49,49,97,116,48,33,49,49,
|
||||
37,37,101,33,37,36,37,100,97,97,97,100,100,100,97,101,96,100,36,101,
|
||||
32,53,96,33,53,101,112,112,112,48,49,49,100,33,97,101,100,48,112,112,
|
||||
112,48,97,112,48,52,52,52,100,100,100,52,116,36,100,100,52,52,52,52,
|
||||
52,48,52,36,37,37,37,49,49,49,101,100,36,49,49,37,37,37,53,97,113,
|
||||
97,100,100,96,97,100,100,100,33,13,102,113,43,57,49,100,96,100,100,
|
||||
97,97,97,97,33,53,53,112,48,113,48,49,49,97,37,49,48,49,113,112,49,
|
||||
97,112,96,37,37,100,52,112,49,49,49,33,116,36,100,100,52,52,52,52,
|
||||
112,117,97,33,37,37,37,49,49,97,52,32,32,49,49,37,37,101,33,37,36,
|
||||
37,97,97,97,97,100,100,100,53,101,101,100,36,101,100,96,97,33,53,101,
|
||||
112,112,112,48,49,49,100,32,49,48,49,53,112,112,112,112,96,112,48,
|
||||
52,52,52,100,100,100,52,116,36,100,100,52,52,52,52,52,48,52,36,37,
|
||||
37,37,49,49,49,101,53,49,49,49,37,37,37,53,97,33,97,100,100,96,97,
|
||||
100,100,100,53,13,102,48,46,57,49,100,96,100,100,97,97,97,97,33,53,
|
||||
53,112,48,113,48,49,49,97,37,49,48,49,113,112,49,97,112,96,37,37,100,
|
||||
52,112,49,49,49,33,116,36,100,100,52,52,52,52,112,117,97,33,37,37,
|
||||
37,49,49,97,116,48,33,49,49,37,37,101,33,37,36,37,97,100,97,97,100,
|
||||
100,100,97,101,96,100,36,101,100,101,97,33,53,101,112,112,112,48,49,
|
||||
49,100,33,53,48,49,53,112,112,112,48,97,112,48,52,52,52,100,100,100,
|
||||
52,116,36,100,100,52,52,52,52,52,48,52,36,37,37,37,49,49,49,37,53,
|
||||
33,49,49,37,37,37,53,97,113,97,100,100,96,97,100,100,100,113,24,102,
|
||||
101,43,57,49,100,96,100,100,97,97,97,97,33,53,53,112,48,113,48,49,
|
||||
49,97,37,49,48,49,113,112,49,97,112,96,37,37,100,52,112,49,49,49,33,
|
||||
116,36,100,100,52,52,52,52,112,117,97,33,37,37,37,49,49,97,52,97,36,
|
||||
49,49,37,37,101,33,37,36,49,97,97,97,97,100,100,100,97,101,96,100,
|
||||
36,101,100,96,97,33,53,101,112,112,112,48,49,49,100,32,49,48,49,53,
|
||||
112,112,112,112,96,112,48,52,52,52,100,100,100,52,116,36,100,100,52,
|
||||
52,52,52,52,48,52,36,37,37,37,49,49,49,101,32,32,49,49,37,37,37,53,
|
||||
97,113,97,100,100,96,97,100,100,100,101,24,102,100,127,108,100,101,
|
||||
96,100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,97,37,49,48,49,
|
||||
113,112,49,97,112,96,37,37,100,52,112,49,49,49,33,116,36,100,100,52,
|
||||
52,52,52,112,117,97,33,37,37,37,49,49,97,116,48,33,49,49,37,37,101,
|
||||
33,37,36,37,97,97,97,97,100,100,100,97,101,96,100,36,101,100,96,97,
|
||||
33,53,101,112,112,112,48,49,49,100,113,53,48,49,53,112,112,112,48,
|
||||
97,112,48,52,52,52,100,100,100,52,116,36,100,100,52,52,52,52,52,48,
|
||||
52,36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,53,97,113,97,100,100,
|
||||
96,100,100,100,100,97,88,51,96,127,108,100,100,100,100,100,97,97,97,
|
||||
97,97,100,36,112,48,113,48,96,100,100,100,100,100,100,36,112,100,117,
|
||||
112,48,49,33,100,52,52,36,48,49,49,49,49,49,49,33,52,52,52,52,100,
|
||||
100,32,37,37,37,33,100,100,100,100,100,100,100,32,37,101,36,37,49,
|
||||
49,96,97,97,97,32,49,49,49,49,49,49,49,48,49,97,97,97,100,36,112,112,
|
||||
112,48,96,100,100,100,100,100,100,36,112,112,112,112,48,49,33,52,52,
|
||||
52,36,48,49,49,49,49,49,49,33,52,52,52,52,52,100,32,37,37,37,33,100,
|
||||
100,100,100,100,100,100,32,37,37,101,100,48,49,48,49,97,97,32,49,49,
|
||||
37,93,51,37,126,108,100,100,100,100,100,97,100,100,100,100,97,100,
|
||||
100,100,36,53,96,100,100,100,100,100,100,36,112,53,49,49,113,32,100,
|
||||
52,36,32,36,48,49,49,49,49,49,49,97,117,117,117,101,52,100,100,112,
|
||||
117,33,112,49,49,49,49,49,49,49,117,37,37,49,49,49,49,49,49,49,96,
|
||||
32,49,49,49,49,49,49,49,96,100,100,97,100,97,36,112,112,53,32,48,49,
|
||||
49,49,49,49,49,113,48,49,49,49,113,48,97,37,32,52,52,100,100,100,100,
|
||||
100,100,100,52,100,100,36,112,32,100,52,52,52,32,117,49,49,49,49,49,
|
||||
49,49,33,52,52,32,117,49,49,116,117,117,100,32,49,49,33,88,51,116,
|
||||
127,108,100,100,100,100,100,100,117,117,117,117,100,36,117,117,53,
|
||||
113,48,49,49,49,49,49,49,33,100,100,96,117,53,49,97,117,101,116,101,
|
||||
100,100,100,100,100,100,100,100,100,100,100,116,101,100,112,49,49,
|
||||
49,49,49,49,49,49,49,49,49,49,37,37,113,116,49,49,116,117,117,100,
|
||||
100,100,100,100,100,100,100,100,100,52,117,100,52,100,100,100,100,
|
||||
32,49,49,49,49,49,49,49,49,49,113,117,117,117,53,49,49,49,33,52,52,
|
||||
100,100,100,100,100,100,100,52,116,117,101,100,100,100,100,100,100,
|
||||
112,49,49,49,49,49,49,49,49,49,49,49,96,100,100,100,100,100,100,117,
|
||||
100,100,100,112,93,51,33,127,108,100,100,100,100,100,100,32,37,37,
|
||||
37,49,49,49,96,117,100,32,49,49,49,49,49,49,49,37,49,49,37,49,49,113,
|
||||
36,96,97,100,97,100,100,100,100,100,100,100,100,100,100,100,100,100,
|
||||
52,36,112,48,113,48,49,49,49,49,49,49,49,117,117,113,116,49,49,116,
|
||||
53,33,33,100,100,100,100,100,100,100,100,52,100,100,52,100,100,100,
|
||||
32,37,37,49,49,49,49,49,49,49,49,49,53,101,112,96,97,100,100,100,52,
|
||||
52,52,97,100,100,100,100,100,100,52,33,116,49,49,49,49,49,49,49,49,
|
||||
49,49,49,49,49,49,49,49,49,49,49,113,48,49,49,49,49,49,116,52,100,
|
||||
100,36,92,51,48,127,108,100,100,100,100,36,53,48,49,49,49,100,116,
|
||||
37,100,52,96,101,100,100,100,100,100,100,116,117,117,37,117,48,49,
|
||||
33,112,36,112,117,49,49,49,49,49,49,49,117,117,117,117,97,101,100,
|
||||
32,116,117,117,117,100,100,100,100,100,100,100,117,32,37,116,32,49,
|
||||
49,96,97,53,117,53,49,49,49,49,49,49,113,117,53,32,117,53,49,97,117,
|
||||
117,117,117,101,100,100,100,100,100,100,116,37,112,112,112,33,49,117,
|
||||
117,33,52,96,48,49,49,49,49,49,49,37,117,117,117,117,49,49,116,117,
|
||||
117,49,117,100,100,100,100,100,100,100,117,117,117,117,117,100,36,
|
||||
117,117,53,32,53,49,49,101,92,59,101,43,179,100,194,206,100,};
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,276 +0,0 @@
|
||||
/*-
|
||||
* Defines for Cronyx-Tau adapter, based on Hitachi HD64570 controller.
|
||||
*
|
||||
* Copyright (C) 1996 Cronyx Engineering.
|
||||
* Author: Serge Vakulenko, <vak@cronyx.ru>
|
||||
*
|
||||
* This software is distributed with NO WARRANTIES, not even the implied
|
||||
* warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* Authors grant any other persons or organisations permission to use
|
||||
* or modify this software as long as this message is kept with the software,
|
||||
* all derivative works or modified versions.
|
||||
*
|
||||
* Cronyx Id: ctaureg.h,v 1.1.2.1 2003/11/12 17:16:10 rik Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/*
|
||||
* Chip register address, B is chip base port, R is chip register number.
|
||||
*/
|
||||
#define R(b,r) ((b) | 0x8000 | (((r)<<6 & 0x3c00) | ((r) & 0xf)))
|
||||
|
||||
/*
|
||||
* Interface board registers, R is register number 0..7.
|
||||
*/
|
||||
#define GR(p,r) ((p) | 0x0010 | (r)<<1)
|
||||
|
||||
/*------------------------------------------------------------
|
||||
* Basic Tau model.
|
||||
*/
|
||||
#define BSR0(p) (p) /* board status register 0, read only */
|
||||
#define BSR1(p) ((p) | 0x2000) /* board status register 1, read only */
|
||||
#define BSR2(p) ((p) | 0x4010) /* board status register 2, read only */
|
||||
#define BSR3(p) ((p) | 0x4000) /* board status register 3, read only */
|
||||
#define BCR0(p) (p) /* board command register 0, write only */
|
||||
#define BCR1(p) ((p) | 0x2000) /* board command register 1, write only */
|
||||
#define BCR2(p) ((p) | 0x4010) /* board command register 2, write only */
|
||||
#define BCR3(p) ((p) | 0x4000) /* board command register 3, write only */
|
||||
#define IACK(p) ((p) | 0x6000) /* interrupt acknowledge register, ro */
|
||||
|
||||
/*
|
||||
* Board status register 0 bits.
|
||||
*/
|
||||
#define BSR0_INTR 0x01 /* interrupt pending flag */
|
||||
#define BSR0_HDINT 0x02 /* HD64570 interrupt pending */
|
||||
#define BSR0_GINT 0x04 /* interface board interrupt pending */
|
||||
#define BSR0_RDYERR 0x10 /* HD64570 reg.i/o error - not ready */
|
||||
|
||||
#define BSR0_TE1 0x02 /* 0 - E1 daughter board installed */
|
||||
#define BSR0_T703 0x04 /* 0 - G.703 daughter board installed */
|
||||
|
||||
/*
|
||||
* Board status register 1 bits.
|
||||
*/
|
||||
#define BSR1_DSR0 0x01 /* DSR from channel 0 */
|
||||
#define BSR1_DSR1 0x02 /* DSR from channel 1 */
|
||||
|
||||
#define BSR1_CH0_CABLE 0x0c /* channel 0 cable type mask */
|
||||
#define BSR1_CH0_V35 0x0c /* channel 0 is V.35 */
|
||||
#define BSR1_CH0_RS232 0x08 /* channel 0 is RS-232 or not connected */
|
||||
#define BSR1_CH0_X21 0x04 /* channel 0 is X.21 */
|
||||
#define BSR1_CH0_RS530 0x00 /* channel 0 is RS-530 */
|
||||
|
||||
#define BSR1_CH1_CABLE 0x30 /* channel 1 cable type mask */
|
||||
#define BSR1_CH1_SHIFT 2
|
||||
#define BSR1_CH1_V35 0x0c /* channel 1 is V.35 */
|
||||
#define BSR1_CH1_RS232 0x08 /* channel 1 is RS-232 or not connected */
|
||||
#define BSR1_CH1_X21 0x04 /* channel 1 is X.21 */
|
||||
#define BSR1_CH1_RS530 0x00 /* channel 1 is RS-530 */
|
||||
|
||||
/*
|
||||
* Board status register 2 bits.
|
||||
*/
|
||||
#define BSR2_GINT0 0x08 /* interface board chan0 interrupt pending */
|
||||
#define BSR2_GINT1 0x40 /* interface board chan1 interrupt pending */
|
||||
#define BSR2_LERR 0x80 /* firmware download error signal */
|
||||
|
||||
/*
|
||||
* Board status register 3 bits.
|
||||
*/
|
||||
#define BSR3_IB 0x08 /* identification bit */
|
||||
#define BSR3_NSTATUS 0x10 /* firmware download status */
|
||||
#define BSR3_CONF_DN 0x20 /* firmware download done */
|
||||
#define BSR3_IB_NEG 0x40 /* negated identification bit */
|
||||
#define BSR3_ZERO 0x80 /* always zero */
|
||||
|
||||
/*
|
||||
* Board control register 0 bits.
|
||||
*/
|
||||
#define BCR0_IRQ_DIS 0x00 /* no interrupt generated */
|
||||
#define BCR0_IRQ_3 0x01 /* select IRQ number 3 */
|
||||
#define BCR0_IRQ_5 0x02 /* select IRQ number 5 */
|
||||
#define BCR0_IRQ_7 0x03 /* select IRQ number 7 */
|
||||
#define BCR0_IRQ_10 0x04 /* select IRQ number 10 */
|
||||
#define BCR0_IRQ_11 0x05 /* select IRQ number 11 */
|
||||
#define BCR0_IRQ_12 0x06 /* select IRQ number 12 */
|
||||
#define BCR0_IRQ_15 0x07 /* select IRQ number 15 */
|
||||
#define BCR0_IRQ_MASK 0x07 /* IRQ mask */
|
||||
|
||||
#define BCR0_HDRUN 0x08 /* inverted board reset flag */
|
||||
|
||||
#define BCR0_DMA_DIS 0x00 /* no interrupt generated */
|
||||
#define BCR0_DMA_5 0x10 /* select DMA channel 5 */
|
||||
#define BCR0_DMA_6 0x20 /* select DMA channel 6 */
|
||||
#define BCR0_DMA_7 0x30 /* select DMA channel 7 */
|
||||
|
||||
#define BCR0_TCK 0x80 /* firmware download TCK signal */
|
||||
|
||||
/*
|
||||
* Board control register 1 bits.
|
||||
*/
|
||||
#define BCR1_DTR0 0x01 /* channel 0 DTR enable */
|
||||
#define BCR1_DTR1 0x02 /* channel 1 DTR enable */
|
||||
|
||||
#define BCR1_TXCOUT0 0x10 /* channel 0 TXCOUT enable */
|
||||
#define BCR1_TXCOUT1 0x20 /* channel 1 TXCOUT enable */
|
||||
|
||||
#define BCR1_TMS 0x08 /* firmware download TMS signal */
|
||||
#define BCR1_TDI 0x80 /* firmware download TDI signal */
|
||||
|
||||
#define BCR1_NCONFIGI 0x08 /* firmware download start */
|
||||
#define BCR1_DCLK 0x40 /* firmware download clock */
|
||||
#define BCR1_1KDAT 0x80 /* firmware download data */
|
||||
|
||||
/*
|
||||
* Board control register 2 bits -- see ctau.h.
|
||||
*/
|
||||
|
||||
#define IMVR(b) R(b,HD_IMVR) /* interrupt modified vector reg. */
|
||||
#define ITCR(b) R(b,HD_ITCR) /* interrupt control register */
|
||||
#define ISR0(b) R(b,HD_ISR0) /* interrupt status register 0, ro */
|
||||
#define ISR1(b) R(b,HD_ISR1) /* interrupt status register 1, ro */
|
||||
#define ISR2(b) R(b,HD_ISR2) /* interrupt status register 2, ro */
|
||||
#define IER0(b) R(b,HD_IER0) /* interrupt enable register 0 */
|
||||
#define IER1(b) R(b,HD_IER1) /* interrupt enable register 1 */
|
||||
#define IER2(b) R(b,HD_IER2) /* interrupt enable register 2 */
|
||||
#define PCR(b) R(b,HD_PCR) /* DMA priority control register */
|
||||
#define DMER(b) R(b,HD_DMER) /* DMA master enable register */
|
||||
#define WCRL(b) R(b,HD_WCRL) /* wait control register L */
|
||||
#define WCRM(b) R(b,HD_WCRM) /* wait control register M */
|
||||
#define WCRH(b) R(b,HD_WCRH) /* wait control register H */
|
||||
|
||||
/*------------------------------------------------------------
|
||||
* Tau/E1 model.
|
||||
*/
|
||||
#define E1CFG(p) GR(p,0) /* control register 0, write only */
|
||||
#define E1SR(p) GR(p,0) /* status register, read only */
|
||||
#define E1CS2(p) GR(p,1) /* chip select 2/IACK, read/write */
|
||||
#define E1SYN(p) GR(p,3) /* sync mode enable, write only */
|
||||
#define E1CS0(p) GR(p,4) /* chip select 0, write only */
|
||||
#define E1CS1(p) GR(p,5) /* chip select 1, write only */
|
||||
#define E1DAT(p) GR(p,7) /* selected chip read/write */
|
||||
|
||||
/*
|
||||
* Tau/E1 CS2/IACK register bits.
|
||||
*/
|
||||
#define E1CS2_IACK 0x08 /* serial controller interrupt acknowledge */
|
||||
#define E1CS2_SCC 0x04 /* serial controller select */
|
||||
#define E1CS2_AB 0x02 /* serial controller A/B signal */
|
||||
#define E1CS2_DC 0x01 /* serial controller D/C signal */
|
||||
|
||||
/*
|
||||
* Tau/E1 control register bits.
|
||||
*/
|
||||
#define E1CFG_II 0x00 /* configuration II */
|
||||
#define E1CFG_K 0x01 /* configuration K */
|
||||
#define E1CFG_HI 0x02 /* configuration HI */
|
||||
#define E1CFG_D 0x03 /* configuration D */
|
||||
|
||||
#define E1CFG_CLK0_INT 0x00 /* channel E0 transmit clock - internal */
|
||||
#define E1CFG_CLK0_RCV 0x04 /* channel E0 transmit clock - RCLK0 */
|
||||
#define E1CFG_CLK0_RCLK1 0x08 /* channel E0 transmit clock - RCLK1 */
|
||||
|
||||
#define E1CFG_CLK1_INT 0x00 /* channel E1 transmit clock - internal */
|
||||
#define E1CFG_CLK1_RCLK0 0x10 /* channel E1 transmit clock - RCLK0 */
|
||||
#define E1CFG_CLK1_RCV 0x20 /* channel E1 transmit clock - RCLK1 */
|
||||
|
||||
#define E1CFG_LED 0x40 /* LED control */
|
||||
#define E1CFG_GRUN 0x80 /* global run flag */
|
||||
|
||||
/*
|
||||
* Tau/E1 sync control register bits.
|
||||
*/
|
||||
#define E1SYN_ENS0 0x01 /* enable channel 0 sync mode */
|
||||
#define E1SYN_ENS1 0x02 /* enable channel 1 sync mode */
|
||||
|
||||
/*
|
||||
* Tau/E1 status register bits.
|
||||
*/
|
||||
#define E1SR_E0_IRQ0 0x01 /* E0 controller interrupt 0 */
|
||||
#define E1SR_E0_IRQ1 0x02 /* E0 controller interrupt 1 */
|
||||
#define E1SR_E1_IRQ0 0x04 /* E1 controller interrupt 0 */
|
||||
#define E1SR_E1_IRQ1 0x08 /* E1 controller interrupt 1 */
|
||||
#define E1SR_SCC_IRQ 0x10 /* serial controller interrupt */
|
||||
#define E1SR_TP0 0x20 /* channel 0 is twisted pair */
|
||||
#define E1SR_TP1 0x40 /* channel 1 is twisted pair */
|
||||
#define E1SR_REV 0x80 /* Tau/E1 revision */
|
||||
|
||||
/*
|
||||
* Tau/E1 serial memory register bits.
|
||||
*/
|
||||
|
||||
/*------------------------------------------------------------
|
||||
* Tau/G.703 model.
|
||||
*/
|
||||
#define GLCR0(p) GR(p,3) /* line control register 0, write only */
|
||||
#define GMD0(p) GR(p,4) /* mode register 0, write only */
|
||||
#define GMD1(p) GR(p,5) /* mode register 1, write only */
|
||||
#define GMD2(p) GR(p,6) /* mode register 2, write only */
|
||||
#define GLCR1(p) GR(p,7) /* line control register 1, write only */
|
||||
#define GERR(p) GR(p,0) /* error register, read/write */
|
||||
#define GLQ(p) GR(p,1) /* line quality register, read only */
|
||||
#define GLDR(p) GR(p,2) /* loop detect request, read only */
|
||||
|
||||
/*
|
||||
* Tau/G.703 mode register 0/1 bits.
|
||||
*/
|
||||
#define GMD_2048 0x00 /* 2048 kbit/sec */
|
||||
#define GMD_1024 0x02 /* 1024 kbit/sec */
|
||||
#define GMD_512 0x03 /* 512 kbit/sec */
|
||||
#define GMD_256 0x04 /* 256 kbit/sec */
|
||||
#define GMD_128 0x05 /* 128 kbit/sec */
|
||||
#define GMD_64 0x06 /* 64 kbit/sec */
|
||||
|
||||
#define GMD_RSYNC 0x08 /* receive synchronization */
|
||||
#define GMD_PCE_PCM2 0x10 /* precoder enable, mode PCM2 */
|
||||
#define GMD_PCE_PCM2D 0x20 /* precoder enable, mode PCM2D */
|
||||
|
||||
#define GMD0_SDI 0x40 /* serial data input */
|
||||
#define GMD0_SCLK 0x80 /* serial data clock */
|
||||
|
||||
#define GMD1_NCS0 0x40 /* chip select 0 inverted */
|
||||
#define GMD1_NCS1 0x80 /* chip select 1 inverted */
|
||||
|
||||
/*
|
||||
* Tau/G.703 mode register 2 bits.
|
||||
*/
|
||||
#define GMD2_SERIAL 0x01 /* channel 1 serial interface V.35/RS-232/etc */
|
||||
#define GMD2_LED 0x02 /* LED control */
|
||||
#define GMD2_RAW0 0x04 /* channel 0 raw mode (byte-sync) */
|
||||
#define GMD2_RAW1 0x08 /* channel 1 raw mode (byte-sync) */
|
||||
|
||||
/*
|
||||
* Tau/G.703 interrupt status register bits.
|
||||
*/
|
||||
#define GERR_BPV0 0x01 /* channel 0 bipolar violation */
|
||||
#define GERR_ERR0 0x02 /* channel 0 test error */
|
||||
#define GERR_BPV1 0x04 /* channel 1 bipolar violation */
|
||||
#define GERR_ERR1 0x08 /* channel 1 test error */
|
||||
|
||||
/*
|
||||
* Tau/G.703 line quality register bits.
|
||||
*/
|
||||
#define GLQ_MASK 0x03 /* channel 0 mask */
|
||||
#define GLQ_SHIFT 2 /* channel 1 shift */
|
||||
|
||||
#define GLQ_DB0 0x00 /* channel 0 level 0.0 dB */
|
||||
#define GLQ_DB95 0x01 /* channel 0 level -9.5 dB */
|
||||
#define GLQ_DB195 0x02 /* channel 0 level -19.5 dB */
|
||||
#define GLQ_DB285 0x03 /* channel 0 level -28.5 dB */
|
||||
|
||||
/*
|
||||
* Tau/G.703 serial data output register bits.
|
||||
*/
|
||||
#define GLDR_C0 0x01 /* chip 0 serial data output */
|
||||
#define GLDR_LREQ0 0x02 /* channel 0 remote loop request */
|
||||
#define GLDR_C1 0x04 /* chip 1 serial data output */
|
||||
#define GLDR_LREQ1 0x08 /* channel 1 remote loop request */
|
||||
|
||||
/*
|
||||
* Tau/G.703 line control register 0/1 bits.
|
||||
*/
|
||||
#define GLCR_RENABLE 0x00 /* normal mode, auto remote loop enabled */
|
||||
#define GLCR_RDISABLE 0x01 /* normal mode, auto remote loop disabled */
|
||||
#define GLCR_RREFUSE 0x02 /* send the remote loop request sequence */
|
||||
#define GLCR_RREQUEST 0x03 /* send the remote loop refuse sequence */
|
||||
1162
sys/dev/ctau/ctddk.c
1162
sys/dev/ctau/ctddk.c
File diff suppressed because it is too large
Load Diff
@ -1,607 +0,0 @@
|
||||
/*-
|
||||
* Defines for Cronyx-Tau adapter driver.
|
||||
*
|
||||
* Copyright (C) 1994-2003 Cronyx Engineering.
|
||||
* Author: Serge Vakulenko, <vak@cronyx.ru>
|
||||
*
|
||||
* This software is distributed with NO WARRANTIES, not even the implied
|
||||
* warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* Authors grant any other persons or organisations permission to use
|
||||
* or modify this software as long as this message is kept with the software,
|
||||
* all derivative works or modified versions.
|
||||
*
|
||||
* Cronyx Id: ctddk.h,v 1.1.2.3 2003/12/11 17:33:44 rik Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#define NBRD 3 /* the maximum number of installed boards */
|
||||
#define NPORT 32 /* the number of i/o ports per board */
|
||||
#define NCHAN 2 /* the number of channels on the board */
|
||||
#define NBUF 4 /* the number of buffers per direction */
|
||||
#define DMABUFSZ 1600 /* buffer size */
|
||||
#define SCCBUFSZ 50
|
||||
|
||||
#ifndef port_t
|
||||
# ifdef _M_ALPHA /* port address on Alpha under */
|
||||
# define port_t unsigned long /* Windows NT is 32 bit long */
|
||||
# else
|
||||
# define port_t unsigned short /* all other architectures */
|
||||
# endif /* have 16-bit port addresses */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* There are tree models of Tau adapters.
|
||||
* Each of two channels of the adapter is assigned a type:
|
||||
*
|
||||
* Channel 0 Channel 1
|
||||
* ------------------------------------------
|
||||
* Tau T_SERIAL T_SERIAL
|
||||
* Tau/E1 T_E1 T_E1_SERIAL
|
||||
* Tau/G703 T_G703 T_G703_SERIAL
|
||||
*
|
||||
* Each channel could work in one of several modes:
|
||||
*
|
||||
* Channel 0 Channel 1
|
||||
* ------------------------------------------
|
||||
* Tau M_ASYNC, M_ASYNC,
|
||||
* M_HDLC M_HDLC
|
||||
* ------------------------------------------
|
||||
* Tau/E1 M_E1, M_E1,
|
||||
* M_E1 & CFG_D, M_E1 & CFG_D,
|
||||
* M_ASYNC,
|
||||
* M_HDLC
|
||||
* ------------------------------------------
|
||||
* Tau/G703 M_G703, M_G703,
|
||||
* M_ASYNC,
|
||||
* M_HDLC
|
||||
* ------------------------------------------
|
||||
*/
|
||||
#define B_TAU 0 /* Tau - basic model */
|
||||
#define B_TAU_E1 1 /* Tau/E1 */
|
||||
#define B_TAU_G703 2 /* Tau/G.703 */
|
||||
#define B_TAU_E1C 3 /* Tau/E1 revision C */
|
||||
#define B_TAU_E1D 4 /* Tau/E1 revision C with phony mode support */
|
||||
#define B_TAU_G703C 5 /* Tau/G.703 revision C */
|
||||
#define B_TAU2 6 /* Tau2 - basic model */
|
||||
#define B_TAU2_E1 7 /* Tau2/E1 */
|
||||
#define B_TAU2_E1D 8 /* Tau2/E1 with phony mode support */
|
||||
#define B_TAU2_G703 9 /* Tau2/G.703 */
|
||||
|
||||
#define T_SERIAL 1
|
||||
#define T_E1 2
|
||||
#define T_G703 4
|
||||
#define T_E1_SERIAL (T_E1 | T_SERIAL)
|
||||
#define T_G703_SERIAL (T_G703 | T_SERIAL)
|
||||
|
||||
#define M_ASYNC 0 /* asynchronous mode */
|
||||
#define M_HDLC 1 /* bit-sync mode (HDLC) */
|
||||
#define M_G703 2
|
||||
#define M_E1 3
|
||||
|
||||
#define CFG_A 0
|
||||
#define CFG_B 1
|
||||
#define CFG_C 2
|
||||
#define CFG_D 3
|
||||
|
||||
/* E1/G.703 interfaces - i0, i1
|
||||
* Digital interface - d0
|
||||
*
|
||||
*
|
||||
* Configuration
|
||||
* ---------------------------------------------------
|
||||
* CFG_A | i0<->ct0 i1<->ct1
|
||||
* ---------------------------------------------------
|
||||
* CFG_B | i0<->ct0 d0<->ct1
|
||||
* | ^
|
||||
* | |
|
||||
* | v
|
||||
* | i1
|
||||
* ---------------------------------------------------
|
||||
* CFG_C | ct0<->i0<->ct1
|
||||
* | ^
|
||||
* | |
|
||||
* | v
|
||||
* | i1
|
||||
* ---------------------------------------------------
|
||||
* CFG_D | i0(e1)<->hdlc<->hdlc<->ct0(e1)
|
||||
* ONLY TAU/E1 | i1(e1)<->hdlc<->hdlc<->ct1(e1)
|
||||
* |
|
||||
*/
|
||||
|
||||
/*
|
||||
* Mode register 0 (MD0) bits.
|
||||
*/
|
||||
#define MD0_STOPB_1 0 /* 1 stop bit */
|
||||
#define MD0_STOPB_15 1 /* 1.5 stop bits */
|
||||
#define MD0_STOPB_2 2 /* 2 stop bits */
|
||||
|
||||
#define MD0_MODE_ASYNC 0 /* asynchronous mode */
|
||||
#define MD0_MODE_EXTSYNC 3 /* external byte-sync mode */
|
||||
#define MD0_MODE_HDLC 4 /* HDLC mode */
|
||||
|
||||
typedef struct {
|
||||
unsigned stopb : 2; /* stop bit length */
|
||||
unsigned : 2;
|
||||
unsigned cts_rts_dcd : 1; /* auto-enable CTS/DCD/RTS */
|
||||
unsigned mode : 3; /* protocol mode */
|
||||
} ct_md0_async_t;
|
||||
|
||||
typedef struct {
|
||||
unsigned crcpre : 1; /* CRC preset 1s / 0s */
|
||||
unsigned ccitt : 1; /* CRC-CCITT / CRC-16 */
|
||||
unsigned crc : 1; /* CRC enable */
|
||||
unsigned : 1;
|
||||
unsigned cts_dcd : 1; /* auto-enable CTS/DCD */
|
||||
unsigned mode : 3; /* protocol mode */
|
||||
} ct_md0_hdlc_t;
|
||||
|
||||
/*
|
||||
* Mode register 1 (MD1) bits.
|
||||
*/
|
||||
#define MD1_PAR_NO 0 /* no parity */
|
||||
#define MD1_PAR_CMD 1 /* parity bit appended by command */
|
||||
#define MD1_PAR_EVEN 2 /* even parity */
|
||||
#define MD1_PAR_ODD 3 /* odd parity */
|
||||
|
||||
#define MD1_CLEN_8 0 /* 8 bits/character */
|
||||
#define MD1_CLEN_7 1 /* 7 bits/character */
|
||||
#define MD1_CLEN_6 2 /* 6 bits/character */
|
||||
#define MD1_CLEN_5 3 /* 5 bits/character */
|
||||
|
||||
#define MD1_CLK_1 0 /* 1/1 clock rate */
|
||||
#define MD1_CLK_16 1 /* 1/16 clock rate */
|
||||
#define MD1_CLK_32 2 /* 1/32 clock rate */
|
||||
#define MD1_CLK_64 3 /* 1/64 clock rate */
|
||||
|
||||
#define MD1_ADDR_NOCHK 0 /* do not check address field */
|
||||
#define MD1_ADDR_SNGLE1 1 /* single address 1 */
|
||||
#define MD1_ADDR_SNGLE2 2 /* single address 2 */
|
||||
#define MD1_ADDR_DUAL 3 /* dual address */
|
||||
|
||||
typedef struct {
|
||||
unsigned parmode : 2; /* parity mode */
|
||||
unsigned rxclen : 2; /* receive character length */
|
||||
unsigned txclen : 2; /* transmit character length */
|
||||
unsigned clk : 2; /* clock rate */
|
||||
} ct_md1_async_t;
|
||||
|
||||
typedef struct {
|
||||
unsigned : 6;
|
||||
unsigned addr : 2; /* address field check */
|
||||
} ct_md1_hdlc_t;
|
||||
|
||||
/*
|
||||
* Mode register 2 (MD2) bits.
|
||||
*/
|
||||
#define MD2_FDX 0 /* full duplex communication */
|
||||
#define MD2_RLOOP 1 /* remote loopback (auto echo) */
|
||||
#define MD2_LLOOP 3 /* local+remote loopback */
|
||||
|
||||
#define MD2_DPLL_CLK_8 0 /* x8 ADPLL clock rate */
|
||||
#define MD2_DPLL_CLK_16 1 /* x16 ADPLL clock rate */
|
||||
#define MD2_DPLL_CLK_32 2 /* x32 ADPLL clock rate */
|
||||
|
||||
#define MD2_ENCOD_NRZ 0 /* NRZ encoding */
|
||||
#define MD2_ENCOD_NRZI 1 /* NRZI encoding */
|
||||
#define MD2_ENCOD_MANCHESTER 4 /* Manchester encoding */
|
||||
#define MD2_ENCOD_FM0 5 /* FM0 encoding */
|
||||
#define MD2_ENCOD_FM1 6 /* FM1 encoding */
|
||||
|
||||
typedef struct {
|
||||
unsigned loop : 2; /* loopback mode */
|
||||
unsigned : 1;
|
||||
unsigned dpll_clk : 2; /* ADPLL clock rate */
|
||||
unsigned encod : 3; /* signal encoding NRZ/NRZI/etc. */
|
||||
} ct_md2_t;
|
||||
|
||||
/*
|
||||
* DMA priority control register (PCR) values.
|
||||
*/
|
||||
#define PCR_PRIO_0_1 0 /* priority c0r > c0t > c1r > c1t */
|
||||
#define PCR_PRIO_1_0 1 /* priority c1r > c1t > c0r > c0t */
|
||||
#define PCR_PRIO_RX_TX 2 /* priority c0r > c1r > c0t > c1t */
|
||||
#define PCR_PRIO_TX_RX 3 /* priority c0t > c1t > c0r > c1r */
|
||||
#define PCR_PRIO_ROTATE 4 /* rotation priority -c0r-c0t-c1r-c1t- */
|
||||
|
||||
typedef struct {
|
||||
unsigned prio : 3; /* priority of channels */
|
||||
unsigned noshare : 1; /* 1 - chan holds the bus until end of data */
|
||||
/* 0 - all channels share the bus hold */
|
||||
unsigned release : 1; /* 1 - release the bus between transfers */
|
||||
/* 0 - hold the bus until all transfers done */
|
||||
} ct_pcr_t;
|
||||
|
||||
typedef struct { /* hdlc channel options */
|
||||
ct_md0_hdlc_t md0; /* mode register 0 */
|
||||
ct_md1_hdlc_t md1; /* mode register 1 */
|
||||
unsigned char ctl; /* control register */
|
||||
unsigned char sa0; /* sync/address register 0 */
|
||||
unsigned char sa1; /* sync/address register 1 */
|
||||
unsigned char rxs; /* receive clock source */
|
||||
unsigned char txs; /* transmit clock source */
|
||||
} ct_opt_hdlc_t;
|
||||
|
||||
typedef struct {
|
||||
ct_md2_t md2; /* mode register 2 */
|
||||
unsigned char dma_rrc; /* DMA mode receive FIFO ready level */
|
||||
unsigned char dma_trc0; /* DMA mode transmit FIFO empty mark */
|
||||
unsigned char dma_trc1; /* DMA mode transmit FIFO full mark */
|
||||
unsigned char pio_rrc; /* port i/o mode receive FIFO ready level */
|
||||
unsigned char pio_trc0; /* port i/o transmit FIFO empty mark */
|
||||
unsigned char pio_trc1; /* port i/o transmit FIFO full mark */
|
||||
} ct_chan_opt_t;
|
||||
|
||||
/*
|
||||
* Option CLK is valid for both E1 and G.703 models.
|
||||
* Options RATE, PCE, TEST are for G.703 only.
|
||||
*/
|
||||
#define GCLK_INT 0 /* internal transmit clock source */
|
||||
#define GCLK_RCV 1 /* transmit clock source = receive */
|
||||
#define GCLK_RCLKO 2 /* tclk = receive clock of another channel */
|
||||
|
||||
#define GTEST_DIS 0 /* test disabled, normal operation */
|
||||
#define GTEST_0 1 /* test "all zeros" */
|
||||
#define GTEST_1 2 /* test "all ones" */
|
||||
#define GTEST_01 3 /* test "0/1" */
|
||||
|
||||
typedef struct { /* E1/G.703 channel options */
|
||||
unsigned char hdb3; /* encoding HDB3/AMI */
|
||||
unsigned char pce; /* precoder enable */
|
||||
unsigned char test; /* test mode 0/1/01/disable */
|
||||
unsigned char crc4; /* E1 CRC4 enable */
|
||||
unsigned char cas; /* E1 signalling mode CAS/CCS */
|
||||
unsigned char higain; /* E1 high gain amplifier (30 dB) */
|
||||
unsigned char phony; /* E1 phony mode */
|
||||
unsigned char pce2; /* old PCM2 precoder compatibility */
|
||||
unsigned long rate; /* data rate 2048/1024/512/256/128/64 kbit/s */
|
||||
unsigned short level; /* G.703 input signal level, -cB */
|
||||
} ct_opt_g703_t;
|
||||
|
||||
typedef struct {
|
||||
unsigned char bcr2; /* board control register 2 */
|
||||
ct_pcr_t pcr; /* DMA priority control register */
|
||||
unsigned char clk0; /* E1/G.703 chan 0 txclk src int/rcv/rclki */
|
||||
unsigned char clk1; /* E1/G.703 chan 1 txclk src int/rcv/rclki */
|
||||
unsigned char cfg; /* E1 configuration II/HI/K */
|
||||
unsigned long s0; /* E1 channel 0 timeslot mask */
|
||||
unsigned long s1; /* E1 channel 1 timeslot mask */
|
||||
unsigned long s2; /* E1 subchannel pass-through timeslot mask */
|
||||
} ct_board_opt_t;
|
||||
|
||||
/*
|
||||
* Board control register 2 bits.
|
||||
*/
|
||||
#define BCR2_INVTXC0 0x10 /* channel 0 invert transmit clock */
|
||||
#define BCR2_INVTXC1 0x20 /* channel 1 invert transmit clock */
|
||||
#define BCR2_INVRXC0 0x40 /* channel 0 invert receive clock */
|
||||
#define BCR2_INVRXC1 0x80 /* channel 1 invert receive clock */
|
||||
|
||||
#define BCR2_BUS_UNLIM 0x01 /* unlimited DMA master burst length */
|
||||
#define BCR2_BUS_RFST 0x02 /* fast read cycle bus timing */
|
||||
#define BCR2_BUS_WFST 0x04 /* fast write cycle bus timing */
|
||||
|
||||
/*
|
||||
* Receive/transmit clock source register (RXS/TXS) bits - from hdc64570.h.
|
||||
*/
|
||||
#define CLK_MASK 0x70 /* RXC/TXC clock input mask */
|
||||
#define CLK_LINE 0x00 /* RXC/TXC line input */
|
||||
#define CLK_INT 0x40 /* internal baud rate generator */
|
||||
|
||||
#define CLK_RXS_LINE_NS 0x20 /* RXC line with noise suppression */
|
||||
#define CLK_RXS_DPLL_INT 0x60 /* ADPLL based on internal BRG */
|
||||
#define CLK_RXS_DPLL_LINE 0x70 /* ADPLL based on RXC line */
|
||||
|
||||
#define CLK_TXS_RECV 0x60 /* receive clock */
|
||||
|
||||
/*
|
||||
* Control register (CTL) bits - from hdc64570.h.
|
||||
*/
|
||||
#define CTL_RTS_INV 0x01 /* RTS control bit (inverted) */
|
||||
#define CTL_SYNCLD 0x04 /* load SYN characters */
|
||||
#define CTL_BRK 0x08 /* async: send break */
|
||||
#define CTL_IDLE_MARK 0 /* HDLC: when idle, transmit mark */
|
||||
#define CTL_IDLE_PTRN 0x10 /* HDLC: when idle, transmit an idle pattern */
|
||||
#define CTL_UDRN_ABORT 0 /* HDLC: on underrun - abort */
|
||||
#define CTL_UDRN_FCS 0x20 /* HDLC: on underrun - send FCS/flag */
|
||||
|
||||
typedef struct {
|
||||
unsigned long bpv; /* bipolar violations */
|
||||
unsigned long fse; /* frame sync errors */
|
||||
unsigned long crce; /* CRC errors */
|
||||
unsigned long rcrce; /* remote CRC errors (E-bit) */
|
||||
unsigned long uas; /* unavailable seconds */
|
||||
unsigned long les; /* line errored seconds */
|
||||
unsigned long es; /* errored seconds */
|
||||
unsigned long bes; /* bursty errored seconds */
|
||||
unsigned long ses; /* severely errored seconds */
|
||||
unsigned long oofs; /* out of frame seconds */
|
||||
unsigned long css; /* controlled slip seconds */
|
||||
unsigned long dm; /* degraded minutes */
|
||||
} ct_gstat_t;
|
||||
|
||||
#define ESTS_NOALARM 0x0001 /* no alarm present */
|
||||
#define ESTS_FARLOF 0x0002 /* receiving far loss of framing */
|
||||
#define ESTS_AIS 0x0008 /* receiving all ones */
|
||||
#define ESTS_LOF 0x0020 /* loss of framing */
|
||||
#define ESTS_LOS 0x0040 /* loss of signal */
|
||||
#define ESTS_AIS16 0x0100 /* receiving all ones in timeslot 16 */
|
||||
#define ESTS_FARLOMF 0x0200 /* receiving alarm in timeslot 16 */
|
||||
#define ESTS_LOMF 0x0400 /* loss of multiframe sync */
|
||||
#define ESTS_TSTREQ 0x0800 /* test code detected */
|
||||
#define ESTS_TSTERR 0x1000 /* test error */
|
||||
|
||||
typedef struct {
|
||||
unsigned char data[10];
|
||||
} ct_desc_t;
|
||||
|
||||
typedef struct {
|
||||
unsigned char tbuffer [NBUF] [DMABUFSZ]; /* transmit buffers */
|
||||
unsigned char rbuffer [NBUF] [DMABUFSZ]; /* receive buffers */
|
||||
ct_desc_t descbuf [4*NBUF]; /* descriptors */
|
||||
/* double size for alignment */
|
||||
} ct_buf_t;
|
||||
|
||||
#define B_NEXT(b) (*(unsigned short*)(b).data) /* next descriptor ptr */
|
||||
#define B_PTR(b) (*(unsigned long*) ((b).data+2)) /* ptr to data buffer */
|
||||
#define B_LEN(b) (*(unsigned short*)((b).data+6)) /* data buffer length */
|
||||
#define B_STATUS(b) (*(unsigned short*)((b).data+8)) /* buf status, see FST */
|
||||
|
||||
typedef struct {
|
||||
port_t DAR, DARB, SAR, SARB, CDA, EDA, BFL, BCR, DSR,
|
||||
DMR, FCT, DIR, DCR, TCNT, TCONR, TCSR, TEPR;
|
||||
} ct_dmareg_t;
|
||||
|
||||
#ifdef NDIS_MINIPORT_DRIVER
|
||||
typedef struct _ct_queue_t { /* packet queue */
|
||||
PNDIS_WAN_PACKET head; /* first packet in queue */
|
||||
PNDIS_WAN_PACKET tail; /* last packet in queue */
|
||||
} ct_queue_t;
|
||||
#endif
|
||||
|
||||
typedef struct _ct_chan_t {
|
||||
port_t MD0, MD1, MD2, CTL, RXS, TXS, TMC, CMD, ST0,
|
||||
ST1, ST2, ST3, FST, IE0, IE1, IE2, FIE, SA0,
|
||||
SA1, IDL, TRB, RRC, TRC0, TRC1, CST;
|
||||
ct_dmareg_t RX; /* RX DMA/timer registers */
|
||||
ct_dmareg_t TX; /* TX DMA/timer registers */
|
||||
|
||||
unsigned char num; /* channel number, 0..1 */
|
||||
struct _ct_board_t *board; /* board pointer */
|
||||
unsigned long baud; /* data rate */
|
||||
unsigned char type; /* channel type */
|
||||
unsigned char mode; /* channel mode */
|
||||
ct_chan_opt_t opt; /* common channel options */
|
||||
ct_opt_hdlc_t hopt; /* hdlc mode options */
|
||||
ct_opt_g703_t gopt; /* E1/G.703 options */
|
||||
unsigned char dtr; /* DTR signal value */
|
||||
unsigned char rts; /* RTS signal value */
|
||||
unsigned char lx; /* LXT input bit settings */
|
||||
|
||||
unsigned char *tbuf [NBUF]; /* transmit buffer */
|
||||
ct_desc_t *tdesc; /* transmit buffer descriptors */
|
||||
unsigned long tphys [NBUF]; /* transmit buffer phys address */
|
||||
unsigned long tdphys [NBUF]; /* transmit descr phys addresses */
|
||||
int tn; /* first active transmit buffer */
|
||||
int te; /* first active transmit buffer */
|
||||
|
||||
unsigned char *rbuf [NBUF]; /* receive buffers */
|
||||
ct_desc_t *rdesc; /* receive buffer descriptors */
|
||||
unsigned long rphys [NBUF]; /* receive buffer phys address */
|
||||
unsigned long rdphys [NBUF]; /* receive descr phys addresses */
|
||||
int rn; /* first active receive buffer */
|
||||
|
||||
unsigned long rintr; /* receive interrupts */
|
||||
unsigned long tintr; /* transmit interrupts */
|
||||
unsigned long mintr; /* modem interrupts */
|
||||
unsigned long ibytes; /* input bytes */
|
||||
unsigned long ipkts; /* input packets */
|
||||
unsigned long ierrs; /* input errors */
|
||||
unsigned long obytes; /* output bytes */
|
||||
unsigned long opkts; /* output packets */
|
||||
unsigned long oerrs; /* output errors */
|
||||
|
||||
unsigned short status; /* line status bit mask */
|
||||
unsigned long totsec; /* total seconds elapsed */
|
||||
unsigned long cursec; /* total seconds elapsed */
|
||||
unsigned long degsec; /* degraded seconds */
|
||||
unsigned long degerr; /* errors during degraded seconds */
|
||||
ct_gstat_t currnt; /* current 15-min interval data */
|
||||
ct_gstat_t total; /* total statistics data */
|
||||
ct_gstat_t interval [48]; /* 12 hour period data */
|
||||
|
||||
void *attach [NBUF]; /* system dependent data per buffer */
|
||||
void *sys; /* system dependent data per channel */
|
||||
int debug;
|
||||
int debug_shadow;
|
||||
|
||||
int e1_first_int;
|
||||
unsigned char *sccrx, *scctx; /* pointers to SCC rx and tx buffers */
|
||||
int sccrx_empty, scctx_empty; /* flags : set when buffer is empty */
|
||||
int sccrx_b, scctx_b; /* first byte in queue */
|
||||
int sccrx_e, scctx_e; /* first free byte in queue */
|
||||
|
||||
/* pointers to callback functions */
|
||||
void (*call_on_tx) (struct _ct_chan_t*, void*, int);
|
||||
void (*call_on_rx) (struct _ct_chan_t*, char*, int);
|
||||
void (*call_on_msig) (struct _ct_chan_t*);
|
||||
void (*call_on_scc) (struct _ct_chan_t*);
|
||||
void (*call_on_err) (struct _ct_chan_t*, int);
|
||||
|
||||
#ifdef NDIS_MINIPORT_DRIVER /* NDIS 3 - WinNT/Win95 */
|
||||
HTAPI_LINE htline; /* TAPI line descriptor */
|
||||
HTAPI_CALL htcall; /* TAPI call descriptor */
|
||||
NDIS_HANDLE connect; /* WAN connection context */
|
||||
ct_queue_t sendq; /* packets to transmit queue */
|
||||
ct_queue_t busyq; /* transmit busy queue */
|
||||
UINT state; /* line state mask */
|
||||
int timo; /* state timeout counter */
|
||||
#endif
|
||||
} ct_chan_t;
|
||||
|
||||
typedef struct _ct_board_t {
|
||||
port_t port; /* base board port, 200..3e0 */
|
||||
unsigned short num; /* board number, 0..2 */
|
||||
unsigned char irq; /* intterupt request {3 5 7 10 11 12 15} */
|
||||
unsigned char dma; /* DMA request {5 6 7} */
|
||||
unsigned long osc; /* oscillator frequency: 10MHz or 8.192 */
|
||||
unsigned char type; /* board type Tau/TauE1/TauG703 */
|
||||
char name[16]; /* board version name */
|
||||
unsigned char bcr0; /* BCR0 image */
|
||||
unsigned char bcr1; /* BCR1 image */
|
||||
unsigned char bcr2; /* BCR2 image */
|
||||
unsigned char gmd0; /* G.703 MD0 register image */
|
||||
unsigned char gmd1; /* G.703 MD1 register image */
|
||||
unsigned char gmd2; /* G.703 MD2 register image */
|
||||
unsigned char e1cfg; /* E1 CFG register image */
|
||||
unsigned char e1syn; /* E1 SYN register image */
|
||||
ct_board_opt_t opt; /* board options */
|
||||
ct_chan_t chan[NCHAN]; /* channel structures */
|
||||
#ifdef NDIS_MINIPORT_DRIVER /* NDIS 3 - WinNT/Win95 */
|
||||
PVOID ioaddr; /* mapped i/o port address */
|
||||
NDIS_HANDLE mh; /* miniport adapter handler */
|
||||
NDIS_MINIPORT_INTERRUPT irqh; /* interrupt handler */
|
||||
NDIS_HANDLE dmah; /* dma channel handler */
|
||||
ULONG bufsz; /* size of shared memory buffer */
|
||||
PVOID buf; /* shared memory for adapter */
|
||||
NDIS_PHYSICAL_ADDRESS bphys; /* shared memory phys address */
|
||||
NDIS_SPIN_LOCK lock; /* lock descriptor */
|
||||
ULONG debug; /* debug flags */
|
||||
ULONG idbase; /* TAPI device identifier base number */
|
||||
ULONG anum; /* adapter number, from inf setup script */
|
||||
NDIS_MINIPORT_TIMER timer; /* periodic timer structure */
|
||||
#endif
|
||||
} ct_board_t;
|
||||
|
||||
extern long ct_baud;
|
||||
extern unsigned char ct_chan_mode;
|
||||
|
||||
extern ct_board_opt_t ct_board_opt_dflt; /* default board options */
|
||||
extern ct_chan_opt_t ct_chan_opt_dflt; /* default channel options */
|
||||
extern ct_opt_hdlc_t ct_opt_hdlc_dflt; /* default hdlc mode options */
|
||||
extern ct_opt_g703_t ct_opt_g703_dflt; /* default E1/G.703 options */
|
||||
|
||||
struct _cr_dat_tst;
|
||||
int ct_probe_board (port_t port, int irq, int dma);
|
||||
void ct_init (ct_board_t *b, int num, port_t port, int irq, int dma,
|
||||
const unsigned char *firmware, long bits,
|
||||
const struct _cr_dat_tst *tst, const unsigned char *firmware2);
|
||||
void ct_init_board (ct_board_t *b, int num, port_t port, int irq, int dma,
|
||||
int type, long osc);
|
||||
int ct_download (port_t port, const unsigned char *firmware, long bits,
|
||||
const struct _cr_dat_tst *tst);
|
||||
int ct_download2 (port_t port, const unsigned char *firmware);
|
||||
int ct_setup_board (ct_board_t *b, const unsigned char *firmware,
|
||||
long bits, const struct _cr_dat_tst *tst);
|
||||
void ct_setup_e1 (ct_board_t *b);
|
||||
void ct_setup_g703 (ct_board_t *b);
|
||||
void ct_setup_chan (ct_chan_t *c);
|
||||
void ct_update_chan (ct_chan_t *c);
|
||||
void ct_start_receiver (ct_chan_t *c, int dma, unsigned long buf1,
|
||||
unsigned len, unsigned long buf, unsigned long lim);
|
||||
void ct_start_transmitter (ct_chan_t *c, int dma, unsigned long buf1,
|
||||
unsigned len, unsigned long buf, unsigned long lim);
|
||||
void ct_set_dtr (ct_chan_t *c, int on);
|
||||
void ct_set_rts (ct_chan_t *c, int on);
|
||||
void ct_set_brk (ct_chan_t *c, int on);
|
||||
void ct_led (ct_board_t *b, int on);
|
||||
void ct_cmd (port_t base, int cmd);
|
||||
void ct_disable_dma (ct_board_t *b);
|
||||
void ct_reinit_board (ct_board_t *b);
|
||||
void ct_reinit_chan (ct_chan_t *c);
|
||||
int ct_get_dsr (ct_chan_t *c);
|
||||
int ct_get_cd (ct_chan_t *c);
|
||||
int ct_get_cts (ct_chan_t *c);
|
||||
int ct_get_lq (ct_chan_t *c);
|
||||
void ct_compute_clock (long hz, long baud, int *txbr, int *tmc);
|
||||
unsigned char cte_in (port_t base, unsigned char reg);
|
||||
void cte_out (port_t base, unsigned char reg, unsigned char val);
|
||||
unsigned char cte_ins (port_t base, unsigned char reg,
|
||||
unsigned char mask);
|
||||
unsigned char cte_in2 (port_t base, unsigned char reg);
|
||||
void cte_out2 (port_t base, unsigned char reg, unsigned char val);
|
||||
void ctg_outx (ct_chan_t *c, unsigned char reg, unsigned char val);
|
||||
unsigned char ctg_inx (ct_chan_t *c, unsigned char reg);
|
||||
unsigned char cte_in2d (ct_chan_t *c);
|
||||
void cte_out2d (ct_chan_t *c, unsigned char val);
|
||||
void cte_out2c (ct_chan_t *c, unsigned char val);
|
||||
|
||||
/* functions dealing with interrupt vector in DOS */
|
||||
#if defined (MSDOS) || defined (__MSDOS__)
|
||||
int ddk_int_alloc (int irq, void (*func)(), void *arg);
|
||||
int ddk_int_restore (int irq);
|
||||
#endif
|
||||
|
||||
int ct_probe_irq (ct_board_t *b, int irq);
|
||||
void ct_int_handler (ct_board_t *b);
|
||||
void ct_g703_timer (ct_chan_t *c);
|
||||
|
||||
/* DDK errors */
|
||||
#define CT_FRAME 1
|
||||
#define CT_CRC 2
|
||||
#define CT_OVERRUN 3
|
||||
#define CT_OVERFLOW 4
|
||||
#define CT_UNDERRUN 5
|
||||
#define CT_SCC_OVERRUN 6
|
||||
#define CT_SCC_FRAME 7
|
||||
#define CT_SCC_OVERFLOW 8
|
||||
|
||||
int ct_open_board (ct_board_t *b, int num, port_t port, int irq, int dma);
|
||||
void ct_close_board (ct_board_t *b);
|
||||
int ct_find (port_t *board_ports);
|
||||
|
||||
int ct_set_config (ct_board_t *b, int cfg);
|
||||
int ct_set_clk (ct_chan_t *c, int clk);
|
||||
int ct_set_ts (ct_chan_t *c, unsigned long ts);
|
||||
int ct_set_subchan (ct_board_t *b, unsigned long ts);
|
||||
int ct_set_higain (ct_chan_t *c, int on);
|
||||
void ct_set_phony (ct_chan_t *c, int on);
|
||||
|
||||
#define ct_get_config(b) ((b)->opt.cfg)
|
||||
#define ct_get_subchan(b) ((b)->opt.s2)
|
||||
#define ct_get_higain(c) ((c)->gopt.higain)
|
||||
#define ct_get_phony(c) ((c)->gopt.phony)
|
||||
int ct_get_clk (ct_chan_t *c);
|
||||
unsigned long ct_get_ts (ct_chan_t *c);
|
||||
|
||||
void ct_start_chan (ct_chan_t *c, ct_buf_t *cb, unsigned long phys);
|
||||
void ct_enable_receive (ct_chan_t *c, int on);
|
||||
void ct_enable_transmit (ct_chan_t *c, int on);
|
||||
int ct_receive_enabled (ct_chan_t *c);
|
||||
int ct_transmit_enabled (ct_chan_t *c);
|
||||
|
||||
void ct_set_baud (ct_chan_t *c, unsigned long baud);
|
||||
unsigned long ct_get_baud (ct_chan_t *c);
|
||||
|
||||
void ct_set_dpll (ct_chan_t *c, int on);
|
||||
int ct_get_dpll (ct_chan_t *c);
|
||||
|
||||
void ct_set_nrzi (ct_chan_t *c, int on);
|
||||
int ct_get_nrzi (ct_chan_t *c);
|
||||
|
||||
void ct_set_loop (ct_chan_t *c, int on);
|
||||
int ct_get_loop (ct_chan_t *c);
|
||||
|
||||
void ct_set_invtxc (ct_chan_t *c, int on);
|
||||
int ct_get_invtxc (ct_chan_t *c);
|
||||
void ct_set_invrxc (ct_chan_t *c, int on);
|
||||
int ct_get_invrxc (ct_chan_t *c);
|
||||
|
||||
int ct_buf_free (ct_chan_t *c);
|
||||
int ct_send_packet (ct_chan_t *c, unsigned char *data, int len,
|
||||
void *attachment);
|
||||
|
||||
void ct_start_scc (ct_chan_t *c, char *rxbuf, char * txbuf);
|
||||
int sccrx_check (ct_chan_t *c);
|
||||
int scc_read (ct_chan_t *c, unsigned char *d, int len);
|
||||
int scc_write (ct_chan_t *c, unsigned char *d, int len);
|
||||
int scc_read_byte (ct_chan_t *c);
|
||||
int scc_write_byte (ct_chan_t *c, unsigned char b);
|
||||
|
||||
void ct_register_transmit (ct_chan_t *c,
|
||||
void (*func) (ct_chan_t*, void *attachment, int len));
|
||||
void ct_register_receive (ct_chan_t *c,
|
||||
void (*func) (ct_chan_t*, char *data, int len));
|
||||
void ct_register_error (ct_chan_t *c,
|
||||
void (*func) (ct_chan_t *c, int data));
|
||||
void ct_register_modem (ct_chan_t *c, void (*func) (ct_chan_t *c));
|
||||
void ct_register_scc (ct_chan_t *c, void (*func) (ct_chan_t *c));
|
||||
@ -1,290 +0,0 @@
|
||||
/*-
|
||||
* Dallas DS2153, DS21x54 single-chip E1 tranceiver registers.
|
||||
*
|
||||
* Copyright (C) 1996 Cronyx Engineering.
|
||||
* Author: Serge Vakulenko, <vak@cronyx.ru>
|
||||
*
|
||||
* This software is distributed with NO WARRANTIES, not even the implied
|
||||
* warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* Authors grant any other persons or organisations permission to use
|
||||
* or modify this software as long as this message is kept with the software,
|
||||
* all derivative works or modified versions.
|
||||
*
|
||||
* Cronyx Id: ds2153.h,v 1.2.4.1 2003/11/12 17:22:33 rik Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/*
|
||||
* Control and test registers
|
||||
*/
|
||||
#define DS_RCR1 0x10 /* rw - receive control 1 */
|
||||
#define DS_RCR2 0x11 /* rw - receive control 2 */
|
||||
#define DS_TCR1 0x12 /* rw - transmit control 1 */
|
||||
#define DS_TCR2 0x13 /* rw - transmit control 2 */
|
||||
#define DS_CCR1 0x14 /* rw - common control 1 */
|
||||
#define DS_CCR2 0x1a /* rw - common control 2 */
|
||||
#define DS_CCR3 0x1b /* rw - common control 3 */
|
||||
#define DS_LICR 0x18 /* rw - line interface control */
|
||||
#define DS_IMR1 0x16 /* rw - interrupt mask 1 */
|
||||
#define DS_IMR2 0x17 /* rw - interrupt mask 2 */
|
||||
#define DS_TEST1 0x15 /* rw - test 1 */
|
||||
#define DS_TEST2 0x19 /* rw - test 2 */
|
||||
|
||||
/*
|
||||
* Status and information registers
|
||||
*/
|
||||
#define DS_RIR 0x08 /* r - receive information */
|
||||
#define DS_SSR 0x1e /* r - synchronizer status */
|
||||
#define DS_SR1 0x06 /* r - status 1 */
|
||||
#define DS_SR2 0x07 /* r - status 2 */
|
||||
|
||||
/*
|
||||
* Error count registers
|
||||
*/
|
||||
#define DS_VCR1 0x00 /* r - BPV or code violation count 1 */
|
||||
#define DS_VCR2 0x01 /* r - BPV or code violation count 2 */
|
||||
#define DS_CRCCR1 0x02 /* r - CRC4 error count 1 */
|
||||
#define DS_CRCCR2 0x03 /* r - CRC4 error count 2 */
|
||||
#define DS_EBCR1 0x04 /* r - E-bit count 1 */
|
||||
#define DS_EBCR2 0x05 /* r - E-bit count 2 */
|
||||
#define DS_FASCR1 0x02 /* r - FAS error count 1 */
|
||||
#define DS_FASCR2 0x04 /* r - FAS error count 2 */
|
||||
|
||||
/*
|
||||
* Signaling registers
|
||||
*/
|
||||
#define DS_RS 0x30 /* r - receive signaling 1..16 */
|
||||
#define DS_TS 0x40 /* rw - transmit signaling 1..16 */
|
||||
|
||||
/*
|
||||
* Transmit idle registers
|
||||
*/
|
||||
#define DS_TIR 0x26 /* rw - transmit idle 1..4 */
|
||||
#define DS_TIDR 0x2a /* rw - transmit idle definition */
|
||||
|
||||
/*
|
||||
* Clock blocking registers
|
||||
*/
|
||||
#define DS_RCBR 0x2b /* rw - receive channel blocking 1..4 */
|
||||
#define DS_TCBR 0x22 /* rw - transmit channel blocking 1..4 */
|
||||
|
||||
/*
|
||||
* Slot 0 registers
|
||||
*/
|
||||
#define DS_RAF 0x2f /* r - receive align frame */
|
||||
#define DS_RNAF 0x1f /* r - receive non-align frame */
|
||||
#define DS_TAF 0x20 /* rw - transmit align frame */
|
||||
#define DS_TNAF 0x21 /* rw - transmit non-align frame */
|
||||
|
||||
/*----------------------------------------------
|
||||
* Receive control register 1
|
||||
*/
|
||||
#define RCR1_RSO 0x00 /* RSYNC outputs frame boundaries */
|
||||
#define RCR1_RSI 0x20 /* RSYNC is input (elastic store) */
|
||||
#define RCR1_RSO_CAS 0x40 /* RSYNC outputs CAS multiframe boundaries */
|
||||
#define RCR1_RSO_CRC4 0xc0 /* RSYNC outputs CRC4 multiframe boundaries */
|
||||
|
||||
#define RCR1_FRC 0x04 /* frame resync criteria */
|
||||
#define RCR1_SYNCD 0x02 /* auto resync disable */
|
||||
#define RCR1_RESYNC 0x01 /* force resync */
|
||||
|
||||
/*
|
||||
* Receive control register 2
|
||||
*/
|
||||
#define RCR2_SA_8 0x80 /* output Sa8 bit at RLINK pin */
|
||||
#define RCR2_SA_7 0x40 /* output Sa7 bit at RLINK pin */
|
||||
#define RCR2_SA_6 0x20 /* output Sa6 bit at RLINK pin */
|
||||
#define RCR2_SA_5 0x10 /* output Sa5 bit at RLINK pin */
|
||||
#define RCR2_SA_4 0x08 /* output Sa4 bit at RLINK pin */
|
||||
#define RCR2_RSCLKM 0x04 /* receive side SYSCLK mode 2048 */
|
||||
#define RCR2_RESE 0x02 /* receive side elastic store enable */
|
||||
|
||||
/*
|
||||
* Transmit control register 1
|
||||
*/
|
||||
#define TCR1_TFPT 0x40 /* source timeslot 0 from TSER pin */
|
||||
#define TCR1_T16S 0x20 /* source timeslot 16 from TS1..TS16 regs */
|
||||
#define TCR1_TUA1 0x10 /* transmit unframed all ones */
|
||||
#define TCR1_TSIS 0x08 /* source Si bits from TAF/TNAF registers */
|
||||
#define TCR1_TSA1 0x04 /* transmit timeslot 16 all ones */
|
||||
|
||||
#define TCR1_TSI 0x00 /* TSYNC is input */
|
||||
#define TCR1_TSO 0x01 /* TSYNC outputs frame boundaries */
|
||||
#define TCR1_TSO_MF 0x03 /* TSYNC outputs CAS/CRC4 m/f boundaries */
|
||||
|
||||
/*
|
||||
* Transmit control register 2
|
||||
*/
|
||||
#define TCR2_SA_8 0x80 /* source Sa8 bit from TLINK pin */
|
||||
#define TCR2_SA_7 0x40 /* source Sa7 bit from TLINK pin */
|
||||
#define TCR2_SA_6 0x20 /* source Sa6 bit from TLINK pin */
|
||||
#define TCR2_SA_5 0x10 /* source Sa5 bit from TLINK pin */
|
||||
#define TCR2_SA_4 0x08 /* source Sa4 bit from TLINK pin */
|
||||
#define TCR2_AEBE 0x02 /* automatic E-bit enable */
|
||||
#define TCR2_P16F 0x01 /* pin 16 is Loss of Transmit Clock */
|
||||
|
||||
/*
|
||||
* Common control register 1
|
||||
*/
|
||||
#define CCR1_FLOOP 0x80 /* enable framer loopback */
|
||||
#define CCR1_THDB3 0x40 /* enable transmit HDB3 */
|
||||
#define CCR1_TG802 0x20 /* enable transmit G.802 */
|
||||
#define CCR1_TCRC4 0x10 /* enable transmit CRC4 */
|
||||
#define CCR1_CCS 0x08 /* common channel signaling mode */
|
||||
#define CCR1_RHDB3 0x04 /* enable receive HDB3 */
|
||||
#define CCR1_RG802 0x02 /* enable receive G.802 */
|
||||
#define CCR1_RCRC4 0x01 /* enable receive CRC4 */
|
||||
|
||||
/*
|
||||
* Common control register 2
|
||||
*/
|
||||
#define CCR2_EC625 0x80 /* update error counters every 62.5 ms */
|
||||
#define CCR2_CNTCV 0x40 /* count code violations */
|
||||
#define CCR2_AUTOAIS 0x20 /* automatic AIS generation */
|
||||
#define CCR2_AUTORA 0x10 /* automatic remote alarm generation */
|
||||
#define CCR2_LOFA1 0x08 /* force RSER to 1 under loss of frame align */
|
||||
#define CCR2_TRCLK 0x04 /* switch transmitter to RCLK if TCLK stops */
|
||||
#define CCR2_RLOOP 0x02 /* enable remote loopback */
|
||||
#define CCR2_LLOOP 0x01 /* enable local loopback */
|
||||
|
||||
/*
|
||||
* Common control register 3
|
||||
*/
|
||||
#define CCR3_TESE 0x80 /* enable transmit elastic store */
|
||||
#define CCR3_TCBFS 0x40 /* TCBRs define signaling bits to insert */
|
||||
#define CCR3_TIRSER 0x20 /* TIRs define data channels from RSER pin */
|
||||
#define CCR3_ESRESET 0x10 /* elastic store reset */
|
||||
#define CCR3_LIRESET 0x08 /* line interface reset */
|
||||
#define CCR3_THSE 0x04 /* insert signaling from TSIG into TSER */
|
||||
#define CCR3_TSCLKM 0x02 /* transmit backplane clock 2048 */
|
||||
|
||||
/*
|
||||
* Line interface control register
|
||||
*/
|
||||
#define LICR_DB21 0x80 /* return loss 21 dB */
|
||||
|
||||
#define LICR_LB75 0x00 /* 75 Ohm normal */
|
||||
#define LICR_LB120 0x20 /* 120 Ohm normal */
|
||||
#define LICR_LB75P 0x40 /* 75 Ohm protected */
|
||||
#define LICR_LB120P 0x60 /* 120 Ohm protected */
|
||||
|
||||
#define LICR_HIGAIN 0x10 /* receive gain 30 dB */
|
||||
#define LICR_JA_TX 0x08 /* transmit side jitter attenuator select */
|
||||
#define LICR_JA_LOW 0x04 /* low jitter attenuator depth (32 bits) */
|
||||
#define LICR_JA_DISABLE 0x02 /* disable jitter attenuator */
|
||||
#define LICR_POWERDOWN 0x01 /* transmit power down */
|
||||
|
||||
/*----------------------------------------------
|
||||
* Receive information register
|
||||
*/
|
||||
#define RIR_TES_FULL 0x80 /* transmit elastic store full */
|
||||
#define RIR_TES_EMPTY 0x40 /* transmit elastic store empty */
|
||||
#define RIR_JALT 0x20 /* jitter attenuation limit trip */
|
||||
#define RIR_ES_FULL 0x10 /* elastic store full */
|
||||
#define RIR_ES_EMPTY 0x08 /* elastic store empty */
|
||||
#define RIR_RESYNC_CRC 0x04 /* CRC4 resync (915/1000 errors) */
|
||||
#define RIR_RESYNC 0x02 /* frame resync (three consec errors) */
|
||||
#define RIR_RESYNC_CAS 0x01 /* CAS resync (two consec errors) */
|
||||
|
||||
/*
|
||||
* Synchronizer status register
|
||||
*/
|
||||
#define SSR_CSC(v) (((v) >> 2) & 0x3c | ((v) >> 3) & 1)
|
||||
/* CRC4 sync counter (6 bits, bit 1 n/a) */
|
||||
#define SSR_SYNC 0x04 /* frame alignment sync active */
|
||||
#define SSR_SYNC_CAS 0x02 /* CAS multiframe sync active */
|
||||
#define SSR_SYNC_CRC4 0x01 /* CRC4 multiframe sync active */
|
||||
|
||||
/*
|
||||
* Status register 1
|
||||
*/
|
||||
#define SR1_RSA1 0x80 /* receive signaling all ones */
|
||||
#define SR1_RDMA 0x40 /* receive distant multiframe alarm */
|
||||
#define SR1_RSA0 0x20 /* receive signaling all zeros */
|
||||
#define SR1_RSLIP 0x10 /* receive elastic store slip event */
|
||||
#define SR1_RUA1 0x08 /* receive unframed all ones */
|
||||
#define SR1_RRA 0x04 /* receive remote alarm */
|
||||
#define SR1_RCL 0x02 /* receive carrier loss */
|
||||
#define SR1_RLOS 0x01 /* receive loss of sync */
|
||||
|
||||
/*
|
||||
* Status register 2
|
||||
*/
|
||||
#define SR2_RMF 0x80 /* receive CAS multiframe (every 2 ms) */
|
||||
#define SR2_RAF 0x40 /* receive align frame (every 250 us) */
|
||||
#define SR2_TMF 0x20 /* transmit multiframe (every 2 ms) */
|
||||
#define SR2_SEC 0x10 /* one second timer (or 62.5 ms) */
|
||||
#define SR2_TAF 0x08 /* transmit align frame (every 250 us) */
|
||||
#define SR2_LOTC 0x04 /* loss of transmit clock */
|
||||
#define SR2_RCMF 0x02 /* receive CRC4 multiframe (every 2 ms) */
|
||||
#define SR2_TSLIP 0x01 /* transmit elastic store slip event */
|
||||
|
||||
/*
|
||||
* Error count registers
|
||||
*/
|
||||
#define VCR(h,l) (((short) (h) << 8) | (l)) /* 16-bit code violation */
|
||||
#define CRCCR(h,l) (((short) (h) << 8 & 0x300) | (l)) /* 10-bit CRC4 error count */
|
||||
#define EBCR(h,l) (((short) (h) << 8 & 0x300) | (l)) /* 10-bit E-bit count */
|
||||
#define FASCR(h,l) (((short) (h) << 4 & 0xfc0) | (l) >> 2) /* 12-bit FAS error count */
|
||||
|
||||
#define FASCRH(h) ((h) << 4) /* 12-bit FAS error count */
|
||||
#define FASCRL(l) ((l) >> 2) /* 12-bit FAS error count */
|
||||
|
||||
/*
|
||||
* DS21x54 additional registers
|
||||
*/
|
||||
#define DS_IDR 0x0f /* r - device id */
|
||||
#define DS_TSACR 0x1c /* rw - transmit Sa bit control */
|
||||
#define DS_CCR6 0x1d /* rw - common control 6 */
|
||||
|
||||
#define DS_TSIAF 0x50 /* rw - transmit Si bits align frame */
|
||||
#define DS_TSINAF 0x51 /* rw - transmit Si bits non-align frame */
|
||||
#define DS_TRA 0x52 /* rw - transmit remote alarm bits */
|
||||
#define DS_TSA4 0x53 /* rw - transmit Sa4 bits */
|
||||
#define DS_TSA5 0x54 /* rw - transmit Sa5 bits */
|
||||
#define DS_TSA6 0x55 /* rw - transmit Sa6 bits */
|
||||
#define DS_TSA7 0x56 /* rw - transmit Sa7 bits */
|
||||
#define DS_TSA8 0x57 /* rw - transmit Sa8 bits */
|
||||
#define DS_RSIAF 0x58 /* r - receive Si bits align frame */
|
||||
#define DS_RSINAF 0x59 /* r - receive Si bits non-align frame */
|
||||
#define DS_RRA 0x5a /* r - receive remote alarm bits */
|
||||
#define DS_RSA4 0x5b /* r - receive Sa4 bits */
|
||||
#define DS_RSA5 0x5c /* r - receive Sa5 bits */
|
||||
#define DS_RSA6 0x5d /* r - receive Sa6 bits */
|
||||
#define DS_RSA7 0x5e /* r - receive Sa7 bits */
|
||||
#define DS_RSA8 0x5f /* r - receive Sa8 bits */
|
||||
|
||||
#define DS_TCC1 0xa0 /* rw - transmit channel control 1 */
|
||||
#define DS_TCC2 0xa1 /* rw - transmit channel control 2 */
|
||||
#define DS_TCC3 0xa2 /* rw - transmit channel control 3 */
|
||||
#define DS_TCC4 0xa3 /* rw - transmit channel control 4 */
|
||||
#define DS_RCC1 0xa4 /* rw - receive channel control 1 */
|
||||
#define DS_RCC2 0xa5 /* rw - receive channel control 2 */
|
||||
#define DS_RCC3 0xa6 /* rw - receive channel control 3 */
|
||||
#define DS_RCC4 0xa7 /* rw - receive channel control 4 */
|
||||
|
||||
#define DS_CCR4 0xa8 /* rw - common control 4 */
|
||||
#define DS_TDS0M 0xa9 /* r - transmit ds0 monitor */
|
||||
#define DS_CCR5 0xaa /* rw - common control 5 */
|
||||
#define DS_RDS0M 0xab /* r - receive ds0 monitor */
|
||||
#define DS_TEST3 0xac /* rw - test 3, set to 00h */
|
||||
|
||||
#define DS_HCR 0xb0 /* rw - hdlc control */
|
||||
#define DS_HSR 0xb1 /* rw - hdlc status */
|
||||
#define DS_HIMR 0xb2 /* rw - hdlc interrupt mask */
|
||||
#define DS_RHIR 0xb3 /* rw - receive hdlc information */
|
||||
#define DS_RHFR 0xb4 /* rw - receive hdlc fifo */
|
||||
#define DS_IBO 0xb5 /* rw - interleave bus operation */
|
||||
#define DS_THIR 0xb6 /* rw - transmit hdlc information */
|
||||
#define DS_THFR 0xb7 /* rw - transmit hdlc fifo */
|
||||
#define DS_RDC1 0xb8 /* rw - receive hdlc ds0 control 1 */
|
||||
#define DS_RDC2 0xb9 /* rw - receive hdlc ds0 control 2 */
|
||||
#define DS_TDC1 0xba /* rw - transmit hdlc ds0 control 1 */
|
||||
#define DS_TDC2 0xbb /* rw - transmit hdlc ds0 control 2 */
|
||||
|
||||
#define CCR4_RLB 0x80 /* enable remote loopback */
|
||||
#define CCR4_LLB 0x40 /* enable local loopback */
|
||||
#define CCR5_LIRST 0x80 /* line interface reset */
|
||||
#define CCR6_RESR 0x02 /* receive elastic store reset */
|
||||
#define CCR6_TESR 0x01 /* transmit elastic store reset */
|
||||
@ -1,492 +0,0 @@
|
||||
/*-
|
||||
* Hitachi HD64570 serial communications adaptor registers.
|
||||
*
|
||||
* Copyright (C) 1996 Cronyx Engineering.
|
||||
* Author: Serge Vakulenko, <vak@cronyx.ru>
|
||||
*
|
||||
* This software is distributed with NO WARRANTIES, not even the implied
|
||||
* warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* Authors grant any other persons or organisations permission to use
|
||||
* or modify this software as long as this message is kept with the software,
|
||||
* all derivative works or modified versions.
|
||||
*
|
||||
* Cronyx Id: hdc64570.h,v 1.1.2.2 2003/11/12 17:31:21 rik Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/*
|
||||
* Low power mode control register.
|
||||
*/
|
||||
#define HD_LPR 0x00 /* low power register */
|
||||
|
||||
/*
|
||||
* Interrupt control registers.
|
||||
*/
|
||||
#define HD_IVR 0x1a /* interrupt vector register */
|
||||
#define HD_IMVR 0x1c /* interrupt modified vector register */
|
||||
#define HD_ITCR 0x18 /* interrupt control register */
|
||||
#define HD_ISR0 0x10 /* interrupt status register 0, ro */
|
||||
#define HD_ISR1 0x11 /* interrupt status register 1, ro */
|
||||
#define HD_ISR2 0x12 /* interrupt status register 2, ro */
|
||||
#define HD_IER0 0x14 /* interrupt enable register 0 */
|
||||
#define HD_IER1 0x15 /* interrupt enable register 1 */
|
||||
#define HD_IER2 0x16 /* interrupt enable register 2 */
|
||||
|
||||
/*
|
||||
* Multiprotocol serial communication interface registers.
|
||||
*/
|
||||
#define HD_MD0_0 0x2e /* mode register 0 chan 0 */
|
||||
#define HD_MD0_1 0x4e /* mode register 0 chan 1 */
|
||||
#define HD_MD1_0 0x2f /* mode register 1 chan 0 */
|
||||
#define HD_MD1_1 0x4f /* mode register 1 chan 1 */
|
||||
#define HD_MD2_0 0x30 /* mode register 2 chan 0 */
|
||||
#define HD_MD2_1 0x50 /* mode register 2 chan 1 */
|
||||
#define HD_CTL_0 0x31 /* control register chan 0 */
|
||||
#define HD_CTL_1 0x51 /* control register chan 1 */
|
||||
#define HD_RXS_0 0x36 /* RX clock source register chan 0 */
|
||||
#define HD_RXS_1 0x56 /* RX clock source register chan 1 */
|
||||
#define HD_TXS_0 0x37 /* TX clock source register chan 0 */
|
||||
#define HD_TXS_1 0x57 /* TX clock source register chan 1 */
|
||||
#define HD_TMC_0 0x35 /* time constant register chan 0 */
|
||||
#define HD_TMC_1 0x55 /* time constant register chan 1 */
|
||||
#define HD_CMD_0 0x2c /* command register chan 0, wo */
|
||||
#define HD_CMD_1 0x4c /* command register chan 1, wo */
|
||||
#define HD_ST0_0 0x22 /* status register 0 chan 0, ro */
|
||||
#define HD_ST0_1 0x42 /* status register 0 chan 1, ro */
|
||||
#define HD_ST1_0 0x23 /* status register 1 chan 0 */
|
||||
#define HD_ST1_1 0x43 /* status register 1 chan 1 */
|
||||
#define HD_ST2_0 0x24 /* status register 2 chan 0 */
|
||||
#define HD_ST2_1 0x44 /* status register 2 chan 1 */
|
||||
#define HD_ST3_0 0x25 /* status register 3 chan 0, ro */
|
||||
#define HD_ST3_1 0x45 /* status register 3 chan 1, ro */
|
||||
#define HD_FST_0 0x26 /* frame status register chan 0 */
|
||||
#define HD_FST_1 0x46 /* frame status register chan 1 */
|
||||
#define HD_IE0_0 0x28 /* interrupt enable register 0 chan 0 */
|
||||
#define HD_IE0_1 0x48 /* interrupt enable register 0 chan 1 */
|
||||
#define HD_IE1_0 0x29 /* interrupt enable register 1 chan 0 */
|
||||
#define HD_IE1_1 0x49 /* interrupt enable register 1 chan 1 */
|
||||
#define HD_IE2_0 0x2a /* interrupt enable register 2 chan 0 */
|
||||
#define HD_IE2_1 0x4a /* interrupt enable register 2 chan 1 */
|
||||
#define HD_FIE_0 0x2b /* frame interrupt enable register chan 0 */
|
||||
#define HD_FIE_1 0x4b /* frame interrupt enable register chan 1 */
|
||||
#define HD_SA0_0 0x32 /* sync/address register 0 chan 0 */
|
||||
#define HD_SA0_1 0x52 /* sync/address register 0 chan 1 */
|
||||
#define HD_SA1_0 0x33 /* sync/address register 1 chan 0 */
|
||||
#define HD_SA1_1 0x53 /* sync/address register 1 chan 1 */
|
||||
#define HD_IDL_0 0x34 /* idle pattern register chan 0 */
|
||||
#define HD_IDL_1 0x54 /* idle pattern register chan 1 */
|
||||
#define HD_TRB_0 0x20 /* TX/RX buffer register chan 0 */
|
||||
#define HD_TRB_1 0x40 /* TX/RX buffer register chan 1 */
|
||||
#define HD_RRC_0 0x3a /* RX ready control register chan 0 */
|
||||
#define HD_RRC_1 0x5a /* RX ready control register chan 1 */
|
||||
#define HD_TRC0_0 0x38 /* TX ready control register 0 chan 0 */
|
||||
#define HD_TRC0_1 0x58 /* TX ready control register 0 chan 1 */
|
||||
#define HD_TRC1_0 0x39 /* TX ready control register 1 chan 0 */
|
||||
#define HD_TRC1_1 0x59 /* TX ready control register 1 chan 1 */
|
||||
#define HD_CST_0 0x3c /* current status register chan 0 */
|
||||
#define HD_CST_1 0x5c /* current status register chan 1 */
|
||||
|
||||
/*
|
||||
* DMA controller registers.
|
||||
*/
|
||||
#define HD_PCR 0x08 /* DMA priority control register */
|
||||
#define HD_DMER 0x09 /* DMA master enable register */
|
||||
|
||||
#define HD_DAR_0R 0x80 /* destination address chan 0rx */
|
||||
#define HD_DAR_0T 0xa0 /* destination address chan 0tx */
|
||||
#define HD_DAR_1R 0xc0 /* destination address chan 1rx */
|
||||
#define HD_DAR_1T 0xe0 /* destination address chan 1tx */
|
||||
#define HD_DARB_0R 0x82 /* destination address B chan 0rx */
|
||||
#define HD_DARB_0T 0xa2 /* destination address B chan 0tx */
|
||||
#define HD_DARB_1R 0xc2 /* destination address B chan 1rx */
|
||||
#define HD_DARB_1T 0xe2 /* destination address B chan 1tx */
|
||||
#define HD_SAR_0R 0x84 /* source address chan 0rx */
|
||||
#define HD_SAR_0T 0xa4 /* source address chan 0tx */
|
||||
#define HD_SAR_1R 0xc4 /* source address chan 1rx */
|
||||
#define HD_SAR_1T 0xe4 /* source address chan 1tx */
|
||||
#define HD_SARB_0R 0x86 /* source address B chan 0rx */
|
||||
#define HD_SARB_0T 0xa6 /* source address B chan 0tx */
|
||||
#define HD_SARB_1R 0xc6 /* source address B chan 1rx */
|
||||
#define HD_SARB_1T 0xe6 /* source address B chan 1tx */
|
||||
#define HD_CDA_0R 0x88 /* current descriptor address chan 0rx */
|
||||
#define HD_CDA_0T 0xa8 /* current descriptor address chan 0tx */
|
||||
#define HD_CDA_1R 0xc8 /* current descriptor address chan 1rx */
|
||||
#define HD_CDA_1T 0xe8 /* current descriptor address chan 1tx */
|
||||
#define HD_EDA_0R 0x8a /* error descriptor address chan 0rx */
|
||||
#define HD_EDA_0T 0xaa /* error descriptor address chan 0tx */
|
||||
#define HD_EDA_1R 0xca /* error descriptor address chan 1rx */
|
||||
#define HD_EDA_1T 0xea /* error descriptor address chan 1tx */
|
||||
#define HD_BFL_0R 0x8c /* receive buffer length chan 0rx */
|
||||
#define HD_BFL_1R 0xcc /* receive buffer length chan 1rx */
|
||||
#define HD_BCR_0R 0x8e /* byte count register chan 0rx */
|
||||
#define HD_BCR_0T 0xae /* byte count register chan 0tx */
|
||||
#define HD_BCR_1R 0xce /* byte count register chan 1rx */
|
||||
#define HD_BCR_1T 0xee /* byte count register chan 1tx */
|
||||
#define HD_DSR_0R 0x90 /* DMA status register chan 0rx */
|
||||
#define HD_DSR_0T 0xb0 /* DMA status register chan 0tx */
|
||||
#define HD_DSR_1R 0xd0 /* DMA status register chan 1rx */
|
||||
#define HD_DSR_1T 0xf0 /* DMA status register chan 1tx */
|
||||
#define HD_DMR_0R 0x91 /* DMA mode register chan 0rx */
|
||||
#define HD_DMR_0T 0xb1 /* DMA mode register chan 0tx */
|
||||
#define HD_DMR_1R 0xd1 /* DMA mode register chan 1rx */
|
||||
#define HD_DMR_1T 0xf1 /* DMA mode register chan 1tx */
|
||||
#define HD_FCT_0R 0x93 /* end-of-frame intr counter chan 0rx, ro */
|
||||
#define HD_FCT_0T 0xb3 /* end-of-frame intr counter chan 0tx, ro */
|
||||
#define HD_FCT_1R 0xd3 /* end-of-frame intr counter chan 1rx, ro */
|
||||
#define HD_FCT_1T 0xf3 /* end-of-frame intr counter chan 1tx, ro */
|
||||
#define HD_DIR_0R 0x94 /* DMA interrupt enable register chan 0rx */
|
||||
#define HD_DIR_0T 0xb4 /* DMA interrupt enable register chan 0tx */
|
||||
#define HD_DIR_1R 0xd4 /* DMA interrupt enable register chan 1rx */
|
||||
#define HD_DIR_1T 0xf4 /* DMA interrupt enable register chan 1tx */
|
||||
#define HD_DCR_0R 0x95 /* DMA command register chan 0rx, wo */
|
||||
#define HD_DCR_0T 0xb5 /* DMA command register chan 0tx, wo */
|
||||
#define HD_DCR_1R 0xd5 /* DMA command register chan 1rx, wo */
|
||||
#define HD_DCR_1T 0xf5 /* DMA command register chan 1tx, wo */
|
||||
|
||||
/*
|
||||
* Timer registers.
|
||||
*/
|
||||
#define HD_TCNT_0R 0x60 /* timer up counter chan 0rx */
|
||||
#define HD_TCNT_0T 0x68 /* timer up counter chan 0tx */
|
||||
#define HD_TCNT_1R 0x70 /* timer up counter chan 1rx */
|
||||
#define HD_TCNT_1T 0x78 /* timer up counter chan 1tx */
|
||||
#define HD_TCONR_0R 0x62 /* timer constant register chan 0rx, wo */
|
||||
#define HD_TCONR_0T 0x6a /* timer constant register chan 0tx, wo */
|
||||
#define HD_TCONR_1R 0x72 /* timer constant register chan 1rx, wo */
|
||||
#define HD_TCONR_1T 0x7a /* timer constant register chan 1tx, wo */
|
||||
#define HD_TCSR_0R 0x64 /* timer control/status register chan 0rx */
|
||||
#define HD_TCSR_0T 0x6c /* timer control/status register chan 0tx */
|
||||
#define HD_TCSR_1R 0x74 /* timer control/status register chan 1rx */
|
||||
#define HD_TCSR_1T 0x7c /* timer control/status register chan 1tx */
|
||||
#define HD_TEPR_0R 0x65 /* timer expand prescale register chan 0rx */
|
||||
#define HD_TEPR_0T 0x6d /* timer expand prescale register chan 0tx */
|
||||
#define HD_TEPR_1R 0x75 /* timer expand prescale register chan 1rx */
|
||||
#define HD_TEPR_1T 0x7d /* timer expand prescale register chan 1tx */
|
||||
|
||||
/*
|
||||
* Wait controller registers.
|
||||
*/
|
||||
#define HD_PABR0 0x02 /* physical address boundary register 0 */
|
||||
#define HD_PABR1 0x03 /* physical address boundary register 1 */
|
||||
#define HD_WCRL 0x04 /* wait control register L */
|
||||
#define HD_WCRM 0x05 /* wait control register M */
|
||||
#define HD_WCRH 0x06 /* wait control register H */
|
||||
|
||||
/*
|
||||
* Interrupt modified vector register (IMVR) bits.
|
||||
*/
|
||||
#define IMVR_CHAN1 040 /* channel 1 vector bit */
|
||||
#define IMVR_VECT_MASK 037 /* interrupt reason mask */
|
||||
|
||||
#define IMVR_RX_RDY 004 /* receive buffer ready */
|
||||
#define IMVR_RX_INT 010 /* receive status */
|
||||
#define IMVR_RX_DMERR 024 /* receive DMA error */
|
||||
#define IMVR_RX_DMOK 026 /* receive DMA normal end */
|
||||
#define IMVR_RX_TIMER 034 /* timer 0/2 count match */
|
||||
|
||||
#define IMVR_TX_RDY 006 /* transmit buffer ready */
|
||||
#define IMVR_TX_INT 012 /* transmit status */
|
||||
#define IMVR_TX_DMERR 030 /* transmit DMA error */
|
||||
#define IMVR_TX_DMOK 032 /* transmit DMA normal end */
|
||||
#define IMVR_TX_TIMER 036 /* timer 1/3 count match */
|
||||
|
||||
/*
|
||||
* Interrupt control register (ITCR) bits.
|
||||
*/
|
||||
#define ITCR_PRIO_DMAC 0x80 /* DMA priority higher than MSCI */
|
||||
#define ITCR_CYCLE_VOID 0x00 /* non-acknowledge cycle */
|
||||
#define ITCR_CYCLE_SINGLE 0x20 /* single acknowledge cycle */
|
||||
#define ITCR_CYCLE_DOUBLE 0x40 /* double acknowledge cycle */
|
||||
#define ITCR_VECT_MOD 0x10 /* interrupt modified vector flag */
|
||||
|
||||
/*
|
||||
* Interrupt status register 0 (ISR0) bits.
|
||||
*/
|
||||
#define ISR0_RX_RDY_0 0x01 /* channel 0 receiver ready */
|
||||
#define ISR0_TX_RDY_0 0x02 /* channel 0 transmitter ready */
|
||||
#define ISR0_RX_INT_0 0x04 /* channel 0 receiver status */
|
||||
#define ISR0_TX_INT_0 0x08 /* channel 0 transmitter status */
|
||||
#define ISR0_RX_RDY_1 0x10 /* channel 1 receiver ready */
|
||||
#define ISR0_TX_RDY_1 0x20 /* channel 1 transmitter ready */
|
||||
#define ISR0_RX_INT_1 0x40 /* channel 1 receiver status */
|
||||
#define ISR0_TX_INT_1 0x80 /* channel 1 transmitter status */
|
||||
|
||||
/*
|
||||
* Interrupt status register 1 (ISR1) bits.
|
||||
*/
|
||||
#define ISR1_RX_DMERR_0 0x01 /* channel 0 receive DMA error */
|
||||
#define ISR1_RX_DMOK_0 0x02 /* channel 0 receive DMA finished */
|
||||
#define ISR1_TX_DMERR_0 0x04 /* channel 0 transmit DMA error */
|
||||
#define ISR1_TX_DMOK_0 0x08 /* channel 0 transmit DMA finished */
|
||||
#define ISR1_RX_DMERR_1 0x10 /* channel 1 receive DMA error */
|
||||
#define ISR1_RX_DMOK_1 0x20 /* channel 1 receive DMA finished */
|
||||
#define ISR1_TX_DMERR_1 0x40 /* channel 1 transmit DMA error */
|
||||
#define ISR1_TX_DMOK_1 0x80 /* channel 1 transmit DMA finished */
|
||||
|
||||
/*
|
||||
* Interrupt status register 2 (ISR2) bits.
|
||||
*/
|
||||
#define ISR2_RX_TIMER_0 0x10 /* channel 0 receive timer */
|
||||
#define ISR2_TX_TIMER_0 0x20 /* channel 0 transmit timer */
|
||||
#define ISR2_RX_TIMER_1 0x40 /* channel 1 receive timer */
|
||||
#define ISR2_TX_TIMER_1 0x80 /* channel 1 transmit timer */
|
||||
|
||||
/*
|
||||
* Interrupt enable register 0 (IER0) bits.
|
||||
*/
|
||||
#define IER0_RX_RDYE_0 0x01 /* channel 0 receiver ready enable */
|
||||
#define IER0_TX_RDYE_0 0x02 /* channel 0 transmitter ready enable */
|
||||
#define IER0_RX_INTE_0 0x04 /* channel 0 receiver status enable */
|
||||
#define IER0_TX_INTE_0 0x08 /* channel 0 transmitter status enable */
|
||||
#define IER0_RX_RDYE_1 0x10 /* channel 1 receiver ready enable */
|
||||
#define IER0_TX_RDYE_1 0x20 /* channel 1 transmitter ready enable */
|
||||
#define IER0_RX_INTE_1 0x40 /* channel 1 receiver status enable */
|
||||
#define IER0_TX_INTE_1 0x80 /* channel 1 transmitter status enable */
|
||||
#define IER0_MASK_0 0x0f /* channel 0 bits */
|
||||
#define IER0_MASK_1 0xf0 /* channel 1 bits */
|
||||
|
||||
/*
|
||||
* Interrupt enable register 1 (IER1) bits.
|
||||
*/
|
||||
#define IER1_RX_DMERE_0 0x01 /* channel 0 receive DMA error enable */
|
||||
#define IER1_RX_DME_0 0x02 /* channel 0 receive DMA finished enable */
|
||||
#define IER1_TX_DMERE_0 0x04 /* channel 0 transmit DMA error enable */
|
||||
#define IER1_TX_DME_0 0x08 /* channel 0 transmit DMA finished enable */
|
||||
#define IER1_RX_DMERE_1 0x10 /* channel 1 receive DMA error enable */
|
||||
#define IER1_RX_DME_1 0x20 /* channel 1 receive DMA finished enable */
|
||||
#define IER1_TX_DMERE_1 0x40 /* channel 1 transmit DMA error enable */
|
||||
#define IER1_TX_DME_1 0x80 /* channel 1 transmit DMA finished enable */
|
||||
#define IER1_MASK_0 0x0f /* channel 0 bits */
|
||||
#define IER1_MASK_1 0xf0 /* channel 1 bits */
|
||||
|
||||
/*
|
||||
* Interrupt enable register 2 (IER2) bits.
|
||||
*/
|
||||
#define IER2_RX_TME_0 0x10 /* channel 0 receive timer enable */
|
||||
#define IER2_TX_TME_0 0x20 /* channel 0 transmit timer enable */
|
||||
#define IER2_RX_TME_1 0x40 /* channel 1 receive timer enable */
|
||||
#define IER2_TX_TME_1 0x80 /* channel 1 transmit timer enable */
|
||||
#define IER2_MASK_0 0x30 /* channel 0 bits */
|
||||
#define IER2_MASK_1 0xc0 /* channel 1 bits */
|
||||
|
||||
/*
|
||||
* Control register (CTL) bits.
|
||||
*/
|
||||
#define CTL_RTS_INV 0x01 /* RTS control bit (inverted) */
|
||||
#define CTL_SYNCLD 0x04 /* load SYN characters */
|
||||
#define CTL_BRK 0x08 /* async: send break */
|
||||
#define CTL_IDLE_MARK 0 /* HDLC: when idle, transmit mark */
|
||||
#define CTL_IDLE_PTRN 0x10 /* HDLC: when idle, transmit an idle pattern */
|
||||
#define CTL_UDRN_ABORT 0 /* HDLC: on underrun - abort */
|
||||
#define CTL_UDRN_FCS 0x20 /* HDLC: on underrun - send FCS/flag */
|
||||
|
||||
/*
|
||||
* Command register (CMD) values.
|
||||
*/
|
||||
#define CMD_TX_RESET 001 /* reset: disable, clear buffer/status/BRK */
|
||||
#define CMD_TX_ENABLE 002 /* transmitter enable */
|
||||
#define CMD_TX_DISABLE 003 /* transmitter disable */
|
||||
#define CMD_TX_CRC_INIT 004 /* initialize CRC calculator */
|
||||
#define CMD_TX_EOM_CHAR 006 /* set end-of-message char */
|
||||
#define CMD_TX_ABORT 007 /* abort transmission (HDLC mode) */
|
||||
#define CMD_TX_MPON 010 /* transmit char with MP bit on (async) */
|
||||
#define CMD_TX_CLEAR 011 /* clear the transmit buffer */
|
||||
|
||||
#define CMD_RX_RESET 021 /* reset: disable, clear buffer/status */
|
||||
#define CMD_RX_ENABLE 022 /* receiver enable */
|
||||
#define CMD_RX_DISABLE 023 /* receiver disable */
|
||||
#define CMD_RX_CRC_INIT 024 /* initialize CRC calculator */
|
||||
#define CMD_RX_REJECT 025 /* reject current message (sync mode) */
|
||||
#define CMD_RX_SRCH_MP 026 /* skip all until the char witn MP bit on */
|
||||
|
||||
#define CMD_NOOP 000 /* continue current operation */
|
||||
#define CMD_CHAN_RESET 041 /* init registers, disable/clear RX/TX */
|
||||
#define CMD_SEARCH_MODE 061 /* set the ADPLL to search mode */
|
||||
|
||||
/*
|
||||
* Status register 0 (ST0) bits.
|
||||
*/
|
||||
#define ST0_RX_RDY 0x01 /* receiver ready */
|
||||
#define ST0_TX_RDY 0x02 /* transmitter ready */
|
||||
#define ST0_RX_INT 0x40 /* receiver status interrupt */
|
||||
#define ST0_TX_INT 0x80 /* transmitter status interrupt */
|
||||
|
||||
/*
|
||||
* Status register 1 (ST1) bits.
|
||||
*/
|
||||
#define ST1_CDCD 0x04 /* carrier changed */
|
||||
#define ST1_CCTS 0x08 /* CTS changed */
|
||||
#define ST1_IDL 0x40 /* transmitter idle, ro */
|
||||
|
||||
#define ST1_ASYNC_BRKE 0x01 /* break end detected */
|
||||
#define ST1_ASYNC_BRKD 0x02 /* break start detected */
|
||||
#define ST1_ASYNC_BITS "\20\1brke\2brkd\3cdcd\4ccts\7idl"
|
||||
|
||||
#define ST1_HDLC_IDLD 0x01 /* idle sequence start detected */
|
||||
#define ST1_HDLC_ABTD 0x02 /* abort sequence start detected */
|
||||
#define ST1_HDLC_FLGD 0x10 /* flag detected */
|
||||
#define ST1_HDLC_UDRN 0x80 /* underrun detected */
|
||||
#define ST1_HDLC_BITS "\20\1idld\2abtd\3cdcd\4ccts\5flgd\7idl\10udrn"
|
||||
|
||||
/*
|
||||
* Status register 2 (ST2) bits.
|
||||
*/
|
||||
#define ST2_OVRN 0x08 /* overrun error detected */
|
||||
|
||||
#define ST2_ASYNC_FRME 0x10 /* framing error detected */
|
||||
#define ST2_ASYNC_PE 0x20 /* parity error detected */
|
||||
#define ST2_ASYNC_PMP 0x40 /* parity/MP bit = 1 */
|
||||
#define ST2_ASYNC_BITS "\20\4ovrn\5frme\6pe\7pmp"
|
||||
|
||||
#define ST2_HDLC_CRCE 0x04 /* CRC error detected */
|
||||
#define ST2_HDLC_RBIT 0x10 /* residual bit frame detected */
|
||||
#define ST2_HDLC_ABT 0x20 /* frame with abort end detected */
|
||||
#define ST2_HDLC_SHRT 0x40 /* short frame detected */
|
||||
#define ST2_HDLC_EOM 0x80 /* receive frame end detected */
|
||||
#define ST2_HDLC_BITS "\20\3crce\4ovrn\5rbit\6abt\7shrt\10eom"
|
||||
|
||||
/*
|
||||
* Status register 3 (ST3) bits.
|
||||
*/
|
||||
#define ST3_RX_ENABLED 0x01 /* receiver is enabled */
|
||||
#define ST3_TX_ENABLED 0x02 /* transmitter is enabled */
|
||||
#define ST3_DCD_INV 0x04 /* DCD input line inverted */
|
||||
#define ST3_CTS_INV 0x08 /* CTS input line inverted */
|
||||
#define ST3_ASYNC_BITS "\20\1rx\2tx\3nodcd\4nocts"
|
||||
|
||||
#define ST3_HDLC_SEARCH 0x10 /* ADPLL search mode */
|
||||
#define ST3_HDLC_TX 0x20 /* channel is transmitting data */
|
||||
#define ST3_HDLC_BITS "\20\1rx\2tx\3nodcd\4nocts\5search\6txact"
|
||||
|
||||
/*
|
||||
* Frame status register (FST) bits, HDLC mode only.
|
||||
*/
|
||||
#define FST_CRCE 0x04 /* CRC error detected */
|
||||
#define FST_OVRN 0x08 /* overrun error detected */
|
||||
#define FST_RBIT 0x10 /* residual bit frame detected */
|
||||
#define FST_ABT 0x20 /* frame with abort end detected */
|
||||
#define FST_SHRT 0x40 /* short frame detected */
|
||||
#define FST_EOM 0x80 /* frame end flag */
|
||||
|
||||
#define FST_EOT 0x01 /* end of transfer, transmit only */
|
||||
|
||||
/*
|
||||
* Interrupt enable register 0 (IE0) bits.
|
||||
*/
|
||||
#define IE0_RX_RDYE 0x01 /* receiver ready interrupt enable */
|
||||
#define IE0_TX_RDYE 0x02 /* transmitter ready interrupt enable */
|
||||
#define IE0_RX_INTE 0x40 /* receiver status interrupt enable */
|
||||
#define IE0_TX_INTE 0x80 /* transmitter status interrupt enable */
|
||||
|
||||
/*
|
||||
* Interrupt enable register 1 (IE1) bits.
|
||||
*/
|
||||
#define IE1_CDCDE 0x04 /* carrier changed */
|
||||
#define IE1_CCTSE 0x08 /* CTS changed */
|
||||
#define IE1_IDLE 0x40 /* transmitter idle, ro */
|
||||
|
||||
#define IE1_ASYNC_BRKEE 0x01 /* break end detected */
|
||||
#define IE1_ASYNC_BRKDE 0x02 /* break start detected */
|
||||
|
||||
#define IE1_HDLC_IDLDE 0x01 /* idle sequence start detected */
|
||||
#define IE1_HDLC_ABTDE 0x02 /* abort sequence start detected */
|
||||
#define IE1_HDLC_FLGDE 0x10 /* flag detected */
|
||||
#define IE1_HDLC_UDRNE 0x80 /* underrun detected */
|
||||
|
||||
/*
|
||||
* Interrupt enable register 2 (IE2) bits.
|
||||
*/
|
||||
#define IE2_OVRNE 0x08 /* overrun error detected */
|
||||
|
||||
#define IE2_ASYNC_FRMEE 0x10 /* framing error detected */
|
||||
#define IE2_ASYNC_PEE 0x20 /* parity error detected */
|
||||
#define IE2_ASYNC_PMPE 0x40 /* parity/MP bit = 1 */
|
||||
|
||||
#define IE2_HDLC_CRCEE 0x04 /* CRC error detected */
|
||||
#define IE2_HDLC_RBITE 0x10 /* residual bit frame detected */
|
||||
#define IE2_HDLC_ABTE 0x20 /* frame with abort end detected */
|
||||
#define IE2_HDLC_SHRTE 0x40 /* short frame detected */
|
||||
#define IE2_HDLC_EOME 0x80 /* receive frame end detected */
|
||||
|
||||
/*
|
||||
* Frame interrupt enable register (FIE) bits, HDLC mode only.
|
||||
*/
|
||||
#define FIE_EOMFE 0x80 /* receive frame end detected */
|
||||
|
||||
/*
|
||||
* Current status register (CST0,CST1) bits.
|
||||
* For other bits, see ST2.
|
||||
*/
|
||||
#define CST0_CDE 0x0001 /* data present on top of FIFO */
|
||||
#define CST1_CDE 0x0100 /* data present on second stage of FIFO */
|
||||
|
||||
/*
|
||||
* Receive/transmit clock source register (RXS/TXS) bits.
|
||||
*/
|
||||
#define CLK_MASK 0x70 /* RXC/TXC clock input mask */
|
||||
#define CLK_LINE 0x00 /* RXC/TXC line input */
|
||||
#define CLK_INT 0x40 /* internal baud rate generator */
|
||||
|
||||
#define CLK_RXS_LINE_NS 0x20 /* RXC line with noise suppression */
|
||||
#define CLK_RXS_DPLL_INT 0x60 /* ADPLL based on internal BRG */
|
||||
#define CLK_RXS_DPLL_LINE 0x70 /* ADPLL based on RXC line */
|
||||
|
||||
#define CLK_TXS_RECV 0x60 /* receive clock */
|
||||
|
||||
/*
|
||||
* DMA status register (DSR) bits.
|
||||
*/
|
||||
#define DSR_DMA_DISABLE 0x00 /* disable DMA channel */
|
||||
#define DSR_DMA_ENABLE 0x02 /* enable DMA channel */
|
||||
#define DSR_DMA_CONTINUE 0x01 /* do not enable/disable DMA channel */
|
||||
#define DSR_CHAIN_COF 0x10 /* counter overflow */
|
||||
#define DSR_CHAIN_BOF 0x20 /* buffer overflow/underflow */
|
||||
#define DSR_CHAIN_EOM 0x40 /* frame transfer completed */
|
||||
#define DSR_EOT 0x80 /* transfer completed */
|
||||
#define DSR_BITS "\20\1cont\2enab\5cof\6bof\7eom\10eot"
|
||||
|
||||
/*
|
||||
* DMA mode register (DMR) bits.
|
||||
*/
|
||||
#define DMR_CHAIN_CNTE 0x02 /* enable frame interrupt counter (FCT) */
|
||||
#define DMR_CHAIN_NF 0x04 /* multi-frame block chain */
|
||||
#define DMR_TMOD 0x10 /* chained-block transfer mode */
|
||||
|
||||
/*
|
||||
* DMA interrupt enable register (DIR) bits.
|
||||
*/
|
||||
#define DIR_CHAIN_COFE 0x10 /* counter overflow */
|
||||
#define DIR_CHAIN_BOFE 0x20 /* buffer overflow/underflow */
|
||||
#define DIR_CHAIN_EOME 0x40 /* frame transfer completed */
|
||||
#define DIR_EOTE 0x80 /* transfer completed */
|
||||
|
||||
/*
|
||||
* DMA command register (DCR) values.
|
||||
*/
|
||||
#define DCR_ABORT 1 /* software abort: initialize DMA channel */
|
||||
#define DCR_CLEAR 2 /* clear FCT and EOM bit of DSR */
|
||||
|
||||
/*
|
||||
* DMA master enable register (DME) bits.
|
||||
*/
|
||||
#define DME_ENABLE 0x80 /* enable DMA master operation */
|
||||
|
||||
/*
|
||||
* Timer control/status register (TCSR) bits.
|
||||
*/
|
||||
#define TCSR_ENABLE 0x10 /* timer starts incrementing */
|
||||
#define TCSR_INTR 0x40 /* timer interrupt enable */
|
||||
#define TCSR_MATCH 0x80 /* TCNT and TCONR are equal */
|
||||
|
||||
/*
|
||||
* Timer expand prescale register (TEPR) values.
|
||||
*/
|
||||
#define TEPR_1 0 /* sysclk/8 */
|
||||
#define TEPR_2 1 /* sysclk/8/2 */
|
||||
#define TEPR_4 2 /* sysclk/8/4 */
|
||||
#define TEPR_8 3 /* sysclk/8/8 */
|
||||
#define TEPR_16 4 /* sysclk/8/16 */
|
||||
#define TEPR_32 5 /* sysclk/8/32 */
|
||||
#define TEPR_64 6 /* sysclk/8/64 */
|
||||
#define TEPR_128 7 /* sysclk/8/128 */
|
||||
2207
sys/dev/ctau/if_ct.c
2207
sys/dev/ctau/if_ct.c
File diff suppressed because it is too large
Load Diff
@ -1,44 +0,0 @@
|
||||
/*-
|
||||
* Level One LXT318 E1 transceiver registers.
|
||||
* Crystal CS61318 E1 Line Interface Unit registers.
|
||||
* Crystal CS61581 T1/E1 Line Interface Unit registers.
|
||||
*
|
||||
* Copyright (C) 1996 Cronyx Engineering.
|
||||
* Author: Serge Vakulenko, <vak@cronyx.ru>
|
||||
*
|
||||
* Copyright (C) 2003 Cronyx Engineering.
|
||||
* Author: Roman Kurakin, <rik@cronyx.ru>
|
||||
*
|
||||
* This software is distributed with NO WARRANTIES, not even the implied
|
||||
* warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* Authors grant any other persons or organisations permission to use
|
||||
* or modify this software as long as this message is kept with the software,
|
||||
* all derivative works or modified versions.
|
||||
*
|
||||
* Cronyx Id: lxt318.h,v 1.2.4.4 2003/11/14 19:08:45 rik Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#define LX_WRITE 0x00
|
||||
#define LX_READ 0x01
|
||||
|
||||
#define LX_CCR1 0x10
|
||||
#define LX_CCR2 0x11 /* CS61318 */
|
||||
#define LX_EQGAIN 0x12 /* CS61318 */
|
||||
#define LX_RAM 0x13 /* CS61318 */
|
||||
#define LX_CCR3 0x14 /* CS61581 */
|
||||
#define LX_DPEC 0x15 /* CS61581 */
|
||||
|
||||
#define LX_LOS 0x01 /* loss of signal condition */
|
||||
#define LX_HDB3 0x04 /* HDB3 encoding enable */
|
||||
#define LX_RLOOP 0x20 /* remote loopback */
|
||||
#define LX_LLOOP 0x40 /* local loopback */
|
||||
#define LX_TAOS 0x80 /* transmit all ones */
|
||||
|
||||
#define LX_RESET (LX_RLOOP | LX_LLOOP) /* reset the chip */
|
||||
|
||||
#define LX_CCR2_LH 0x00 /* Long Haul mode */
|
||||
#define LX_CCR2_SH 0x01 /* Long Haul mode */
|
||||
|
||||
#define LX_CCR3_E1_LH 0x60 /* Long Haul mode */
|
||||
@ -1,31 +0,0 @@
|
||||
/*-
|
||||
* Defines for Cronyx-Tau adapter driver.
|
||||
*
|
||||
* Copyright (C) 1999-2004 Cronyx Engineering.
|
||||
* Author: Kurakin Roman, <rik@cronyx.ru>
|
||||
*
|
||||
* This software is distributed with NO WARRANTIES, not even the implied
|
||||
* warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* Authors grant any other persons or organisations a permission to use,
|
||||
* modify and redistribute this software in source and binary forms,
|
||||
* as long as this message is kept with the software, all derivative
|
||||
* works or modified versions.
|
||||
*
|
||||
* Cronyx Id: ng_ct.h,v 1.1.2.3 2004/01/27 14:39:11 rik Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifdef NETGRAPH
|
||||
|
||||
#ifndef _CT_NETGRAPH_H_
|
||||
#define _CT_NETGRAPH_H_
|
||||
|
||||
#define NG_CT_NODE_TYPE "ct"
|
||||
#define NGM_CT_COOKIE 942835777
|
||||
#define NG_CT_HOOK_RAW "rawdata"
|
||||
#define NG_CT_HOOK_DEBUG "debug"
|
||||
|
||||
#endif /* _CT_NETGRAPH_H_ */
|
||||
|
||||
#endif /* NETGRAPH */
|
||||
@ -1,32 +0,0 @@
|
||||
/*-
|
||||
* Cronyx firmware definitions.
|
||||
*
|
||||
* Copyright (C) 1996 Cronyx Engineering.
|
||||
* Author: Serge Vakulenko, <vak@cronyx.ru>
|
||||
*
|
||||
* This software is distributed with NO WARRANTIES, not even the implied
|
||||
* warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* Authors grant any other persons or organisations permission to use
|
||||
* or modify this software as long as this message is kept with the software,
|
||||
* all derivative works or modified versions.
|
||||
*
|
||||
* Cronyx Id: cronyxfw.h,v 1.1.2.1 2003/11/12 17:09:49 rik Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#define CRONYX_DAT_MAGIC 2001107011L /* firmware file magic */
|
||||
|
||||
typedef struct _cr_dat_tst {
|
||||
long start; /* verify start */
|
||||
long end; /* verify end */
|
||||
} cr_dat_tst_t;
|
||||
|
||||
typedef struct { /* firmware file header */
|
||||
unsigned long magic; /* firmware magic */
|
||||
long hdrsz; /* header size in bytes */
|
||||
long len; /* firmware data size in bits */
|
||||
long ntest; /* number of tests */
|
||||
unsigned long sum; /* header+tests+data checksum */
|
||||
char version[8]; /* firmware version number */
|
||||
char date[8]; /* date when compiled */
|
||||
} cr_dat_t;
|
||||
1438
sys/dev/cx/csigma.c
1438
sys/dev/cx/csigma.c
File diff suppressed because it is too large
Load Diff
@ -1,852 +0,0 @@
|
||||
/*
|
||||
* DO NOT EDIT MANUALLY!
|
||||
* This code was generated by mkfw utility
|
||||
* from the file `csigma.dat'
|
||||
*
|
||||
* Cronyx Id: csigmafw.h,v 1.1 2002/06/03 10:19:39 rik Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
long csigma_fw_len = 131234;
|
||||
|
||||
const char *csigma_fw_version = "1.2";
|
||||
const char *csigma_fw_date = "06.06.00";
|
||||
const char *csigma_fw_copyright = "Copyright (C) 2000 Cronyx Engineering.";
|
||||
|
||||
const cr_dat_tst_t csigma_fw_tvec[] = {
|
||||
{ 65066, 66278}, { 66314, 67526}, { 67562, 68774}, { 68810, 70022},
|
||||
{ 70058, 71270}, { 71306, 72518}, { 72554, 73766}, { 73802, 75014},
|
||||
{ 75050, 76262}, { 76298, 77510}, { 77546, 78758}, { 78794, 80006},
|
||||
{ 80042, 81254}, { 81290, 82502}, { 82538, 83750}, { 83786, 84998},
|
||||
{ 85034, 86246}, { 86282, 87494}, { 87530, 88742}, { 88778, 89990},
|
||||
{ 90026, 91238}, { 91274, 92486}, { 92522, 93734}, { 93770, 94982},
|
||||
{ 95018, 96230}, { 96266, 97478}, { 97514, 98726}, { 98762, 99974},
|
||||
{100010,101222}, {101258,102470}, {102506,103718}, {103754,104966},
|
||||
{105002,106214}, {106250,107462}, {107498,108710}, {108746,109958},
|
||||
{109994,111206}, {111242,112454}, {112490,113702}, {113738,114950},
|
||||
{114986,116198}, {116234,117446}, {117482,118694}, {118730,119942},
|
||||
{119978,121190}, {121226,122438}, {122474,123686}, {123722,124934},
|
||||
{124970,126182}, {126218,127430}, {127466,128678}, {128714,129926},
|
||||
{129962,131174}, {131234,131234},
|
||||
};
|
||||
|
||||
const unsigned char csigma_fw_data[] = {
|
||||
155,153,97,92,102,96,32,100,100,36,112,112,112,112,48,49,48,52,52,
|
||||
52,100,100,100,116,117,36,100,100,52,52,52,52,116,100,49,49,36,37,
|
||||
37,49,49,49,117,53,33,49,49,37,37,37,37,37,36,52,97,97,97,97,100,100,
|
||||
100,97,101,96,100,36,53,96,97,97,36,97,97,112,112,96,101,100,100,100,
|
||||
36,49,48,49,49,97,101,116,37,96,101,49,52,112,33,100,100,100,112,101,
|
||||
116,49,97,36,37,52,100,101,116,36,49,100,52,33,49,49,49,100,53,100,
|
||||
100,100,32,37,37,37,37,116,112,96,97,97,97,100,100,100,97,101,96,100,
|
||||
100,97,97,113,36,33,97,97,112,112,112,48,49,49,113,53,59,57,49,100,
|
||||
96,100,100,97,97,97,97,33,48,101,112,112,112,48,49,49,113,32,101,101,
|
||||
100,36,112,112,112,112,97,96,100,48,52,52,100,100,100,52,96,113,49,
|
||||
49,33,52,52,52,52,112,113,36,37,37,37,49,49,49,37,116,117,100,100,
|
||||
117,32,37,37,49,116,37,97,97,33,53,49,49,49,113,37,97,100,100,33,53,
|
||||
113,53,32,53,101,112,48,97,101,100,100,116,37,49,48,113,49,52,112,
|
||||
48,53,49,48,100,48,113,36,100,100,100,112,97,36,100,100,52,52,52,52,
|
||||
52,52,116,33,37,37,37,49,49,49,37,52,48,49,49,37,37,101,49,36,36,117,
|
||||
97,97,97,97,100,100,100,49,76,68,100,48,33,49,49,49,37,37,37,37,96,
|
||||
52,97,97,97,97,100,100,100,97,101,96,100,100,97,97,97,97,37,33,49,
|
||||
97,112,112,48,49,49,113,112,49,48,49,113,112,112,112,112,96,96,49,
|
||||
52,52,52,100,100,100,52,37,32,49,49,117,33,52,52,100,96,52,36,37,37,
|
||||
116,100,100,100,100,48,33,49,49,49,116,100,117,32,116,52,97,97,36,
|
||||
53,49,49,113,37,33,48,49,100,112,96,97,116,100,101,48,97,100,49,48,
|
||||
49,49,97,116,113,101,100,100,36,112,112,112,96,37,37,52,52,52,100,
|
||||
100,100,52,116,36,100,100,100,100,52,101,48,48,52,36,37,37,37,49,49,
|
||||
49,53,16,177,177,112,116,100,100,52,52,52,100,52,32,113,36,37,37,37,
|
||||
49,49,49,101,100,48,49,49,37,37,37,37,53,113,100,36,97,97,97,100,100,
|
||||
100,49,49,100,100,100,97,97,97,97,33,53,101,112,112,112,48,49,49,113,
|
||||
112,49,48,49,97,37,112,112,48,97,112,48,52,52,112,49,49,49,49,36,97,
|
||||
100,100,52,112,49,117,33,112,113,36,37,116,32,49,49,49,116,48,33,49,
|
||||
53,97,33,37,113,49,33,97,36,49,101,96,100,100,36,53,100,96,100,100,
|
||||
97,97,97,97,33,53,52,112,112,112,48,49,49,113,116,112,101,100,36,112,
|
||||
112,52,97,96,112,48,52,52,52,100,100,100,52,32,179,51,37,48,100,100,
|
||||
100,36,112,112,112,32,100,49,52,52,52,100,100,100,52,96,37,100,100,
|
||||
52,52,52,52,52,113,49,36,37,37,37,49,49,49,101,100,36,49,49,37,37,
|
||||
37,37,37,116,52,97,97,97,97,100,100,100,97,101,96,100,36,53,96,97,
|
||||
97,36,97,97,112,112,96,101,100,100,100,112,32,48,49,49,97,101,116,
|
||||
37,96,101,49,52,100,52,100,100,100,48,36,49,49,97,36,37,52,100,48,
|
||||
113,113,101,37,52,33,49,49,49,52,32,32,49,49,37,37,37,37,37,116,52,
|
||||
97,97,97,97,100,100,100,97,101,96,100,100,100,100,113,36,33,97,97,
|
||||
112,112,112,48,49,49,113,37,110,108,100,101,96,100,100,97,97,97,97,
|
||||
33,48,101,112,112,112,48,49,49,113,112,49,48,49,113,112,112,112,112,
|
||||
49,101,100,48,52,52,100,100,100,52,116,36,100,100,52,52,52,52,52,48,
|
||||
112,36,37,37,37,49,49,49,37,96,100,100,100,117,32,37,37,49,36,112,
|
||||
96,97,33,53,49,49,49,49,100,96,100,100,33,53,113,53,32,53,101,112,
|
||||
96,117,101,100,100,116,37,49,48,49,100,49,112,48,53,49,48,100,48,113,
|
||||
36,100,100,100,112,97,36,100,100,52,52,52,52,52,112,97,33,37,37,37,
|
||||
49,49,49,101,101,101,100,100,32,37,101,49,36,36,37,97,97,97,97,100,
|
||||
100,100,113,77,68,116,96,32,49,49,37,37,37,37,37,96,100,97,97,97,97,
|
||||
100,100,100,113,49,48,49,49,49,96,97,97,101,52,49,97,112,112,48,49,
|
||||
49,113,112,49,48,49,113,112,112,112,112,96,96,49,52,52,52,100,100,
|
||||
100,52,116,36,100,100,112,33,52,52,100,48,52,36,37,37,116,100,100,
|
||||
100,100,48,33,49,49,37,37,49,116,32,116,52,97,33,117,53,49,49,113,
|
||||
101,97,48,49,53,101,96,97,116,100,96,112,116,96,49,48,49,49,97,113,
|
||||
101,48,49,113,112,112,112,112,96,37,37,52,52,52,100,100,100,52,49,
|
||||
49,100,100,52,52,100,96,37,112,97,33,37,37,37,49,49,49,53,21,177,177,
|
||||
97,36,100,100,52,52,52,52,52,32,113,36,37,37,37,49,49,49,37,53,33,
|
||||
49,49,37,37,37,37,53,113,100,36,100,97,97,100,100,100,113,48,97,100,
|
||||
100,97,97,97,97,33,36,101,112,112,112,48,49,49,113,96,97,48,49,49,
|
||||
113,112,112,48,97,112,48,52,52,112,49,49,49,49,32,37,100,100,52,112,
|
||||
49,117,33,112,113,36,37,116,117,100,100,100,117,48,33,49,101,33,116,
|
||||
32,113,101,116,52,37,49,101,96,100,100,36,53,100,96,100,100,97,97,
|
||||
97,97,33,53,113,112,112,112,48,49,49,113,112,49,48,49,113,112,112,
|
||||
52,97,96,112,48,52,52,52,100,100,100,52,52,230,102,53,96,101,100,36,
|
||||
112,112,112,112,32,100,52,52,52,52,100,100,100,52,33,33,49,49,33,100,
|
||||
52,52,116,100,49,49,36,37,37,49,49,49,101,116,116,100,100,32,37,37,
|
||||
37,37,36,52,97,97,97,97,100,100,100,97,101,96,100,100,100,97,97,97,
|
||||
36,97,97,112,112,96,101,100,100,100,37,117,100,100,36,112,48,113,112,
|
||||
96,101,49,52,112,117,49,49,49,53,52,116,49,97,36,37,52,100,32,117,
|
||||
113,49,112,52,33,49,49,49,116,48,33,49,49,37,37,37,37,37,116,112,96,
|
||||
97,97,97,100,100,100,33,112,48,49,49,96,97,97,37,33,97,97,112,112,
|
||||
112,48,49,49,113,117,58,57,49,100,96,100,100,97,97,97,97,33,48,101,
|
||||
112,112,112,48,49,49,113,112,49,48,49,113,112,112,112,112,49,101,100,
|
||||
96,52,52,100,100,100,52,116,36,100,100,100,52,52,52,52,48,112,36,37,
|
||||
37,37,49,49,49,101,97,48,49,49,116,32,37,37,49,36,37,97,97,33,53,49,
|
||||
49,49,49,100,96,100,100,33,48,113,48,32,53,101,112,96,117,101,100,
|
||||
100,116,37,49,48,49,37,37,113,48,53,49,48,32,32,113,36,100,100,100,
|
||||
112,117,96,100,100,52,52,52,52,52,32,97,33,37,37,37,49,49,49,37,53,
|
||||
33,49,49,37,37,101,49,36,36,37,97,97,97,97,100,100,100,49,73,68,116,
|
||||
37,53,49,49,37,37,37,37,37,96,52,97,97,97,97,100,100,100,33,36,49,
|
||||
49,49,96,97,100,97,101,52,49,97,112,112,48,49,49,113,113,116,100,100,
|
||||
36,112,112,112,112,96,96,49,52,52,52,100,100,100,52,116,36,100,100,
|
||||
100,52,52,52,100,48,52,36,37,37,116,100,100,100,100,48,33,49,49,37,
|
||||
96,100,117,32,116,52,97,33,117,53,49,49,113,49,97,48,49,52,37,97,97,
|
||||
100,48,53,53,36,101,49,48,49,49,97,49,32,100,100,36,112,112,112,112,
|
||||
96,37,37,52,52,52,100,100,100,52,53,36,49,49,33,52,52,96,37,48,52,
|
||||
36,37,37,37,49,49,49,53,4,177,177,97,36,100,100,52,52,52,52,52,32,
|
||||
49,37,37,37,37,49,49,49,37,53,33,49,49,37,37,37,37,53,113,100,36,100,
|
||||
97,97,100,100,100,97,101,96,100,100,100,97,100,97,36,33,101,112,112,
|
||||
48,49,49,49,113,36,112,101,100,116,37,112,112,48,97,112,48,52,52,112,
|
||||
49,49,49,49,48,32,49,49,33,112,49,117,33,112,113,36,37,116,117,100,
|
||||
100,100,117,48,33,49,113,97,33,37,113,49,33,33,32,48,101,96,100,100,
|
||||
36,53,100,96,100,100,97,97,97,97,33,48,52,112,112,112,48,49,49,113,
|
||||
112,49,48,49,113,112,112,52,97,96,112,48,52,52,52,100,100,100,52,112,
|
||||
179,51,116,113,101,100,36,48,113,112,112,32,100,49,52,52,52,100,100,
|
||||
100,116,97,32,100,100,52,52,52,100,116,100,49,49,36,37,37,49,49,49,
|
||||
101,49,48,49,49,37,37,37,37,37,36,52,97,97,97,97,100,100,100,113,33,
|
||||
96,100,100,100,97,97,97,36,97,97,48,113,96,101,100,100,100,36,49,48,
|
||||
49,113,96,101,36,112,96,101,49,52,112,117,49,49,49,53,52,48,49,49,
|
||||
116,32,33,100,101,36,36,96,97,52,33,49,49,49,36,48,33,49,49,37,37,
|
||||
37,37,37,116,112,96,97,97,97,100,100,100,33,116,96,100,100,97,97,49,
|
||||
97,33,97,97,112,112,112,48,49,49,113,101,111,108,100,101,96,100,100,
|
||||
97,97,97,97,33,48,101,112,112,112,48,49,49,113,112,49,48,49,113,112,
|
||||
112,112,112,49,101,32,37,52,52,100,100,100,52,116,36,100,100,52,100,
|
||||
52,52,52,48,112,36,37,37,37,49,49,49,37,53,33,49,49,116,32,37,37,49,
|
||||
36,37,97,97,33,53,49,49,49,97,113,96,100,100,33,53,113,53,32,53,101,
|
||||
112,96,117,101,100,100,116,37,49,48,113,97,52,112,48,101,101,101,37,
|
||||
49,113,36,100,100,100,112,37,96,100,100,52,100,52,52,52,112,97,33,
|
||||
37,37,37,49,49,49,37,53,33,49,49,37,37,101,49,36,36,37,97,97,97,97,
|
||||
100,100,100,113,72,68,100,48,33,49,49,37,37,37,37,37,96,52,97,97,97,
|
||||
97,100,100,100,101,113,49,49,49,96,97,97,97,48,97,49,97,112,112,48,
|
||||
49,49,113,37,33,48,49,113,112,112,112,112,96,96,49,52,52,52,100,100,
|
||||
100,52,96,37,100,100,52,52,52,52,100,48,52,36,37,37,116,100,100,100,
|
||||
100,48,33,49,49,37,116,100,97,32,116,52,97,33,117,53,49,49,113,97,
|
||||
53,96,100,101,112,96,97,116,100,96,96,97,100,49,48,49,49,97,37,49,
|
||||
48,49,113,112,112,112,112,96,37,37,52,52,52,100,100,100,52,116,36,
|
||||
100,100,52,52,52,117,49,48,52,36,37,37,37,49,49,49,53,1,177,177,53,
|
||||
48,49,49,33,52,100,52,52,32,113,36,37,37,37,49,49,49,37,53,33,49,49,
|
||||
37,37,37,37,37,36,101,36,97,97,97,100,100,100,97,101,96,100,100,97,
|
||||
100,97,100,33,33,101,48,49,113,48,49,49,113,112,49,48,49,97,37,112,
|
||||
112,48,97,48,49,52,52,112,49,49,49,49,36,32,49,49,33,112,49,117,33,
|
||||
112,113,36,37,116,117,100,100,100,117,48,33,49,101,97,33,37,113,49,
|
||||
33,97,36,49,101,96,100,100,36,37,49,100,100,100,97,97,100,97,33,53,
|
||||
52,112,112,112,48,49,49,113,32,48,48,49,113,112,112,52,97,96,112,48,
|
||||
52,52,52,100,100,100,52,36,178,51,113,49,48,49,113,112,112,112,112,
|
||||
32,100,49,52,52,52,100,100,100,52,116,36,100,100,52,52,52,52,116,100,
|
||||
117,116,32,37,37,49,49,49,37,36,97,100,100,32,37,37,37,37,36,52,97,
|
||||
97,97,97,100,100,100,101,113,49,49,113,53,96,97,97,36,97,97,112,112,
|
||||
96,101,100,100,100,52,53,48,49,113,96,101,116,37,96,101,49,52,52,52,
|
||||
100,100,100,48,101,116,100,116,48,112,33,100,101,36,36,97,112,52,33,
|
||||
49,49,49,116,48,33,49,49,37,37,37,37,37,116,112,96,97,97,97,100,100,
|
||||
100,97,101,96,100,100,97,97,113,116,33,33,52,112,112,112,48,49,49,
|
||||
113,53,106,108,36,97,53,49,49,96,97,97,97,36,48,101,112,112,112,48,
|
||||
49,49,113,96,97,48,49,113,112,112,112,112,96,112,32,37,52,52,100,100,
|
||||
100,52,116,36,100,100,52,52,100,52,52,48,112,36,37,37,37,49,49,49,
|
||||
37,53,33,49,49,49,37,37,37,49,36,37,97,97,33,53,49,49,49,49,100,96,
|
||||
100,100,33,53,113,53,32,48,101,112,96,117,101,100,100,116,37,49,48,
|
||||
113,37,96,112,48,101,52,48,100,53,113,36,100,100,100,112,117,37,49,
|
||||
49,33,52,52,100,52,112,97,33,37,37,37,49,49,49,37,52,36,49,49,37,37,
|
||||
101,49,36,36,37,97,97,97,97,100,100,100,49,8,17,49,53,33,49,49,37,
|
||||
37,37,37,37,96,52,97,97,97,97,100,100,100,97,101,96,100,100,97,97,
|
||||
97,97,33,97,33,52,112,112,48,49,49,113,96,52,48,49,113,112,112,112,
|
||||
112,96,96,49,52,52,52,100,100,100,52,49,49,100,100,32,33,52,52,100,
|
||||
48,52,36,37,37,116,100,100,100,36,48,96,100,100,32,116,100,117,32,
|
||||
116,52,97,33,117,48,49,49,113,113,49,96,100,101,112,96,97,116,36,97,
|
||||
48,97,36,100,101,100,100,116,37,49,48,49,113,112,112,112,112,96,37,
|
||||
37,52,52,52,100,100,100,52,116,36,100,100,52,52,52,101,48,48,52,36,
|
||||
37,37,37,49,49,49,53,0,228,228,113,53,100,100,52,52,52,52,52,32,113,
|
||||
48,37,37,37,49,49,49,101,97,48,49,49,37,37,37,37,53,113,53,53,96,97,
|
||||
97,100,100,100,97,101,96,100,100,97,97,97,100,33,33,101,112,112,112,
|
||||
48,49,49,113,112,49,48,49,97,37,112,112,48,97,112,48,52,52,112,49,
|
||||
49,49,49,97,36,100,100,52,112,49,117,49,117,113,36,37,116,117,100,
|
||||
100,100,117,48,33,49,53,97,33,37,113,49,33,97,36,49,33,53,49,49,113,
|
||||
101,32,53,49,49,96,97,97,97,36,53,52,112,112,112,48,49,49,113,52,36,
|
||||
49,49,113,112,112,52,117,96,32,37,52,52,52,100,100,100,52,96,178,51,
|
||||
113,49,48,49,113,112,112,112,112,32,100,49,52,52,52,100,100,100,52,
|
||||
116,36,100,100,52,52,52,52,52,48,52,49,36,37,37,49,49,49,101,52,48,
|
||||
49,49,37,37,37,37,37,36,52,97,97,97,97,100,100,100,49,33,48,49,113,
|
||||
53,96,97,97,36,97,117,112,112,96,101,100,100,100,37,36,48,49,113,96,
|
||||
101,116,37,96,101,49,52,112,117,49,49,49,53,36,117,49,97,36,37,52,
|
||||
100,101,36,36,49,100,100,33,49,49,49,52,113,49,49,49,37,37,37,37,37,
|
||||
116,112,96,97,97,97,100,100,100,113,33,96,100,100,97,97,113,116,33,
|
||||
33,52,112,112,112,48,49,49,113,37,107,108,116,116,97,100,100,97,97,
|
||||
97,97,33,48,101,48,113,112,48,49,49,113,36,112,101,100,36,112,112,
|
||||
112,112,49,101,32,37,52,52,100,100,100,52,116,36,100,100,52,52,52,
|
||||
52,100,48,112,36,37,37,37,49,49,49,37,53,33,49,49,116,32,37,37,49,
|
||||
36,37,97,97,33,53,49,49,49,49,100,96,100,100,33,53,113,53,96,97,96,
|
||||
112,96,117,101,100,100,116,37,49,48,113,49,52,112,48,53,97,48,100,
|
||||
48,33,116,49,49,49,117,97,36,100,100,52,52,52,52,52,112,97,101,32,
|
||||
37,37,49,49,49,37,53,33,49,49,37,37,101,49,36,36,37,97,97,97,97,100,
|
||||
100,100,113,9,17,49,53,33,49,49,37,37,37,37,37,96,52,97,97,97,97,100,
|
||||
100,100,113,33,96,100,100,97,97,97,97,33,33,116,36,112,112,48,49,49,
|
||||
113,113,113,48,49,113,112,112,112,112,112,53,48,52,52,52,100,100,100,
|
||||
116,49,116,49,49,117,49,33,52,100,48,52,36,37,37,116,100,100,100,116,
|
||||
33,116,100,100,32,116,100,117,32,37,33,97,33,117,53,49,49,113,33,100,
|
||||
96,100,101,112,96,100,116,100,96,48,97,100,49,48,49,49,97,37,49,48,
|
||||
49,113,112,112,112,112,96,37,37,52,52,52,100,100,100,116,117,36,100,
|
||||
100,52,52,52,101,48,48,52,36,37,37,37,49,49,49,53,5,228,228,113,33,
|
||||
49,49,33,52,52,52,52,32,113,36,37,49,37,49,49,49,37,53,33,49,49,37,
|
||||
37,37,37,53,113,100,36,97,97,97,100,100,100,97,101,96,100,100,97,97,
|
||||
97,97,33,33,113,112,112,112,48,49,49,113,112,49,48,49,97,37,112,112,
|
||||
48,97,112,48,52,100,32,49,49,49,49,97,36,100,100,52,112,49,117,33,
|
||||
112,113,36,37,116,117,100,100,100,117,49,117,100,48,97,33,37,113,49,
|
||||
33,97,36,49,101,96,100,100,36,117,36,96,100,100,97,97,97,97,33,53,
|
||||
52,48,113,112,48,49,49,113,32,101,101,100,36,112,112,52,97,96,117,
|
||||
48,52,52,52,100,100,100,52,116,231,102,36,49,48,49,113,112,112,112,
|
||||
112,32,100,49,52,52,52,100,100,100,52,117,112,49,49,33,52,52,52,116,
|
||||
100,49,49,36,37,37,49,49,49,53,36,116,100,100,32,37,37,37,37,36,100,
|
||||
97,97,97,97,100,100,100,37,101,101,100,36,53,96,97,97,36,97,97,112,
|
||||
112,96,101,100,100,100,117,112,49,49,113,96,101,116,37,96,101,49,52,
|
||||
112,117,49,49,49,117,100,113,49,97,36,37,52,100,101,36,36,49,100,52,
|
||||
33,49,49,49,116,48,33,49,49,37,37,37,37,37,116,112,96,97,97,97,100,
|
||||
100,100,97,101,96,100,100,97,97,113,36,33,117,97,112,112,112,48,49,
|
||||
49,113,117,63,57,97,52,48,49,49,96,97,97,97,33,48,101,112,112,48,49,
|
||||
49,49,113,112,49,48,49,113,112,112,112,112,96,112,96,52,52,52,100,
|
||||
100,100,52,116,36,100,100,52,52,52,52,52,116,37,36,37,37,37,49,49,
|
||||
49,37,53,33,49,49,116,100,32,37,49,36,37,97,97,97,97,100,100,100,100,
|
||||
101,96,100,100,33,53,113,53,96,97,96,112,96,117,101,100,100,116,37,
|
||||
49,48,113,49,52,112,48,101,49,48,100,48,113,36,100,100,100,112,52,
|
||||
48,49,49,33,52,52,52,52,112,97,33,37,49,37,49,49,49,101,100,48,49,
|
||||
49,37,37,101,49,36,36,37,97,97,97,97,100,100,100,49,93,68,100,48,33,
|
||||
49,49,37,37,37,37,37,96,52,97,97,97,97,100,100,100,97,101,96,100,100,
|
||||
97,97,97,97,101,52,49,97,112,112,48,49,49,113,33,117,49,49,113,112,
|
||||
112,112,112,112,53,33,52,52,52,100,100,100,116,49,48,49,49,117,33,
|
||||
52,52,100,48,52,36,37,37,116,100,100,100,116,53,117,100,100,32,116,
|
||||
100,117,32,116,52,100,33,117,53,49,49,113,101,53,97,100,101,112,96,
|
||||
97,116,100,96,48,97,112,49,48,49,49,97,37,49,48,49,113,112,112,112,
|
||||
112,96,37,37,52,52,52,100,100,100,52,116,36,100,100,52,52,52,101,48,
|
||||
96,52,36,37,37,37,49,49,49,53,84,177,177,53,53,49,49,33,52,52,52,52,
|
||||
32,113,36,37,37,37,49,49,49,49,52,48,49,49,37,37,37,37,37,36,37,100,
|
||||
97,97,97,100,100,100,97,101,96,100,100,97,97,97,97,33,33,101,112,112,
|
||||
112,48,49,49,113,112,49,48,49,97,101,36,112,48,97,112,48,52,52,52,
|
||||
100,100,100,100,116,36,100,100,52,112,49,117,33,112,113,36,37,116,
|
||||
117,100,100,100,117,48,33,49,53,97,33,37,113,49,33,97,36,49,101,96,
|
||||
100,100,36,117,100,48,49,49,96,97,97,97,33,53,52,112,112,48,49,49,
|
||||
49,113,52,100,48,49,113,112,112,52,97,96,48,49,52,52,52,100,100,100,
|
||||
52,48,178,51,113,49,48,49,113,112,112,112,112,32,100,49,52,52,52,100,
|
||||
100,100,52,49,49,100,100,52,52,52,52,116,113,97,112,33,37,37,49,49,
|
||||
49,53,32,117,100,100,32,37,37,37,37,36,52,100,97,97,97,100,100,100,
|
||||
48,48,96,100,36,53,96,97,97,36,97,97,112,112,96,101,100,100,100,117,
|
||||
36,48,49,113,96,101,116,37,96,101,49,52,112,117,49,49,49,117,97,36,
|
||||
100,116,36,37,52,100,101,36,36,49,36,53,33,49,49,49,116,48,33,49,49,
|
||||
37,37,37,37,37,116,112,96,97,97,97,100,100,100,33,117,53,49,49,96,
|
||||
97,113,36,33,97,97,112,112,112,48,49,49,113,101,106,108,100,101,96,
|
||||
100,100,97,97,97,97,33,48,101,112,112,112,48,49,49,113,112,49,48,49,
|
||||
113,112,112,112,112,49,101,100,48,52,52,100,100,100,52,116,36,100,
|
||||
100,52,52,52,52,52,48,112,36,37,37,37,49,49,49,37,53,33,49,49,116,
|
||||
32,49,37,49,117,36,97,97,33,53,49,49,49,49,100,96,100,100,33,53,113,
|
||||
53,32,53,113,112,96,117,101,100,100,116,117,33,49,113,49,52,112,48,
|
||||
53,49,48,100,48,113,36,100,100,100,112,52,116,49,49,33,52,52,52,52,
|
||||
112,97,33,37,37,37,49,49,49,49,53,33,49,49,37,37,101,49,36,48,37,97,
|
||||
97,97,97,100,100,100,113,92,68,100,48,33,49,49,37,37,37,37,37,96,52,
|
||||
97,97,97,97,100,100,100,101,33,49,49,49,96,97,97,97,101,52,49,97,112,
|
||||
112,48,49,49,113,36,100,101,100,36,112,112,112,112,96,96,49,52,52,
|
||||
52,100,100,100,116,48,112,49,49,117,33,52,52,100,48,52,36,37,37,116,
|
||||
100,100,100,52,97,117,100,100,32,116,100,117,32,116,100,97,33,117,
|
||||
53,49,49,113,117,117,53,49,100,112,96,97,116,100,96,48,97,100,49,48,
|
||||
49,49,97,37,49,48,49,113,112,112,112,112,96,37,37,52,52,52,100,100,
|
||||
100,52,113,113,49,49,33,52,52,101,48,48,52,36,37,37,37,49,49,49,53,
|
||||
81,177,177,97,36,100,100,52,52,52,52,52,32,113,36,37,37,37,49,49,49,
|
||||
37,53,33,49,49,37,37,37,37,53,113,100,48,97,97,97,100,100,100,97,101,
|
||||
96,100,100,97,97,97,97,33,33,101,48,113,112,48,49,49,113,112,49,48,
|
||||
49,97,37,48,113,48,113,101,48,52,52,112,49,49,49,49,97,36,100,100,
|
||||
52,112,49,117,33,112,113,36,37,116,117,100,100,100,117,48,33,49,53,
|
||||
97,33,37,113,49,33,113,113,96,101,96,100,100,36,53,100,96,100,100,
|
||||
97,97,97,97,33,53,52,112,112,112,48,49,49,113,112,49,48,49,113,112,
|
||||
112,52,33,97,112,96,52,52,52,100,100,100,52,100,227,102,36,49,48,49,
|
||||
113,112,112,112,112,32,100,49,52,52,52,100,100,100,52,112,117,49,49,
|
||||
33,52,52,52,116,100,49,113,37,37,37,49,49,49,101,100,48,49,49,37,37,
|
||||
37,37,37,36,52,97,97,97,97,100,100,100,37,116,101,100,36,53,96,97,
|
||||
97,100,53,97,112,112,96,101,100,100,100,33,49,48,49,113,96,101,116,
|
||||
37,96,101,49,100,112,117,49,49,49,117,36,52,100,116,36,37,52,100,101,
|
||||
36,36,49,100,96,116,100,100,100,117,48,33,49,49,37,37,37,37,37,116,
|
||||
112,96,97,97,97,100,100,100,49,37,100,100,100,97,97,113,36,33,97,97,
|
||||
112,112,112,48,49,49,113,53,47,57,49,100,96,100,100,97,97,97,97,33,
|
||||
48,101,112,112,112,48,49,49,113,112,49,48,49,113,112,112,112,112,113,
|
||||
112,36,49,52,52,100,100,100,52,116,36,100,100,52,52,52,52,52,48,112,
|
||||
36,37,49,37,49,49,49,37,53,33,49,49,116,32,49,37,49,36,37,97,97,33,
|
||||
53,49,49,49,113,32,100,100,100,33,53,113,53,32,53,101,112,96,117,101,
|
||||
100,100,36,112,49,48,113,49,52,112,48,53,49,48,100,48,113,36,100,100,
|
||||
100,112,97,36,100,100,52,52,52,52,52,112,97,33,37,37,37,49,49,49,37,
|
||||
53,33,49,49,37,37,101,49,36,36,37,97,100,97,97,100,100,100,49,28,68,
|
||||
100,48,33,49,49,37,37,37,37,37,96,52,97,97,97,97,100,100,100,49,36,
|
||||
48,49,49,96,97,97,97,101,52,49,117,112,112,48,49,49,113,52,36,49,49,
|
||||
113,112,112,112,112,96,96,49,52,52,52,100,100,100,116,117,36,100,100,
|
||||
112,33,52,52,100,48,52,36,37,37,116,100,100,100,100,48,33,49,49,37,
|
||||
116,100,117,32,116,52,97,33,117,53,49,49,113,37,113,101,100,101,112,
|
||||
96,97,116,100,96,48,97,100,52,48,49,49,97,37,49,48,49,113,112,112,
|
||||
112,112,96,37,37,52,52,52,100,100,100,52,48,37,100,100,52,52,52,101,
|
||||
48,48,52,36,37,37,37,49,49,49,53,80,176,177,97,36,100,100,52,52,52,
|
||||
52,52,32,113,36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,37,53,113,
|
||||
100,36,97,97,97,100,100,100,97,101,96,100,100,97,97,97,97,33,33,101,
|
||||
112,112,48,49,49,49,113,116,32,48,49,97,37,112,48,49,97,112,48,52,
|
||||
52,112,49,49,49,49,117,96,100,100,52,112,49,117,33,112,113,36,49,116,
|
||||
117,100,100,100,32,53,33,49,53,97,33,37,113,49,33,97,36,49,101,96,
|
||||
100,100,36,53,100,96,100,100,97,97,97,97,33,53,52,112,112,112,48,49,
|
||||
49,113,112,49,48,49,113,112,112,52,97,96,112,48,52,100,52,100,100,
|
||||
100,52,32,226,102,36,49,48,49,113,112,112,112,112,32,100,49,52,52,
|
||||
52,100,100,100,116,116,52,100,100,52,52,52,52,116,100,113,100,33,37,
|
||||
37,49,49,49,37,53,33,49,49,37,37,37,37,37,36,52,97,97,97,97,100,100,
|
||||
100,33,36,49,49,113,53,96,97,97,36,97,97,112,112,96,101,100,100,100,
|
||||
36,49,48,49,113,96,101,116,37,96,101,49,52,112,117,49,49,49,117,117,
|
||||
36,100,116,36,37,52,100,101,36,36,49,100,116,116,100,100,100,117,48,
|
||||
33,49,49,37,37,37,37,37,116,112,96,97,97,97,100,100,100,113,36,100,
|
||||
100,100,97,97,113,36,33,97,97,112,112,112,48,49,49,113,37,42,57,49,
|
||||
100,96,100,100,97,97,97,97,33,48,101,112,112,112,48,49,49,113,112,
|
||||
49,48,49,113,112,112,112,112,49,101,100,48,52,52,100,100,100,52,116,
|
||||
36,100,100,52,52,52,52,52,48,112,36,37,37,37,49,49,49,37,53,33,49,
|
||||
49,116,32,37,37,49,36,37,100,97,33,53,49,49,49,33,96,53,49,49,32,53,
|
||||
113,53,32,53,101,112,48,97,101,100,100,116,37,49,48,113,49,52,112,
|
||||
48,53,49,48,100,48,113,36,100,100,100,112,97,36,100,100,52,52,52,52,
|
||||
52,112,97,33,37,37,37,49,49,49,37,53,33,49,49,37,37,101,49,36,36,37,
|
||||
97,97,97,100,100,100,100,113,29,68,100,48,33,49,49,37,37,37,37,37,
|
||||
96,52,97,97,97,97,100,100,100,37,33,53,49,49,96,97,97,97,101,52,49,
|
||||
97,112,112,48,49,49,113,112,49,48,49,113,112,112,112,112,96,96,49,
|
||||
52,52,52,100,100,100,52,33,33,49,49,117,33,52,52,100,48,52,36,37,37,
|
||||
116,100,100,100,52,49,32,49,49,37,116,100,117,32,116,52,97,33,117,
|
||||
53,49,49,113,53,100,96,100,101,112,96,97,116,100,96,48,97,100,97,48,
|
||||
49,49,97,37,49,48,49,113,112,112,112,112,96,37,37,52,52,52,100,100,
|
||||
100,116,96,52,100,100,52,52,52,101,48,48,52,36,37,37,37,49,49,49,53,
|
||||
85,176,177,97,36,100,100,52,52,52,52,52,32,113,36,37,37,37,49,49,49,
|
||||
37,53,33,49,49,37,37,37,37,53,113,52,113,96,97,97,100,100,100,97,101,
|
||||
96,100,100,97,97,97,97,33,33,101,112,112,112,48,49,49,113,112,49,48,
|
||||
49,97,37,112,112,48,97,112,96,52,52,112,49,49,49,49,97,36,100,100,
|
||||
52,112,49,117,33,112,113,36,37,49,116,100,100,100,53,33,96,100,48,
|
||||
97,33,37,113,49,33,97,36,49,101,96,100,100,36,53,100,96,100,100,97,
|
||||
97,97,97,33,53,52,112,112,112,48,49,49,113,112,49,48,49,113,112,112,
|
||||
52,97,112,101,48,52,52,52,100,100,100,52,52,227,102,36,49,48,49,113,
|
||||
112,112,112,112,32,100,49,52,52,52,100,100,100,116,96,117,100,100,
|
||||
52,52,52,52,116,100,49,49,36,37,37,49,49,49,37,53,33,49,49,37,37,37,
|
||||
37,37,36,52,97,97,97,97,100,100,100,113,49,48,49,113,53,96,97,97,36,
|
||||
97,97,112,112,96,101,100,100,100,96,100,48,49,113,96,101,116,37,96,
|
||||
101,49,52,32,117,49,49,49,53,100,32,100,116,36,37,52,100,101,36,36,
|
||||
49,100,52,36,49,49,49,37,53,33,49,49,37,37,37,37,37,116,112,96,97,
|
||||
97,97,100,100,100,53,112,53,49,49,96,97,113,36,33,97,97,112,112,112,
|
||||
48,49,49,113,117,46,57,49,100,96,100,100,97,97,97,97,33,48,101,112,
|
||||
112,112,48,49,49,113,112,49,48,49,113,112,112,112,112,49,101,49,37,
|
||||
52,52,100,100,100,52,116,36,100,100,52,52,52,52,52,48,112,36,37,37,
|
||||
37,49,49,49,37,53,33,49,49,116,32,37,37,49,36,37,100,97,33,53,49,49,
|
||||
49,49,100,96,100,100,33,53,113,53,32,53,101,112,96,117,101,100,100,
|
||||
116,37,49,48,113,49,52,112,48,53,49,48,100,48,113,116,100,100,100,
|
||||
32,97,36,100,100,52,52,52,52,52,112,97,33,37,37,37,49,49,49,37,53,
|
||||
33,49,49,37,37,101,49,36,117,36,97,97,97,97,100,100,100,49,25,68,100,
|
||||
48,33,49,49,37,37,37,37,37,96,52,97,97,97,97,100,100,100,37,96,53,
|
||||
49,49,96,97,97,97,101,52,49,97,48,113,48,49,49,113,112,49,48,49,113,
|
||||
112,112,112,112,96,96,49,52,52,52,100,100,100,52,116,36,100,100,112,
|
||||
33,52,52,100,48,52,36,37,37,116,100,100,100,100,117,117,100,100,32,
|
||||
116,100,117,32,116,52,97,33,117,48,49,49,113,48,100,96,100,101,112,
|
||||
96,97,116,100,96,48,97,100,113,49,49,49,97,37,49,48,49,113,112,112,
|
||||
112,112,96,37,37,52,52,52,100,100,100,116,117,36,100,100,52,52,52,
|
||||
101,48,48,52,36,37,37,37,49,49,49,97,65,176,177,97,36,100,100,52,52,
|
||||
52,52,52,32,113,36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,37,53,
|
||||
113,100,36,97,97,97,100,100,100,97,101,96,100,100,97,97,97,97,33,33,
|
||||
101,112,112,112,48,49,49,113,96,33,49,49,97,37,112,112,48,97,112,48,
|
||||
100,52,112,49,49,49,49,97,36,100,100,52,112,49,117,33,112,113,36,37,
|
||||
116,32,49,49,49,101,48,37,49,53,97,33,37,113,49,33,97,36,49,101,96,
|
||||
100,100,36,53,100,96,100,100,97,97,97,97,33,53,52,112,112,112,48,49,
|
||||
49,113,32,113,101,100,36,112,112,52,97,96,112,48,52,52,52,100,100,
|
||||
100,52,112,226,102,36,49,48,49,113,112,112,112,112,32,100,49,52,52,
|
||||
52,100,100,100,52,116,36,100,100,52,52,52,52,116,52,52,49,36,37,37,
|
||||
49,49,49,37,53,33,49,49,37,37,37,37,37,36,52,97,97,97,97,100,100,100,
|
||||
113,97,48,49,113,53,96,97,97,36,97,97,112,48,97,101,100,100,100,112,
|
||||
101,48,49,113,96,101,116,37,96,101,49,52,112,117,49,49,49,33,116,36,
|
||||
100,116,36,37,52,100,101,36,36,49,100,52,33,49,49,49,37,53,33,49,49,
|
||||
37,37,37,37,37,116,112,96,97,97,97,100,100,100,97,101,96,100,100,97,
|
||||
97,113,36,33,97,97,112,112,112,48,49,49,113,101,43,57,49,100,96,100,
|
||||
100,97,97,97,97,33,48,101,112,112,112,48,49,49,113,52,100,48,49,113,
|
||||
112,112,112,112,49,37,101,48,52,52,100,100,100,52,116,36,100,100,52,
|
||||
52,52,52,52,48,112,36,37,37,37,49,49,49,37,53,33,49,49,116,32,37,37,
|
||||
49,36,37,97,97,97,100,100,100,100,100,101,96,100,100,33,53,113,53,
|
||||
32,53,101,112,96,117,101,100,100,116,97,32,100,36,49,52,112,48,53,
|
||||
49,48,100,48,113,36,100,100,100,112,97,36,100,100,52,52,52,52,52,112,
|
||||
97,33,37,37,37,49,49,49,37,53,33,49,49,37,37,101,49,36,36,37,97,97,
|
||||
97,97,100,100,100,113,24,68,100,48,33,49,49,37,37,37,37,37,96,52,97,
|
||||
97,97,97,100,100,100,33,97,48,49,49,96,97,97,97,101,52,49,97,112,112,
|
||||
48,49,49,113,112,49,48,49,113,112,112,112,112,96,96,49,52,52,52,100,
|
||||
100,100,52,116,36,100,100,112,33,52,52,100,48,52,36,37,37,116,100,
|
||||
100,100,100,33,48,49,49,37,116,100,117,32,116,52,97,33,117,53,49,49,
|
||||
113,48,100,96,100,101,112,96,97,116,100,96,48,97,100,49,48,49,49,33,
|
||||
36,49,48,49,113,112,112,112,112,96,37,37,52,52,52,100,100,100,52,116,
|
||||
36,100,100,52,52,52,101,48,48,52,36,37,37,37,49,49,49,53,65,176,177,
|
||||
97,36,100,100,52,52,52,52,52,32,113,36,37,37,37,49,49,49,37,53,33,
|
||||
49,49,37,37,37,37,53,113,100,36,97,97,100,100,100,100,100,101,96,100,
|
||||
100,97,97,97,97,33,33,101,112,112,112,48,49,49,113,112,49,48,49,97,
|
||||
37,112,112,48,97,112,48,52,52,112,49,49,49,49,97,36,100,100,52,112,
|
||||
49,117,33,112,113,36,37,116,117,100,100,100,53,53,96,100,48,97,33,
|
||||
37,113,49,33,97,36,49,101,96,100,100,36,53,100,96,100,100,97,97,97,
|
||||
97,33,53,52,112,112,112,48,49,49,113,112,49,48,49,113,112,112,52,97,
|
||||
96,112,48,52,52,52,100,100,100,52,36,183,51,49,49,49,49,113,112,112,
|
||||
112,112,48,49,33,52,52,52,36,48,49,49,49,49,49,49,33,52,52,52,52,49,
|
||||
100,112,37,37,37,33,100,100,100,100,100,100,100,32,37,37,37,37,49,
|
||||
49,96,97,97,97,32,49,49,49,49,49,49,49,96,97,97,97,100,100,36,112,
|
||||
112,112,48,49,49,49,49,49,49,49,113,112,48,113,112,48,49,33,52,52,
|
||||
52,36,48,49,49,49,49,49,49,33,49,52,100,113,53,100,112,48,112,37,33,
|
||||
100,100,100,100,100,100,100,32,37,37,37,37,37,49,96,97,97,97,32,49,
|
||||
49,49,49,49,49,49,96,97,49,117,97,97,36,112,112,112,48,96,100,100,
|
||||
97,127,108,100,100,100,100,100,117,32,116,117,117,100,36,117,117,117,
|
||||
117,53,49,49,49,49,49,49,113,117,117,117,117,53,49,33,116,37,48,49,
|
||||
49,49,49,49,49,49,49,33,52,52,52,52,100,100,52,32,37,37,117,49,49,
|
||||
49,49,49,49,49,37,33,100,100,100,32,49,116,97,32,37,49,49,49,49,49,
|
||||
49,49,49,49,96,100,97,100,97,36,53,32,112,112,48,49,49,49,49,49,49,
|
||||
49,49,113,53,49,113,48,49,33,36,112,112,48,49,49,49,49,49,49,97,101,
|
||||
36,112,112,48,49,33,52,52,52,52,100,100,100,100,100,100,100,52,52,
|
||||
52,52,100,100,100,100,100,100,100,117,100,100,52,88,17,49,49,49,49,
|
||||
49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,
|
||||
49,49,49,49,33,100,100,36,117,53,49,49,49,49,49,49,113,112,112,112,
|
||||
112,48,49,49,33,52,52,100,100,100,100,100,100,100,100,100,100,100,
|
||||
113,117,101,100,36,53,49,49,117,49,49,49,49,49,49,49,113,48,116,100,
|
||||
112,49,49,49,33,100,100,100,100,100,100,100,100,100,100,117,117,36,
|
||||
53,116,100,36,37,100,100,100,100,100,100,100,100,100,100,100,36,53,
|
||||
49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,97,101,
|
||||
100,112,117,117,117,49,49,49,97,85,229,228,100,100,100,100,100,100,
|
||||
100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,
|
||||
100,100,100,100,100,100,100,52,100,36,33,116,100,100,100,100,100,100,
|
||||
100,37,37,37,37,37,100,100,36,97,97,33,49,49,49,49,49,49,49,49,37,
|
||||
37,49,97,33,49,49,96,97,97,49,97,100,100,100,100,100,100,100,100,49,
|
||||
100,97,100,100,100,36,112,112,112,48,49,49,49,49,49,49,49,49,49,37,
|
||||
113,48,49,49,33,52,52,52,100,100,100,100,100,100,100,100,97,100,100,
|
||||
100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,32,49,
|
||||
37,101,53,49,53,96,117,117,101,100,100,100,96,183,51,49,49,49,49,97,
|
||||
117,117,117,117,101,100,112,117,117,117,117,49,49,49,49,49,49,49,117,
|
||||
117,117,117,117,49,49,116,117,117,112,37,49,49,49,49,49,49,49,48,49,
|
||||
49,49,49,100,36,117,100,100,100,53,49,49,49,49,49,49,113,117,117,117,
|
||||
48,96,100,116,117,117,117,37,48,49,49,49,49,49,49,97,117,101,116,53,
|
||||
97,100,112,117,117,117,117,49,49,49,49,49,49,49,33,52,112,49,33,100,
|
||||
100,32,116,117,117,117,100,100,100,100,100,100,100,117,100,117,117,
|
||||
117,100,36,117,117,117,117,53,49,49,49,49,49,49,113,117,117,117,53,
|
||||
96,100,36,117,112,112,96,101,100,100,49,127,76,100,28,102,97,110,108,
|
||||
52,33,48,49,49,96,97,97,97,97,100,96,112,112,112,48,49,49,113,117,
|
||||
49,48,49,113,112,112,112,112,49,101,100,48,52,52,100,100,100,116,117,
|
||||
36,100,100,52,52,52,52,52,48,112,36,37,37,37,49,49,49,37,53,33,49,
|
||||
49,116,32,37,37,49,36,37,97,97,33,53,49,49,49,49,100,96,100,100,36,
|
||||
53,113,53,32,53,101,112,96,37,48,49,49,97,53,113,101,36,49,52,112,
|
||||
48,53,113,49,100,48,113,36,100,100,100,48,117,48,49,49,33,52,52,52,
|
||||
52,112,97,33,37,37,37,49,49,49,37,53,33,49,49,37,37,101,49,36,36,37,
|
||||
97,97,97,97,100,100,100,117,76,102,32,59,57,49,100,96,100,100,97,97,
|
||||
97,97,33,48,101,112,112,112,48,49,49,113,32,101,101,100,36,112,112,
|
||||
112,112,97,96,100,48,52,52,100,100,100,52,96,113,49,49,33,52,52,52,
|
||||
52,112,113,36,37,37,37,49,49,49,37,116,117,100,100,117,32,37,37,49,
|
||||
116,37,97,97,33,53,49,49,49,113,37,97,100,100,33,53,113,53,32,53,101,
|
||||
112,48,97,101,100,100,116,37,49,48,113,49,52,112,48,53,49,48,100,48,
|
||||
113,36,100,100,100,112,97,36,100,100,52,52,52,52,52,52,116,33,37,37,
|
||||
37,49,49,49,37,52,48,49,49,37,37,101,49,36,36,117,97,97,97,97,100,
|
||||
100,100,49,76,102,117,110,108,100,101,96,100,100,100,97,97,97,33,48,
|
||||
101,112,112,112,48,49,49,113,112,49,48,49,113,112,112,112,112,97,96,
|
||||
100,48,52,52,100,100,100,52,116,36,100,100,52,52,52,52,52,48,112,36,
|
||||
37,37,37,49,49,49,101,33,96,100,100,117,32,37,37,49,48,37,97,97,33,
|
||||
53,49,49,49,49,100,96,100,100,36,53,113,53,32,53,101,112,48,97,101,
|
||||
100,100,116,97,32,100,36,49,52,112,48,53,113,49,100,48,113,36,100,
|
||||
100,100,48,117,116,49,49,49,33,52,52,52,112,97,33,37,37,37,49,49,49,
|
||||
37,53,33,49,49,49,49,101,49,36,36,37,97,97,97,97,100,100,100,37,76,
|
||||
102,52,110,108,52,101,101,100,100,97,97,97,100,33,48,101,112,112,112,
|
||||
48,49,49,113,100,36,49,49,113,112,112,112,112,49,101,100,48,52,52,
|
||||
100,100,100,52,49,97,100,100,52,52,52,52,52,112,113,36,37,37,37,49,
|
||||
49,49,37,53,33,49,49,116,32,37,37,49,36,37,97,97,33,53,49,49,49,97,
|
||||
48,100,100,100,33,53,113,53,32,53,101,112,96,37,48,49,49,97,37,49,
|
||||
48,113,49,52,112,48,53,49,48,100,48,113,36,100,100,100,112,97,36,100,
|
||||
100,52,52,52,52,52,112,97,33,37,37,37,49,49,49,101,37,117,100,100,
|
||||
32,37,101,49,36,36,37,97,97,97,97,100,100,100,33,24,51,48,110,108,
|
||||
52,96,48,49,49,49,96,97,97,33,48,101,112,112,112,48,49,49,113,32,53,
|
||||
48,49,113,112,112,112,112,100,101,48,52,52,52,100,100,100,52,49,49,
|
||||
100,100,52,52,52,52,52,112,113,36,37,37,37,49,49,49,37,53,33,49,49,
|
||||
116,32,37,37,49,36,37,97,97,33,53,49,49,49,97,33,96,100,100,36,53,
|
||||
113,53,32,53,101,112,48,113,48,49,49,97,48,100,100,36,49,52,112,48,
|
||||
97,100,101,53,53,112,36,100,100,100,112,32,32,100,100,52,52,52,52,
|
||||
52,112,113,36,37,37,37,49,49,49,37,53,33,49,49,49,49,101,49,36,36,
|
||||
37,97,97,97,97,100,100,100,53,24,51,117,59,57,49,100,96,100,100,97,
|
||||
97,97,97,33,48,101,112,112,112,48,49,49,113,112,49,48,49,113,112,112,
|
||||
112,112,49,101,100,48,52,52,100,100,100,52,116,36,100,100,52,52,52,
|
||||
52,52,48,112,36,37,37,37,49,49,49,37,96,100,100,100,117,32,37,37,49,
|
||||
36,112,96,97,33,53,49,49,49,49,100,96,100,100,33,53,113,53,32,53,101,
|
||||
112,96,117,101,100,100,116,37,49,48,49,100,49,112,48,53,49,48,100,
|
||||
48,113,36,100,100,100,112,97,36,100,100,52,52,52,52,52,112,97,33,37,
|
||||
37,37,49,49,49,101,101,101,100,100,32,37,101,49,36,36,37,97,97,97,
|
||||
97,100,100,100,113,77,102,37,110,108,48,48,96,100,100,97,97,97,97,
|
||||
33,48,113,112,112,112,48,49,49,113,116,36,100,100,100,36,112,112,112,
|
||||
49,101,100,48,52,52,100,100,100,52,116,36,100,100,52,52,52,52,52,48,
|
||||
112,36,37,37,37,49,49,49,37,53,33,49,49,116,32,37,37,49,36,37,97,97,
|
||||
33,53,49,49,49,49,100,96,100,100,97,97,36,53,32,53,101,112,96,117,
|
||||
101,100,100,116,113,48,100,100,101,49,112,48,53,49,48,52,53,112,36,
|
||||
100,100,100,112,116,49,100,100,52,52,52,52,52,112,97,33,37,37,37,49,
|
||||
49,49,101,100,36,49,49,37,37,49,112,33,116,112,96,97,97,97,100,100,
|
||||
100,101,77,102,36,58,57,49,100,96,100,100,97,97,97,97,33,48,101,112,
|
||||
112,112,48,49,49,113,112,49,48,49,113,112,112,112,112,49,101,100,96,
|
||||
52,52,100,100,100,52,37,49,100,100,52,52,52,52,52,96,112,36,37,37,
|
||||
37,49,49,49,37,52,36,49,49,49,37,37,37,49,36,37,97,97,33,53,49,49,
|
||||
49,33,112,96,100,100,33,53,113,53,32,53,101,112,96,117,101,100,100,
|
||||
116,37,49,48,113,52,96,37,48,117,100,101,113,48,113,36,100,100,100,
|
||||
112,97,36,100,100,52,52,52,52,52,112,49,37,37,37,37,49,49,49,37,53,
|
||||
33,49,49,37,37,101,49,36,36,37,97,97,97,97,100,100,100,97,73,102,33,
|
||||
58,57,117,32,53,49,49,96,97,97,97,33,48,113,112,112,112,48,49,49,113,
|
||||
36,36,100,100,36,48,113,112,112,49,101,100,48,52,52,100,100,100,52,
|
||||
113,113,49,49,33,52,52,52,52,48,112,36,37,37,37,49,49,49,37,53,33,
|
||||
49,49,49,37,37,37,49,36,37,97,97,33,53,49,49,49,53,116,49,49,49,96,
|
||||
97,100,97,33,53,101,112,96,117,101,100,100,116,112,112,101,36,49,52,
|
||||
112,48,33,116,101,101,96,113,36,100,100,100,112,97,36,100,100,52,52,
|
||||
52,52,52,112,97,33,37,37,37,49,49,49,37,96,97,100,100,32,37,37,53,
|
||||
36,36,37,97,97,97,97,100,100,100,117,73,102,96,58,57,49,100,96,100,
|
||||
100,97,97,97,97,33,48,101,112,112,112,48,49,49,113,112,49,48,49,113,
|
||||
112,112,112,112,49,101,100,96,52,52,100,100,100,52,116,36,100,100,
|
||||
100,52,52,52,52,48,112,36,37,37,37,49,49,49,101,97,48,49,49,116,32,
|
||||
37,37,49,36,37,97,97,33,53,49,49,49,49,100,96,100,100,33,48,113,48,
|
||||
32,53,101,112,96,117,101,100,100,116,37,49,48,49,37,37,113,48,53,49,
|
||||
48,32,32,113,36,100,100,100,112,117,96,100,100,52,52,52,52,52,32,97,
|
||||
33,37,37,37,49,49,49,37,53,33,49,49,37,37,101,49,36,36,37,97,97,97,
|
||||
97,100,100,100,49,73,102,53,58,57,117,97,101,100,100,97,97,97,97,33,
|
||||
48,101,112,112,112,48,49,49,113,32,97,100,100,36,112,48,113,112,49,
|
||||
101,100,48,52,52,100,100,100,116,52,53,49,49,33,52,52,52,52,48,112,
|
||||
36,37,37,37,49,49,49,37,53,33,49,49,49,37,37,37,49,36,37,97,97,33,
|
||||
53,49,49,49,49,100,96,100,100,33,48,113,53,32,53,101,112,96,117,101,
|
||||
100,100,116,100,48,100,36,101,97,112,48,49,100,101,37,97,113,36,100,
|
||||
100,100,112,36,32,49,49,33,52,52,52,52,112,97,33,37,37,37,49,49,49,
|
||||
101,37,97,100,100,32,37,37,112,33,36,37,97,97,97,97,100,100,100,37,
|
||||
73,102,116,111,108,100,101,96,100,100,97,97,97,97,33,48,113,112,112,
|
||||
112,48,49,49,113,112,49,48,49,113,112,112,112,112,49,101,100,96,52,
|
||||
52,100,100,100,52,116,36,100,100,100,52,100,52,100,48,112,36,37,37,
|
||||
49,49,49,49,101,32,117,100,100,117,32,37,37,49,36,37,97,97,33,53,49,
|
||||
49,49,33,33,48,49,49,32,53,113,53,32,53,101,112,96,117,101,100,100,
|
||||
116,37,49,48,49,53,52,112,48,53,49,48,32,32,113,36,100,100,100,112,
|
||||
97,36,100,100,52,52,52,52,52,32,97,33,37,37,37,49,49,49,37,53,33,49,
|
||||
49,37,37,101,49,36,36,37,97,97,97,97,100,100,100,33,29,51,112,111,
|
||||
108,112,101,53,49,49,96,100,97,97,33,48,101,112,112,112,48,49,49,113,
|
||||
37,33,48,49,113,112,112,48,113,49,101,100,48,52,52,100,100,100,52,
|
||||
101,96,100,100,52,52,52,52,52,48,112,36,37,37,37,49,49,49,101,37,32,
|
||||
49,49,49,37,37,37,49,36,37,97,100,33,53,49,49,49,49,100,96,100,100,
|
||||
33,53,49,96,33,53,101,112,96,117,101,100,100,116,112,96,100,100,112,
|
||||
33,36,48,53,49,48,32,37,113,36,100,100,100,48,96,36,100,100,52,52,
|
||||
52,52,52,112,97,33,37,37,37,49,49,49,37,112,33,49,49,37,37,101,36,
|
||||
37,36,37,97,97,97,97,100,100,100,53,29,51,53,58,57,49,100,96,100,100,
|
||||
97,97,97,97,33,48,101,112,112,112,48,49,49,113,112,49,48,49,113,112,
|
||||
112,112,112,49,101,32,37,52,52,100,100,100,52,116,36,100,100,52,100,
|
||||
52,52,52,48,112,36,37,37,37,49,49,49,37,53,33,49,49,116,32,37,37,49,
|
||||
36,37,97,97,33,53,49,49,49,97,113,96,100,100,33,53,113,53,32,53,101,
|
||||
112,96,117,101,100,100,116,37,49,48,113,97,52,112,48,101,101,101,37,
|
||||
49,113,36,100,100,100,112,37,96,100,100,52,100,52,52,52,112,97,33,
|
||||
37,37,37,49,49,49,37,53,33,49,49,37,37,101,49,36,36,37,97,97,97,97,
|
||||
100,100,100,113,72,102,101,111,108,100,101,96,100,100,97,97,97,97,
|
||||
33,48,101,112,112,112,48,49,49,113,113,116,100,100,36,112,112,112,
|
||||
48,100,112,100,48,52,52,100,100,100,116,97,32,100,100,52,52,52,52,
|
||||
52,48,112,36,37,37,37,49,49,49,37,112,33,49,49,37,37,37,37,49,36,37,
|
||||
97,97,33,53,49,49,49,49,100,96,100,100,33,53,113,48,32,53,101,112,
|
||||
96,117,101,100,100,116,112,37,48,113,49,52,112,48,53,49,48,112,48,
|
||||
113,36,100,100,100,112,97,36,100,100,52,52,52,52,52,112,97,33,37,37,
|
||||
37,49,49,49,37,53,33,49,49,37,37,101,117,36,36,37,97,97,97,97,100,
|
||||
100,100,101,72,102,100,107,108,36,33,49,49,49,96,97,100,97,33,48,101,
|
||||
112,112,112,48,49,49,113,112,49,48,49,113,112,112,112,112,96,112,100,
|
||||
48,52,52,100,100,100,52,116,36,100,100,52,100,52,100,52,48,112,36,
|
||||
49,49,37,49,49,49,37,53,33,49,49,116,32,37,37,49,36,49,97,97,33,53,
|
||||
49,49,49,97,32,48,49,49,32,53,113,53,32,53,101,112,96,117,101,100,
|
||||
100,116,37,49,48,113,52,52,112,48,53,49,48,100,48,113,36,100,100,100,
|
||||
112,48,97,100,100,52,52,100,52,52,112,97,33,37,37,37,49,49,49,37,32,
|
||||
33,49,49,37,37,101,49,36,36,37,97,97,97,97,100,100,100,97,8,51,96,
|
||||
107,108,100,101,96,100,100,97,97,97,97,33,48,101,112,112,112,48,49,
|
||||
49,113,112,49,48,49,113,112,112,112,112,49,117,113,33,52,52,100,100,
|
||||
100,52,48,36,49,49,33,52,52,52,52,48,112,36,37,37,37,49,49,49,53,101,
|
||||
101,100,100,117,32,37,37,49,36,37,97,97,33,53,49,49,49,113,116,96,
|
||||
100,100,33,53,113,53,32,53,101,112,112,112,48,49,49,97,52,113,49,113,
|
||||
97,96,37,48,53,49,48,36,97,113,36,100,100,100,112,97,36,100,100,52,
|
||||
52,52,52,52,112,97,33,37,37,37,49,49,49,37,53,33,49,49,37,37,101,113,
|
||||
37,36,112,96,97,97,97,100,100,100,117,8,51,37,106,108,36,97,53,49,
|
||||
49,96,97,97,97,36,48,101,112,112,112,48,49,49,113,96,97,48,49,113,
|
||||
112,112,112,112,96,112,32,37,52,52,100,100,100,52,116,36,100,100,52,
|
||||
52,100,52,52,48,112,36,37,37,37,49,49,49,37,53,33,49,49,49,37,37,37,
|
||||
49,36,37,97,97,33,53,49,49,49,49,100,96,100,100,33,53,113,53,32,48,
|
||||
101,112,96,117,101,100,100,116,37,49,48,113,37,96,112,48,101,52,48,
|
||||
100,53,113,36,100,100,100,112,117,37,49,49,33,52,52,100,52,112,97,
|
||||
33,37,37,37,49,49,49,37,52,36,49,49,37,37,101,49,36,36,37,97,97,97,
|
||||
97,100,100,100,49,8,51,116,107,108,100,101,96,100,100,97,97,97,97,
|
||||
33,48,101,112,112,112,48,49,49,113,112,49,48,49,113,112,112,112,112,
|
||||
96,112,32,37,52,52,100,100,100,52,48,37,100,100,52,52,52,52,52,48,
|
||||
112,36,37,37,37,49,49,49,101,100,36,49,49,96,32,37,37,49,36,37,97,
|
||||
97,33,53,49,49,49,33,36,48,49,49,32,53,113,53,32,53,101,112,96,53,
|
||||
100,100,100,116,116,36,48,113,49,52,112,48,53,97,48,100,48,33,113,
|
||||
49,49,49,117,97,36,100,100,52,52,52,52,52,112,97,33,37,37,37,49,49,
|
||||
49,37,53,33,49,49,37,37,101,49,36,36,37,97,97,97,97,100,100,100,37,
|
||||
8,51,33,107,108,52,117,97,100,100,97,97,97,97,33,48,37,113,112,112,
|
||||
48,49,49,113,52,36,49,49,113,112,112,112,112,49,117,113,33,52,52,100,
|
||||
100,100,52,116,36,100,100,52,52,52,100,52,48,112,36,37,37,37,49,49,
|
||||
49,37,53,33,49,49,116,32,37,37,49,36,37,97,97,33,53,49,49,49,49,100,
|
||||
96,100,100,33,53,113,53,113,53,101,112,96,117,101,100,100,116,37,49,
|
||||
48,113,49,52,112,48,53,49,48,100,48,49,112,49,49,49,117,36,112,49,
|
||||
49,33,52,52,52,100,112,97,33,37,37,37,49,49,49,101,97,48,49,49,37,
|
||||
37,101,113,37,36,112,96,97,97,97,100,100,100,33,12,51,48,107,108,100,
|
||||
101,96,100,100,97,97,97,97,33,48,101,112,112,112,48,49,49,113,112,
|
||||
49,48,49,113,112,112,112,112,96,112,100,48,52,52,100,100,100,52,113,
|
||||
96,100,100,52,52,52,52,52,48,112,36,37,37,37,49,49,49,101,36,96,100,
|
||||
100,117,32,37,37,49,36,117,97,97,33,53,49,49,49,53,48,96,100,100,33,
|
||||
53,113,53,32,53,101,112,96,117,101,100,100,116,48,116,101,36,49,52,
|
||||
112,48,53,49,48,100,48,49,37,100,100,100,112,100,101,100,100,52,52,
|
||||
52,52,52,112,97,33,37,37,37,49,49,49,101,37,32,49,49,37,37,101,113,
|
||||
37,36,112,96,97,97,97,100,100,100,53,12,51,117,106,108,116,116,97,
|
||||
100,100,97,97,97,97,33,48,101,48,113,112,48,49,49,113,36,112,101,100,
|
||||
36,112,112,112,112,49,101,32,37,52,52,100,100,100,52,116,36,100,100,
|
||||
52,52,52,52,100,48,112,36,37,37,37,49,49,49,37,53,33,49,49,116,32,
|
||||
37,37,49,36,37,97,97,33,53,49,49,49,49,100,96,100,100,33,53,113,53,
|
||||
96,97,96,112,96,117,101,100,100,116,37,49,48,113,49,52,112,48,53,97,
|
||||
48,100,48,33,116,49,49,49,117,97,36,100,100,52,52,52,52,52,112,97,
|
||||
101,32,37,37,49,49,49,37,53,33,49,49,37,37,101,49,36,36,37,97,97,97,
|
||||
97,100,100,100,113,9,51,36,107,108,100,101,96,100,100,97,97,97,97,
|
||||
33,48,101,112,112,112,48,49,49,113,116,32,48,49,113,112,112,112,112,
|
||||
96,32,53,33,52,52,100,100,100,116,116,52,100,100,52,52,52,52,52,116,
|
||||
37,36,37,37,37,49,49,49,117,36,117,100,100,117,100,32,37,49,36,37,
|
||||
97,97,33,53,49,49,49,117,32,53,49,49,32,53,113,53,96,97,96,112,96,
|
||||
117,101,100,100,116,32,49,48,113,49,52,48,49,53,49,48,100,48,113,36,
|
||||
100,100,100,112,97,36,100,100,52,52,52,52,52,112,97,33,37,37,37,49,
|
||||
49,49,117,53,33,49,49,37,37,101,49,36,36,37,97,97,97,97,100,100,100,
|
||||
101,9,51,113,63,57,33,53,48,49,49,96,97,97,97,33,48,101,112,48,113,
|
||||
48,49,49,113,112,49,48,49,113,112,112,112,112,49,101,100,48,52,52,
|
||||
100,100,100,52,116,36,100,100,52,52,52,52,52,48,48,37,37,37,37,49,
|
||||
49,49,37,53,33,49,49,116,32,37,37,49,36,37,97,97,36,48,49,49,49,49,
|
||||
100,96,100,100,33,53,113,53,32,53,101,112,96,117,101,100,100,116,53,
|
||||
113,101,36,49,52,112,48,53,49,48,100,48,113,36,100,100,100,112,101,
|
||||
32,100,100,52,52,52,52,52,112,97,33,49,37,37,49,49,49,37,112,116,100,
|
||||
100,32,37,101,49,36,116,37,97,97,97,97,100,100,100,97,93,102,33,63,
|
||||
57,49,100,96,100,100,97,97,97,97,33,48,101,112,112,112,48,49,49,113,
|
||||
116,97,101,100,36,112,112,112,112,49,101,100,48,52,52,100,100,100,
|
||||
116,48,112,49,49,33,52,52,52,52,48,48,37,37,37,37,49,49,49,53,52,53,
|
||||
49,49,116,32,37,37,49,36,37,97,97,33,53,49,49,49,117,97,101,100,100,
|
||||
33,53,113,53,32,53,101,112,96,117,101,100,100,116,49,101,101,36,49,
|
||||
52,112,48,53,49,48,100,48,113,36,100,100,100,112,97,36,100,100,52,
|
||||
52,52,52,52,112,97,33,37,37,37,49,49,49,37,53,33,49,49,37,37,101,49,
|
||||
36,116,37,97,97,97,97,100,100,100,117,93,102,96,63,57,97,52,48,49,
|
||||
49,96,97,97,97,33,48,101,112,112,48,49,49,49,113,112,49,48,49,113,
|
||||
112,112,112,112,96,112,96,52,52,52,100,100,100,52,116,36,100,100,52,
|
||||
52,52,52,52,116,37,36,37,37,37,49,49,49,37,53,33,49,49,116,100,32,
|
||||
37,49,36,37,97,97,97,97,100,100,100,100,101,96,100,100,33,53,113,53,
|
||||
96,97,96,112,96,117,101,100,100,116,37,49,48,113,49,52,112,48,101,
|
||||
49,48,100,48,113,36,100,100,100,112,52,48,49,49,33,52,52,52,52,112,
|
||||
97,33,37,49,37,49,49,49,101,100,48,49,49,37,37,101,49,36,36,37,97,
|
||||
97,97,97,100,100,100,49,93,102,53,63,57,49,100,96,100,100,97,97,97,
|
||||
97,33,48,101,112,112,112,48,49,49,113,112,49,48,49,113,112,112,112,
|
||||
112,49,101,100,48,52,52,100,100,100,116,96,117,100,100,52,52,52,52,
|
||||
52,116,101,32,37,37,37,49,49,49,117,36,100,100,100,117,32,37,37,49,
|
||||
36,37,97,97,33,53,49,49,49,117,101,53,49,49,32,53,113,53,32,53,37,
|
||||
113,96,117,101,100,100,116,113,101,48,113,49,52,112,48,53,49,48,100,
|
||||
48,116,36,100,100,100,112,97,36,100,100,52,52,52,52,52,112,97,33,37,
|
||||
37,37,49,49,49,37,53,33,49,49,37,37,101,49,36,48,37,97,97,97,97,100,
|
||||
100,100,37,93,102,116,106,108,36,113,49,49,49,96,97,97,97,33,48,101,
|
||||
112,112,112,48,49,49,49,97,33,49,49,113,112,112,112,112,96,112,96,
|
||||
52,52,52,100,100,100,52,116,36,100,100,52,52,52,52,52,48,112,36,37,
|
||||
37,37,49,49,49,37,53,33,49,49,116,100,32,37,49,36,37,97,97,97,97,100,
|
||||
100,100,100,101,96,100,100,33,53,113,53,32,53,101,112,96,117,101,100,
|
||||
100,116,37,49,48,113,49,52,112,48,53,49,48,100,48,113,36,100,100,100,
|
||||
112,101,36,49,49,33,52,52,52,52,112,97,33,37,37,49,49,49,49,101,97,
|
||||
36,49,49,37,37,101,49,36,36,49,97,97,97,97,100,100,100,33,9,51,112,
|
||||
106,108,100,101,96,100,100,97,97,97,97,33,48,101,112,112,112,48,49,
|
||||
49,113,100,100,48,49,113,112,112,112,112,101,37,97,37,52,52,100,100,
|
||||
100,116,32,116,49,49,33,52,52,52,52,48,112,48,37,37,37,49,49,49,97,
|
||||
96,32,49,49,116,32,37,37,49,36,37,97,97,33,53,49,49,49,117,49,96,100,
|
||||
100,33,53,113,53,32,53,101,112,96,117,101,100,100,116,37,49,48,113,
|
||||
49,52,112,48,53,49,48,100,48,116,36,100,100,100,112,97,36,100,100,
|
||||
52,52,52,52,52,112,97,33,37,37,37,49,49,49,37,116,117,100,100,32,37,
|
||||
101,49,36,36,37,97,97,97,97,100,100,100,53,9,51,53,63,57,49,100,96,
|
||||
100,100,97,97,97,97,33,48,101,112,112,112,48,49,49,113,112,49,48,49,
|
||||
113,112,112,112,112,49,101,100,48,52,52,100,100,100,52,116,36,100,
|
||||
100,52,52,52,52,52,48,112,36,37,37,37,49,49,49,37,53,33,49,49,116,
|
||||
32,49,37,49,117,36,97,97,33,53,49,49,49,49,100,96,100,100,33,53,113,
|
||||
53,32,53,113,112,96,117,101,100,100,116,117,33,49,113,49,52,112,48,
|
||||
53,49,48,100,48,113,36,100,100,100,112,52,116,49,49,33,52,52,52,52,
|
||||
112,97,33,37,37,37,49,49,49,49,53,33,49,49,37,37,101,49,36,48,37,97,
|
||||
97,97,97,100,100,100,113,92,102,101,106,108,100,101,96,100,100,97,
|
||||
97,97,97,33,48,101,112,112,112,48,49,49,113,113,96,100,100,36,112,
|
||||
112,112,112,49,101,100,48,52,52,100,100,100,52,33,113,49,49,33,52,
|
||||
52,52,52,48,112,36,37,37,37,49,49,49,53,36,116,100,100,117,32,37,37,
|
||||
49,36,37,97,97,33,53,49,49,49,101,112,53,49,49,32,53,113,53,32,53,
|
||||
113,112,96,117,101,100,100,116,117,117,101,36,49,52,112,48,53,49,48,
|
||||
100,48,113,36,100,100,100,112,97,36,100,100,52,52,52,52,52,112,97,
|
||||
33,37,37,37,49,49,49,101,116,116,100,100,32,37,101,49,36,36,37,97,
|
||||
97,97,97,100,100,100,101,92,102,100,42,57,49,100,96,100,100,97,97,
|
||||
97,97,33,48,101,112,112,112,48,49,49,113,112,49,48,49,113,112,112,
|
||||
112,112,49,101,36,49,52,52,100,100,100,52,116,36,100,100,52,52,52,
|
||||
52,52,48,112,36,49,37,37,49,49,49,37,53,33,49,49,116,32,49,37,49,117,
|
||||
36,97,97,33,53,49,49,49,49,100,96,100,100,33,53,113,53,32,53,101,112,
|
||||
96,117,101,100,100,116,37,49,48,113,49,52,112,48,53,49,48,53,37,116,
|
||||
36,100,100,100,112,97,36,100,100,52,52,52,52,52,112,97,33,37,37,37,
|
||||
49,49,49,37,53,33,49,49,37,37,101,49,48,36,37,100,97,97,97,100,100,
|
||||
100,97,28,102,97,42,57,49,100,96,100,100,97,97,97,97,33,48,101,112,
|
||||
112,112,48,49,49,113,96,117,101,100,36,112,112,112,112,49,101,100,
|
||||
53,52,52,100,100,100,52,49,97,100,100,52,52,52,52,52,48,112,36,37,
|
||||
37,37,49,49,49,53,112,53,49,49,116,32,37,37,49,117,36,97,97,33,53,
|
||||
49,49,49,37,100,96,100,100,33,53,113,53,32,53,101,48,97,117,101,100,
|
||||
100,116,49,112,48,113,49,52,112,48,53,49,48,100,48,33,113,49,49,49,
|
||||
117,97,36,100,100,52,52,52,52,52,112,97,33,37,37,37,49,49,49,101,52,
|
||||
48,49,49,37,37,101,49,36,36,37,97,97,97,97,100,100,100,117,28,102,
|
||||
32,47,57,49,100,96,100,100,97,97,97,97,33,48,101,112,112,112,48,49,
|
||||
49,113,112,49,48,49,113,112,112,112,112,113,112,36,49,52,52,100,100,
|
||||
100,52,116,36,100,100,52,52,52,52,52,48,112,36,37,49,37,49,49,49,37,
|
||||
53,33,49,49,116,32,49,37,49,36,37,97,97,33,53,49,49,49,113,32,100,
|
||||
100,100,33,53,113,53,32,53,101,112,96,117,101,100,100,36,112,49,48,
|
||||
113,49,52,112,48,53,49,48,100,48,113,36,100,100,100,112,97,36,100,
|
||||
100,52,52,52,52,52,112,97,33,37,37,37,49,49,49,37,53,33,49,49,37,37,
|
||||
101,49,36,36,37,97,100,97,97,100,100,100,49,28,102,117,42,57,49,100,
|
||||
96,100,100,97,97,97,97,33,48,101,112,112,112,48,49,49,113,36,33,100,
|
||||
100,36,112,112,112,112,49,101,100,53,52,52,100,100,100,52,37,97,100,
|
||||
100,52,52,52,52,52,48,112,36,37,37,37,49,49,49,117,53,33,49,49,116,
|
||||
32,37,37,49,36,37,97,97,33,53,49,49,49,49,100,96,100,100,33,53,113,
|
||||
53,32,53,101,112,96,117,101,100,100,116,97,116,49,113,49,52,112,48,
|
||||
53,49,48,100,48,49,37,100,100,100,112,97,36,100,100,52,52,52,52,52,
|
||||
112,97,33,37,37,37,49,49,49,37,100,33,49,49,37,37,101,49,36,36,37,
|
||||
97,97,97,97,100,100,100,37,28,102,52,42,57,49,100,96,100,100,97,97,
|
||||
97,97,33,48,101,112,112,112,48,49,49,113,112,49,48,49,113,112,112,
|
||||
112,112,49,101,100,48,52,52,100,100,100,52,116,36,100,100,52,52,52,
|
||||
52,52,48,112,36,37,37,49,49,49,49,101,37,32,49,49,116,32,37,49,49,
|
||||
36,37,97,97,33,53,49,49,49,113,37,100,100,100,33,53,113,53,32,53,101,
|
||||
48,97,117,101,100,100,36,112,49,48,113,49,52,112,48,53,49,48,100,48,
|
||||
113,36,100,100,100,112,97,36,100,100,52,52,52,52,52,112,97,33,37,37,
|
||||
37,49,49,49,37,53,33,49,49,37,37,101,49,36,36,37,97,97,100,97,100,
|
||||
100,100,33,8,102,49,42,57,49,100,96,100,100,97,97,97,97,33,48,101,
|
||||
112,112,112,48,49,49,113,113,113,48,49,113,112,112,112,112,49,101,
|
||||
49,37,52,52,100,100,100,52,116,36,100,100,52,52,52,52,52,48,112,36,
|
||||
37,37,37,49,49,49,37,48,100,100,100,117,32,37,37,49,36,37,97,97,33,
|
||||
53,49,49,49,49,100,96,100,100,33,53,113,53,32,53,101,112,96,117,101,
|
||||
100,100,116,117,49,48,113,49,52,112,48,53,49,48,100,48,113,113,49,
|
||||
49,49,117,97,36,100,100,52,52,52,52,52,112,97,33,37,37,37,49,49,49,
|
||||
101,49,48,49,49,37,37,101,49,36,36,37,97,97,97,97,100,100,100,53,8,
|
||||
102,112,47,57,49,100,96,100,100,97,97,97,97,33,48,101,112,112,112,
|
||||
48,49,49,113,112,49,48,49,113,112,112,112,112,49,101,100,48,52,52,
|
||||
100,100,100,52,116,36,100,100,52,52,52,52,52,48,112,36,37,37,37,49,
|
||||
49,49,37,53,33,49,49,116,32,37,37,49,36,37,100,97,33,53,49,49,49,33,
|
||||
96,53,49,49,32,53,113,53,32,53,101,112,48,97,101,100,100,116,37,49,
|
||||
48,113,49,52,112,48,53,49,48,100,48,113,36,100,100,100,112,97,36,100,
|
||||
100,52,52,52,52,52,112,97,33,37,37,37,49,49,49,37,53,33,49,49,37,37,
|
||||
101,49,36,36,37,97,97,97,100,100,100,100,113,29,102,37,42,57,49,100,
|
||||
96,100,100,97,97,97,97,33,48,101,112,112,112,48,49,49,113,97,96,101,
|
||||
100,36,112,112,112,112,49,101,100,48,52,52,100,100,100,52,116,36,100,
|
||||
100,52,52,52,52,52,48,112,36,37,37,37,49,49,49,101,96,96,100,100,117,
|
||||
32,37,37,49,36,37,97,97,33,53,49,49,49,101,36,96,100,100,33,53,113,
|
||||
53,32,53,101,112,96,117,101,100,100,116,37,49,48,113,49,52,112,48,
|
||||
53,49,48,100,48,113,48,100,100,100,112,97,36,100,100,52,52,52,52,52,
|
||||
112,97,33,37,37,37,49,49,49,53,48,37,49,49,37,37,101,49,36,36,37,97,
|
||||
97,97,97,100,100,100,101,29,102,36,46,57,49,100,96,100,100,97,97,97,
|
||||
97,33,48,101,112,112,112,48,49,49,113,112,49,48,49,113,112,112,112,
|
||||
112,49,101,49,37,52,52,100,100,100,52,116,36,100,100,52,52,52,52,52,
|
||||
48,112,36,37,37,37,49,49,49,37,53,33,49,49,116,32,37,37,49,36,37,100,
|
||||
97,33,53,49,49,49,49,100,96,100,100,33,53,113,53,32,53,101,112,48,
|
||||
97,101,100,100,116,49,32,100,36,49,52,112,48,53,49,48,100,48,113,36,
|
||||
100,100,100,112,97,36,100,100,52,52,52,52,52,112,97,33,37,37,37,49,
|
||||
49,49,37,53,33,49,49,37,37,101,49,36,117,36,97,97,97,97,100,100,100,
|
||||
97,25,102,33,46,57,49,100,96,100,100,97,97,97,97,33,48,101,112,112,
|
||||
112,48,49,49,113,33,117,49,49,113,112,112,112,112,49,101,100,48,52,
|
||||
52,100,100,100,52,116,36,100,100,52,52,52,52,52,48,112,36,37,37,37,
|
||||
49,49,49,101,101,96,100,100,117,32,37,37,49,36,37,97,97,33,53,49,49,
|
||||
49,33,49,97,100,100,33,53,113,53,32,53,101,112,32,116,101,100,100,
|
||||
116,48,33,48,113,49,52,112,48,53,49,48,100,48,113,48,100,100,100,52,
|
||||
116,36,100,100,52,52,52,52,52,112,97,33,37,37,37,49,49,49,117,96,117,
|
||||
100,100,32,37,101,49,36,36,37,97,97,97,97,100,100,100,117,25,102,96,
|
||||
46,57,49,100,96,100,100,97,97,97,97,33,48,101,112,112,112,48,49,49,
|
||||
113,112,49,48,49,113,112,112,112,112,49,101,49,37,52,52,100,100,100,
|
||||
52,116,36,100,100,52,52,52,52,52,48,112,36,37,37,37,49,49,49,37,53,
|
||||
33,49,49,116,32,37,37,49,36,37,100,97,33,53,49,49,49,49,100,96,100,
|
||||
100,33,53,113,53,32,53,101,112,96,117,101,100,100,116,37,49,48,113,
|
||||
49,52,112,48,53,49,48,100,48,113,116,100,100,100,32,97,36,100,100,
|
||||
52,52,52,52,52,112,97,33,37,37,37,49,49,49,37,53,33,49,49,37,37,101,
|
||||
49,36,117,36,97,97,97,97,100,100,100,49,25,102,53,46,57,49,100,96,
|
||||
100,100,97,97,97,97,33,48,101,112,112,112,48,49,49,113,33,112,101,
|
||||
100,36,112,112,112,112,49,101,100,48,100,52,100,100,100,52,116,36,
|
||||
100,100,52,52,52,52,52,48,112,36,37,37,37,49,49,49,37,53,33,49,49,
|
||||
116,32,37,37,49,36,37,97,97,33,53,49,49,49,113,117,53,49,49,32,53,
|
||||
113,53,32,53,101,112,96,53,100,100,100,52,36,49,48,113,49,52,112,48,
|
||||
53,49,48,100,48,113,116,100,100,100,112,97,36,100,100,52,52,52,52,
|
||||
52,112,97,33,37,37,37,49,49,49,117,53,33,49,49,37,37,101,49,36,36,
|
||||
37,97,97,97,97,100,100,100,112,24,102,116,43,57,49,100,96,100,100,
|
||||
97,97,97,97,33,48,101,112,112,112,48,49,49,113,112,49,48,49,113,112,
|
||||
112,112,112,49,101,100,48,52,52,100,100,100,52,116,36,100,100,52,52,
|
||||
52,52,52,48,112,36,37,37,37,49,49,49,37,52,48,49,49,116,32,37,37,49,
|
||||
36,37,97,100,33,53,49,49,49,49,100,96,100,100,33,53,113,53,32,53,101,
|
||||
112,96,37,48,49,49,113,36,113,48,113,49,52,112,48,53,49,48,100,48,
|
||||
113,36,100,100,100,112,97,36,100,100,52,52,52,52,52,112,97,33,37,37,
|
||||
37,49,49,49,37,48,117,100,100,32,37,101,49,36,36,37,97,97,97,97,100,
|
||||
100,100,33,13,102,113,43,57,49,100,96,100,100,97,97,97,97,33,48,101,
|
||||
112,112,112,48,49,49,113,112,49,48,49,113,112,112,112,112,113,112,
|
||||
100,48,52,52,100,100,100,52,116,36,100,100,52,52,52,52,52,48,112,36,
|
||||
37,37,37,49,49,49,101,37,97,100,100,117,32,37,37,49,36,37,97,97,36,
|
||||
53,49,49,49,97,53,97,100,100,33,53,113,53,32,53,101,112,96,117,101,
|
||||
100,100,36,112,49,48,113,49,52,112,48,53,49,48,100,48,113,36,100,100,
|
||||
100,52,116,36,100,100,52,52,52,52,52,112,97,33,37,37,37,49,49,49,37,
|
||||
53,33,49,49,37,37,101,49,36,36,37,97,97,97,97,100,100,100,53,13,102,
|
||||
48,46,57,49,100,96,100,100,97,97,97,97,33,48,101,112,112,112,48,49,
|
||||
49,113,52,100,48,49,113,112,112,112,112,49,37,101,48,52,52,100,100,
|
||||
100,52,116,36,100,100,52,52,52,52,52,48,112,36,37,37,37,49,49,49,37,
|
||||
53,33,49,49,116,32,37,37,49,36,37,97,97,97,100,100,100,100,100,101,
|
||||
96,100,100,33,53,113,53,32,53,101,112,96,117,101,100,100,116,97,32,
|
||||
100,36,49,52,112,48,53,49,48,100,48,113,36,100,100,100,112,97,36,100,
|
||||
100,52,52,52,52,52,112,97,33,37,37,37,49,49,49,37,53,33,49,49,37,37,
|
||||
101,49,36,36,37,97,97,97,97,100,100,100,113,24,102,101,43,57,49,100,
|
||||
96,100,100,97,97,97,97,33,48,101,112,112,112,48,49,49,113,96,48,100,
|
||||
100,36,112,112,112,112,49,101,100,48,52,52,100,100,100,52,116,36,100,
|
||||
100,52,52,52,52,52,48,112,36,37,37,37,49,49,49,37,53,33,49,49,116,
|
||||
32,37,37,49,36,37,97,97,33,53,49,49,49,113,32,100,100,100,33,53,113,
|
||||
53,32,53,101,112,96,117,101,100,100,52,36,49,48,113,49,52,112,48,53,
|
||||
49,48,100,48,113,36,100,100,100,32,97,36,100,100,52,52,52,52,52,112,
|
||||
97,33,37,37,37,49,49,49,37,53,33,49,49,37,37,101,49,36,36,37,97,97,
|
||||
97,97,100,100,100,101,24,102,100,127,108,100,101,96,100,100,97,97,
|
||||
97,97,33,48,101,112,112,112,48,49,49,113,112,49,48,49,113,112,112,
|
||||
112,112,49,101,100,48,52,100,100,100,100,100,116,36,100,100,52,52,
|
||||
52,52,52,48,112,36,37,37,37,49,49,49,37,53,33,49,49,116,32,37,37,49,
|
||||
36,37,97,97,33,53,49,49,49,49,100,96,100,100,33,53,113,53,32,53,101,
|
||||
112,96,117,101,100,100,116,113,33,100,36,49,52,112,48,53,49,48,100,
|
||||
48,113,36,100,100,100,112,97,36,100,100,52,52,52,52,52,112,97,33,37,
|
||||
37,37,49,49,49,37,53,33,49,49,37,37,101,49,36,36,37,97,97,97,97,100,
|
||||
100,100,97,88,51,96,127,108,100,100,100,100,100,97,97,97,97,97,100,
|
||||
36,112,112,112,48,96,100,100,100,100,100,100,36,112,112,112,112,100,
|
||||
48,97,53,52,52,36,48,49,49,49,49,49,49,33,52,52,52,52,100,100,32,37,
|
||||
37,37,33,100,100,100,100,100,100,100,32,37,37,37,49,49,49,96,97,97,
|
||||
97,100,100,100,100,100,100,100,100,97,97,100,97,97,100,36,112,112,
|
||||
112,48,96,100,100,100,100,100,100,36,100,112,48,101,117,48,97,97,96,
|
||||
53,36,48,49,49,49,49,49,49,33,52,52,52,52,52,100,32,37,37,37,33,100,
|
||||
100,100,100,100,100,100,32,37,101,116,37,37,49,96,97,97,97,32,49,49,
|
||||
37,93,51,37,126,108,100,100,100,100,100,117,32,116,117,117,100,36,
|
||||
117,117,117,117,53,49,49,49,49,49,49,113,117,117,117,117,53,49,33,
|
||||
116,37,48,49,49,49,49,49,49,49,49,33,52,52,52,52,100,100,52,32,37,
|
||||
37,117,49,49,49,49,49,49,49,37,33,100,100,100,32,49,116,97,32,37,49,
|
||||
49,49,49,49,49,49,49,49,96,100,97,100,97,36,53,32,112,112,48,49,49,
|
||||
49,49,49,49,49,49,113,53,49,113,48,49,33,36,112,112,48,49,49,49,49,
|
||||
49,49,97,101,36,112,112,48,49,33,52,52,52,52,100,100,100,100,100,100,
|
||||
100,52,52,52,52,100,100,100,100,100,100,100,117,100,100,52,88,51,116,
|
||||
127,108,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,
|
||||
100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,32,49,
|
||||
49,97,117,101,100,100,100,100,100,100,52,52,52,52,52,100,100,100,32,
|
||||
37,37,49,49,49,49,49,49,49,49,49,49,113,116,117,49,49,97,101,100,100,
|
||||
117,100,100,100,100,100,100,100,52,36,53,49,116,100,100,100,32,49,
|
||||
49,49,49,49,49,49,49,49,113,117,53,97,37,53,49,97,33,49,49,49,49,49,
|
||||
49,49,49,49,49,49,97,101,100,100,100,100,100,100,100,100,100,100,100,
|
||||
100,100,100,100,100,100,100,100,100,112,49,49,116,117,117,117,100,
|
||||
100,100,112,93,51,33,127,108,100,100,100,100,100,100,100,100,100,100,
|
||||
100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,
|
||||
100,100,100,100,97,100,48,96,101,100,100,100,100,100,100,116,112,112,
|
||||
112,112,96,100,100,48,52,52,48,49,49,49,49,49,49,49,113,112,48,49,
|
||||
52,48,49,33,52,52,52,49,100,100,100,100,100,100,100,100,52,97,52,100,
|
||||
100,100,100,32,37,37,37,49,49,49,49,49,49,49,49,49,113,48,37,49,49,
|
||||
49,96,97,97,97,100,100,100,100,100,100,100,52,100,100,100,100,100,
|
||||
100,100,100,100,100,100,100,100,100,100,100,100,36,48,113,112,116,
|
||||
49,113,33,116,117,117,100,100,100,36,92,51,48,127,108,100,100,100,
|
||||
100,36,117,117,117,117,53,49,97,117,117,117,117,101,100,100,100,100,
|
||||
100,100,116,117,117,117,117,101,100,112,117,117,97,53,100,100,100,
|
||||
100,100,100,100,96,100,100,100,100,48,49,116,49,49,49,117,100,100,
|
||||
100,100,100,100,100,117,117,117,97,32,49,113,117,117,117,53,96,100,
|
||||
100,100,100,100,100,36,117,53,113,117,36,49,97,117,117,117,117,101,
|
||||
100,100,100,100,100,100,36,112,96,101,36,48,49,33,112,117,117,117,
|
||||
49,49,49,49,49,49,49,117,49,117,117,117,49,49,116,117,117,117,117,
|
||||
100,100,100,100,100,100,100,117,117,117,117,32,49,49,116,97,97,33,
|
||||
53,49,49,101,92,59,101,43,179,100,194,206,100,};
|
||||
@ -1,905 +0,0 @@
|
||||
/*-
|
||||
* Cronyx-Sigma Driver Development Kit.
|
||||
*
|
||||
* Copyright (C) 1998 Cronyx Engineering.
|
||||
* Author: Pavel Novikov, <pavel@inr.net.kiae.su>
|
||||
*
|
||||
* Copyright (C) 1998-2003 Cronyx Engineering.
|
||||
* Author: Roman Kurakin, <rik@cronyx.ru>
|
||||
*
|
||||
* This software is distributed with NO WARRANTIES, not even the implied
|
||||
* warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* Authors grant any other persons or organisations permission to use
|
||||
* or modify this software as long as this message is kept with the software,
|
||||
* all derivative works or modified versions.
|
||||
*
|
||||
* Cronyx Id: cxddk.c,v 1.1.2.2 2003/11/27 14:24:50 rik Exp $
|
||||
*/
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <dev/cx/machdep.h>
|
||||
#include <dev/cx/cxddk.h>
|
||||
#include <dev/cx/cxreg.h>
|
||||
#include <dev/cx/cronyxfw.h>
|
||||
#include <dev/cx/csigmafw.h>
|
||||
|
||||
#define BYTE *(unsigned char*)&
|
||||
|
||||
/* standard base port set */
|
||||
static short porttab [] = {
|
||||
0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0,
|
||||
0x300, 0x320, 0x340, 0x360, 0x380, 0x3a0, 0x3c0, 0x3e0, 0
|
||||
};
|
||||
|
||||
/*
|
||||
* Compute the optimal size of the receive buffer.
|
||||
*/
|
||||
static int cx_compute_buf_len (cx_chan_t *c)
|
||||
{
|
||||
int rbsz;
|
||||
if (c->mode == M_ASYNC) {
|
||||
rbsz = (c->rxbaud + 800 - 1) / 800 * 2;
|
||||
if (rbsz < 4)
|
||||
rbsz = 4;
|
||||
else if (rbsz > DMABUFSZ)
|
||||
rbsz = DMABUFSZ;
|
||||
}
|
||||
else
|
||||
rbsz = DMABUFSZ;
|
||||
|
||||
return rbsz;
|
||||
}
|
||||
|
||||
/*
|
||||
* Auto-detect the installed adapters.
|
||||
*/
|
||||
int cx_find (port_t *board_ports)
|
||||
{
|
||||
int i, n;
|
||||
|
||||
for (i=0, n=0; porttab[i] && n<NBRD; i++)
|
||||
if (cx_probe_board (porttab[i], -1, -1))
|
||||
board_ports[n++] = porttab[i];
|
||||
return n;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize the adapter.
|
||||
*/
|
||||
int cx_open_board (cx_board_t *b, int num, port_t port, int irq, int dma)
|
||||
{
|
||||
cx_chan_t *c;
|
||||
|
||||
if (num >= NBRD || ! cx_probe_board (port, irq, dma))
|
||||
return 0;
|
||||
|
||||
/* init callback pointers */
|
||||
for (c=b->chan; c<b->chan+NCHAN; ++c) {
|
||||
c->call_on_tx = 0;
|
||||
c->call_on_rx = 0;
|
||||
c->call_on_msig = 0;
|
||||
c->call_on_err = 0;
|
||||
}
|
||||
|
||||
cx_init (b, num, port, irq, dma);
|
||||
|
||||
/* Loading firmware */
|
||||
if (! cx_setup_board (b, csigma_fw_data, csigma_fw_len, csigma_fw_tvec))
|
||||
return 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Shutdown the adapter.
|
||||
*/
|
||||
void cx_close_board (cx_board_t *b)
|
||||
{
|
||||
cx_setup_board (b, 0, 0, 0);
|
||||
|
||||
/* Reset the controller. */
|
||||
outb (BCR0(b->port), 0);
|
||||
if (b->chan[8].type || b->chan[12].type)
|
||||
outb (BCR0(b->port+0x10), 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Start the channel.
|
||||
*/
|
||||
void cx_start_chan (cx_chan_t *c, cx_buf_t *cb, unsigned long phys)
|
||||
{
|
||||
int command = 0;
|
||||
int mode = 0;
|
||||
int ier = 0;
|
||||
int rbsz;
|
||||
|
||||
c->overflow = 0;
|
||||
|
||||
/* Setting up buffers */
|
||||
if (cb) {
|
||||
c->arbuf = cb->rbuffer[0];
|
||||
c->brbuf = cb->rbuffer[1];
|
||||
c->atbuf = cb->tbuffer[0];
|
||||
c->btbuf = cb->tbuffer[1];
|
||||
c->arphys = phys + ((char*)c->arbuf - (char*)cb);
|
||||
c->brphys = phys + ((char*)c->brbuf - (char*)cb);
|
||||
c->atphys = phys + ((char*)c->atbuf - (char*)cb);
|
||||
c->btphys = phys + ((char*)c->btbuf - (char*)cb);
|
||||
}
|
||||
|
||||
/* Set current channel number */
|
||||
outb (CAR(c->port), c->num & 3);
|
||||
|
||||
/* set receiver A buffer physical address */
|
||||
outw (ARBADRU(c->port), (unsigned short) (c->arphys>>16));
|
||||
outw (ARBADRL(c->port), (unsigned short) c->arphys);
|
||||
|
||||
/* set receiver B buffer physical address */
|
||||
outw (BRBADRU(c->port), (unsigned short) (c->brphys>>16));
|
||||
outw (BRBADRL(c->port), (unsigned short) c->brphys);
|
||||
|
||||
/* set transmitter A buffer physical address */
|
||||
outw (ATBADRU(c->port), (unsigned short) (c->atphys>>16));
|
||||
outw (ATBADRL(c->port), (unsigned short) c->atphys);
|
||||
|
||||
/* set transmitter B buffer physical address */
|
||||
outw (BTBADRU(c->port), (unsigned short) (c->btphys>>16));
|
||||
outw (BTBADRL(c->port), (unsigned short) c->btphys);
|
||||
|
||||
/* rx */
|
||||
command |= CCR_ENRX;
|
||||
ier |= IER_RXD;
|
||||
if (c->board->dma) {
|
||||
mode |= CMR_RXDMA;
|
||||
if (c->mode == M_ASYNC)
|
||||
ier |= IER_RET;
|
||||
}
|
||||
|
||||
/* tx */
|
||||
command |= CCR_ENTX;
|
||||
ier |= (c->mode == M_ASYNC) ? IER_TXD : (IER_TXD | IER_TXMPTY);
|
||||
if (c->board->dma)
|
||||
mode |= CMR_TXDMA;
|
||||
|
||||
/* Set mode */
|
||||
outb (CMR(c->port), mode | (c->mode == M_ASYNC ? CMR_ASYNC : CMR_HDLC));
|
||||
|
||||
/* Clear and initialize channel */
|
||||
cx_cmd (c->port, CCR_CLRCH);
|
||||
cx_cmd (c->port, CCR_INITCH | command);
|
||||
if (c->mode == M_ASYNC)
|
||||
cx_cmd (c->port, CCR_ENTX);
|
||||
|
||||
/* Start receiver */
|
||||
rbsz = cx_compute_buf_len(c);
|
||||
outw (ARBCNT(c->port), rbsz);
|
||||
outw (BRBCNT(c->port), rbsz);
|
||||
outw (ARBSTS(c->port), BSTS_OWN24);
|
||||
outw (BRBSTS(c->port), BSTS_OWN24);
|
||||
|
||||
if (c->mode == M_ASYNC)
|
||||
ier |= IER_MDM;
|
||||
|
||||
/* Enable interrupts */
|
||||
outb (IER(c->port), ier);
|
||||
|
||||
/* Clear DTR and RTS */
|
||||
cx_set_dtr (c, 0);
|
||||
cx_set_rts (c, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Turn the receiver on/off.
|
||||
*/
|
||||
void cx_enable_receive (cx_chan_t *c, int on)
|
||||
{
|
||||
unsigned char ier;
|
||||
|
||||
if (cx_receive_enabled(c) && ! on) {
|
||||
outb (CAR(c->port), c->num & 3);
|
||||
if (c->mode == M_ASYNC) {
|
||||
ier = inb (IER(c->port));
|
||||
outb (IER(c->port), ier & ~ (IER_RXD | IER_RET));
|
||||
}
|
||||
cx_cmd (c->port, CCR_DISRX);
|
||||
} else if (! cx_receive_enabled(c) && on) {
|
||||
outb (CAR(c->port), c->num & 3);
|
||||
ier = inb (IER(c->port));
|
||||
if (c->mode == M_ASYNC)
|
||||
outb (IER(c->port), ier | (IER_RXD | IER_RET));
|
||||
else
|
||||
outb (IER(c->port), ier | IER_RXD);
|
||||
cx_cmd (c->port, CCR_ENRX);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Turn the transmitter on/off.
|
||||
*/
|
||||
void cx_enable_transmit (cx_chan_t *c, int on)
|
||||
{
|
||||
if (cx_transmit_enabled(c) && ! on) {
|
||||
outb (CAR(c->port), c->num & 3);
|
||||
if (c->mode != M_ASYNC)
|
||||
outb (STCR(c->port), STC_ABORTTX | STC_SNDSPC);
|
||||
cx_cmd (c->port, CCR_DISTX);
|
||||
} else if (! cx_transmit_enabled(c) && on) {
|
||||
outb (CAR(c->port), c->num & 3);
|
||||
cx_cmd (c->port, CCR_ENTX);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Get channel status.
|
||||
*/
|
||||
int cx_receive_enabled (cx_chan_t *c)
|
||||
{
|
||||
outb (CAR(c->port), c->num & 3);
|
||||
return (inb (CSR(c->port)) & CSRA_RXEN) != 0;
|
||||
}
|
||||
|
||||
int cx_transmit_enabled (cx_chan_t *c)
|
||||
{
|
||||
outb (CAR(c->port), c->num & 3);
|
||||
return (inb (CSR(c->port)) & CSRA_TXEN) != 0;
|
||||
}
|
||||
|
||||
unsigned long cx_get_baud (cx_chan_t *c)
|
||||
{
|
||||
return (c->opt.tcor.clk == CLK_EXT) ? 0 : c->txbaud;
|
||||
}
|
||||
|
||||
int cx_get_loop (cx_chan_t *c)
|
||||
{
|
||||
return c->opt.tcor.llm ? 1 : 0;
|
||||
}
|
||||
|
||||
int cx_get_nrzi (cx_chan_t *c)
|
||||
{
|
||||
return c->opt.rcor.encod == ENCOD_NRZI;
|
||||
}
|
||||
|
||||
int cx_get_dpll (cx_chan_t *c)
|
||||
{
|
||||
return c->opt.rcor.dpll ? 1 : 0;
|
||||
}
|
||||
|
||||
void cx_set_baud (cx_chan_t *c, unsigned long bps)
|
||||
{
|
||||
int clock, period;
|
||||
|
||||
c->txbaud = c->rxbaud = bps;
|
||||
|
||||
/* Set current channel number */
|
||||
outb (CAR(c->port), c->num & 3);
|
||||
if (bps) {
|
||||
if (c->mode == M_ASYNC || c->opt.rcor.dpll || c->opt.tcor.llm) {
|
||||
/* Receive baud - internal */
|
||||
cx_clock (c->oscfreq, c->rxbaud, &clock, &period);
|
||||
c->opt.rcor.clk = clock;
|
||||
outb (RCOR(c->port), BYTE c->opt.rcor);
|
||||
outb (RBPR(c->port), period);
|
||||
} else {
|
||||
/* Receive baud - external */
|
||||
c->opt.rcor.clk = CLK_EXT;
|
||||
outb (RCOR(c->port), BYTE c->opt.rcor);
|
||||
outb (RBPR(c->port), 1);
|
||||
}
|
||||
|
||||
/* Transmit baud - internal */
|
||||
cx_clock (c->oscfreq, c->txbaud, &clock, &period);
|
||||
c->opt.tcor.clk = clock;
|
||||
c->opt.tcor.ext1x = 0;
|
||||
outb (TBPR(c->port), period);
|
||||
} else if (c->mode != M_ASYNC) {
|
||||
/* External clock - disable local loopback and DPLL */
|
||||
c->opt.tcor.llm = 0;
|
||||
c->opt.rcor.dpll = 0;
|
||||
|
||||
/* Transmit baud - external */
|
||||
c->opt.tcor.ext1x = 1;
|
||||
c->opt.tcor.clk = CLK_EXT;
|
||||
outb (TBPR(c->port), 1);
|
||||
|
||||
/* Receive baud - external */
|
||||
c->opt.rcor.clk = CLK_EXT;
|
||||
outb (RCOR(c->port), BYTE c->opt.rcor);
|
||||
outb (RBPR(c->port), 1);
|
||||
}
|
||||
if (c->opt.tcor.llm)
|
||||
outb (COR2(c->port), (BYTE c->hopt.cor2) & ~3);
|
||||
else
|
||||
outb (COR2(c->port), BYTE c->hopt.cor2);
|
||||
outb (TCOR(c->port), BYTE c->opt.tcor);
|
||||
}
|
||||
|
||||
void cx_set_loop (cx_chan_t *c, int on)
|
||||
{
|
||||
if (! c->txbaud)
|
||||
return;
|
||||
|
||||
c->opt.tcor.llm = on ? 1 : 0;
|
||||
cx_set_baud (c, c->txbaud);
|
||||
}
|
||||
|
||||
void cx_set_dpll (cx_chan_t *c, int on)
|
||||
{
|
||||
if (! c->txbaud)
|
||||
return;
|
||||
|
||||
c->opt.rcor.dpll = on ? 1 : 0;
|
||||
cx_set_baud (c, c->txbaud);
|
||||
}
|
||||
|
||||
void cx_set_nrzi (cx_chan_t *c, int nrzi)
|
||||
{
|
||||
c->opt.rcor.encod = (nrzi ? ENCOD_NRZI : ENCOD_NRZ);
|
||||
outb (CAR(c->port), c->num & 3);
|
||||
outb (RCOR(c->port), BYTE c->opt.rcor);
|
||||
}
|
||||
|
||||
static int cx_send (cx_chan_t *c, char *data, int len,
|
||||
void *attachment)
|
||||
{
|
||||
unsigned char *buf;
|
||||
port_t cnt_port, sts_port;
|
||||
void **attp;
|
||||
|
||||
/* Set the current channel number. */
|
||||
outb (CAR(c->port), c->num & 3);
|
||||
|
||||
/* Determine the buffer order. */
|
||||
if (inb (DMABSTS(c->port)) & DMABSTS_NTBUF) {
|
||||
if (inb (BTBSTS(c->port)) & BSTS_OWN24) {
|
||||
buf = c->atbuf;
|
||||
cnt_port = ATBCNT(c->port);
|
||||
sts_port = ATBSTS(c->port);
|
||||
attp = &c->attach[0];
|
||||
} else {
|
||||
buf = c->btbuf;
|
||||
cnt_port = BTBCNT(c->port);
|
||||
sts_port = BTBSTS(c->port);
|
||||
attp = &c->attach[1];
|
||||
}
|
||||
} else {
|
||||
if (inb (ATBSTS(c->port)) & BSTS_OWN24) {
|
||||
buf = c->btbuf;
|
||||
cnt_port = BTBCNT(c->port);
|
||||
sts_port = BTBSTS(c->port);
|
||||
attp = &c->attach[1];
|
||||
} else {
|
||||
buf = c->atbuf;
|
||||
cnt_port = ATBCNT(c->port);
|
||||
sts_port = ATBSTS(c->port);
|
||||
attp = &c->attach[0];
|
||||
}
|
||||
}
|
||||
/* Is it busy? */
|
||||
if (inb (sts_port) & BSTS_OWN24)
|
||||
return -1;
|
||||
|
||||
memcpy (buf, data, len);
|
||||
*attp = attachment;
|
||||
|
||||
/* Start transmitter. */
|
||||
outw (cnt_port, len);
|
||||
outb (sts_port, BSTS_EOFR | BSTS_INTR | BSTS_OWN24);
|
||||
|
||||
/* Enable TXMPTY interrupt,
|
||||
* to catch the case when the second buffer is empty. */
|
||||
if (c->mode != M_ASYNC) {
|
||||
if ((inb(ATBSTS(c->port)) & BSTS_OWN24) &&
|
||||
(inb(BTBSTS(c->port)) & BSTS_OWN24)) {
|
||||
outb (IER(c->port), IER_RXD | IER_TXD | IER_TXMPTY);
|
||||
} else
|
||||
outb (IER(c->port), IER_RXD | IER_TXD);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Number of free buffs
|
||||
*/
|
||||
int cx_buf_free (cx_chan_t *c)
|
||||
{
|
||||
return ! (inb (ATBSTS(c->port)) & BSTS_OWN24) +
|
||||
! (inb (BTBSTS(c->port)) & BSTS_OWN24);
|
||||
}
|
||||
|
||||
/*
|
||||
* Send the data packet.
|
||||
*/
|
||||
int cx_send_packet (cx_chan_t *c, char *data, int len, void *attachment)
|
||||
{
|
||||
if (len >= DMABUFSZ)
|
||||
return -2;
|
||||
if (c->mode == M_ASYNC) {
|
||||
static char buf [DMABUFSZ];
|
||||
char *p, *t = buf;
|
||||
|
||||
/* Async -- double all nulls. */
|
||||
for (p=data; p < data+len && t < buf+DMABUFSZ-1; ++p)
|
||||
if ((*t++ = *p) == 0)
|
||||
*t++ = 0;
|
||||
return cx_send (c, buf, t-buf, attachment);
|
||||
}
|
||||
return cx_send (c, data, len, attachment);
|
||||
}
|
||||
|
||||
static int cx_receive_interrupt (cx_chan_t *c)
|
||||
{
|
||||
unsigned short risr;
|
||||
int len = 0, rbsz;
|
||||
|
||||
++c->rintr;
|
||||
risr = inw (RISR(c->port));
|
||||
|
||||
/* Compute optimal receiver buffer length */
|
||||
rbsz = cx_compute_buf_len(c);
|
||||
if (c->mode == M_ASYNC && (risr & RISA_TIMEOUT)) {
|
||||
unsigned long rcbadr = (unsigned short) inw (RCBADRL(c->port)) |
|
||||
(long) inw (RCBADRU(c->port)) << 16;
|
||||
unsigned char *buf = NULL;
|
||||
port_t cnt_port = 0, sts_port = 0;
|
||||
|
||||
if (rcbadr >= c->brphys && rcbadr < c->brphys+DMABUFSZ) {
|
||||
buf = c->brbuf;
|
||||
len = rcbadr - c->brphys;
|
||||
cnt_port = BRBCNT(c->port);
|
||||
sts_port = BRBSTS(c->port);
|
||||
} else if (rcbadr >= c->arphys && rcbadr < c->arphys+DMABUFSZ) {
|
||||
buf = c->arbuf;
|
||||
len = rcbadr - c->arphys;
|
||||
cnt_port = ARBCNT(c->port);
|
||||
sts_port = ARBSTS(c->port);
|
||||
}
|
||||
|
||||
if (len) {
|
||||
c->ibytes += len;
|
||||
c->received_data = buf;
|
||||
c->received_len = len;
|
||||
|
||||
/* Restart receiver. */
|
||||
outw (cnt_port, rbsz);
|
||||
outb (sts_port, BSTS_OWN24);
|
||||
}
|
||||
return (REOI_TERMBUFF);
|
||||
}
|
||||
|
||||
/* Receive errors. */
|
||||
if (risr & RIS_OVERRUN) {
|
||||
++c->ierrs;
|
||||
if (c->call_on_err)
|
||||
c->call_on_err (c, CX_OVERRUN);
|
||||
} else if (c->mode != M_ASYNC && (risr & RISH_CRCERR)) {
|
||||
++c->ierrs;
|
||||
if (c->call_on_err)
|
||||
c->call_on_err (c, CX_CRC);
|
||||
} else if (c->mode != M_ASYNC && (risr & (RISH_RXABORT | RISH_RESIND))) {
|
||||
++c->ierrs;
|
||||
if (c->call_on_err)
|
||||
c->call_on_err (c, CX_FRAME);
|
||||
} else if (c->mode == M_ASYNC && (risr & RISA_PARERR)) {
|
||||
++c->ierrs;
|
||||
if (c->call_on_err)
|
||||
c->call_on_err (c, CX_CRC);
|
||||
} else if (c->mode == M_ASYNC && (risr & RISA_FRERR)) {
|
||||
++c->ierrs;
|
||||
if (c->call_on_err)
|
||||
c->call_on_err (c, CX_FRAME);
|
||||
} else if (c->mode == M_ASYNC && (risr & RISA_BREAK)) {
|
||||
if (c->call_on_err)
|
||||
c->call_on_err (c, CX_BREAK);
|
||||
} else if (! (risr & RIS_EOBUF)) {
|
||||
++c->ierrs;
|
||||
} else {
|
||||
/* Handle received data. */
|
||||
len = (risr & RIS_BB) ? inw(BRBCNT(c->port)) : inw(ARBCNT(c->port));
|
||||
|
||||
if (len > DMABUFSZ) {
|
||||
/* Fatal error: actual DMA transfer size
|
||||
* exceeds our buffer size. It could be caused
|
||||
* by incorrectly programmed DMA register or
|
||||
* hardware fault. Possibly, should panic here. */
|
||||
len = DMABUFSZ;
|
||||
} else if (c->mode != M_ASYNC && ! (risr & RIS_EOFR)) {
|
||||
/* The received frame does not fit in the DMA buffer.
|
||||
* It could be caused by serial lie noise,
|
||||
* or if the peer has too big MTU. */
|
||||
if (! c->overflow) {
|
||||
if (c->call_on_err)
|
||||
c->call_on_err (c, CX_OVERFLOW);
|
||||
c->overflow = 1;
|
||||
++c->ierrs;
|
||||
}
|
||||
} else if (! c->overflow) {
|
||||
if (risr & RIS_BB) {
|
||||
c->received_data = c->brbuf;
|
||||
c->received_len = len;
|
||||
} else {
|
||||
c->received_data = c->arbuf;
|
||||
c->received_len = len;
|
||||
}
|
||||
if (c->mode != M_ASYNC)
|
||||
++c->ipkts;
|
||||
c->ibytes += len;
|
||||
} else
|
||||
c->overflow = 0;
|
||||
}
|
||||
|
||||
/* Restart receiver. */
|
||||
if (! (inb (ARBSTS(c->port)) & BSTS_OWN24)) {
|
||||
outw (ARBCNT(c->port), rbsz);
|
||||
outb (ARBSTS(c->port), BSTS_OWN24);
|
||||
}
|
||||
if (! (inb (BRBSTS(c->port)) & BSTS_OWN24)) {
|
||||
outw (BRBCNT(c->port), rbsz);
|
||||
outb (BRBSTS(c->port), BSTS_OWN24);
|
||||
}
|
||||
|
||||
/* Discard exception characters. */
|
||||
if ((risr & RISA_SCMASK) && c->aopt.cor2.ixon)
|
||||
return (REOI_DISCEXC);
|
||||
else
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void cx_transmit_interrupt (cx_chan_t *c)
|
||||
{
|
||||
unsigned char tisr;
|
||||
int len = 0;
|
||||
|
||||
++c->tintr;
|
||||
tisr = inb (TISR(c->port));
|
||||
if (tisr & TIS_UNDERRUN) { /* Transmit underrun error */
|
||||
if (c->call_on_err)
|
||||
c->call_on_err (c, CX_UNDERRUN);
|
||||
++c->oerrs;
|
||||
} else if (tisr & (TIS_EOBUF | TIS_TXEMPTY | TIS_TXDATA)) {
|
||||
/* Call processing function */
|
||||
if (tisr & TIS_BB) {
|
||||
len = inw(BTBCNT(c->port));
|
||||
if (c->call_on_tx)
|
||||
c->call_on_tx (c, c->attach[1], len);
|
||||
} else {
|
||||
len = inw(ATBCNT(c->port));
|
||||
if (c->call_on_tx)
|
||||
c->call_on_tx (c, c->attach[0], len);
|
||||
}
|
||||
if (c->mode != M_ASYNC && len != 0)
|
||||
++c->opkts;
|
||||
c->obytes += len;
|
||||
}
|
||||
|
||||
/* Enable TXMPTY interrupt,
|
||||
* to catch the case when the second buffer is empty. */
|
||||
if (c->mode != M_ASYNC) {
|
||||
if ((inb (ATBSTS(c->port)) & BSTS_OWN24) &&
|
||||
(inb (BTBSTS(c->port)) & BSTS_OWN24)) {
|
||||
outb (IER(c->port), IER_RXD | IER_TXD | IER_TXMPTY);
|
||||
} else
|
||||
outb (IER(c->port), IER_RXD | IER_TXD);
|
||||
}
|
||||
}
|
||||
|
||||
void cx_int_handler (cx_board_t *b)
|
||||
{
|
||||
unsigned char livr;
|
||||
cx_chan_t *c;
|
||||
|
||||
while (! (inw (BSR(b->port)) & BSR_NOINTR)) {
|
||||
/* Enter the interrupt context, using IACK bus cycle.
|
||||
Read the local interrupt vector register. */
|
||||
livr = inb (IACK(b->port, BRD_INTR_LEVEL));
|
||||
c = b->chan + (livr>>2 & 0xf);
|
||||
if (c->type == T_NONE)
|
||||
continue;
|
||||
switch (livr & 3) {
|
||||
case LIV_MODEM: /* modem interrupt */
|
||||
++c->mintr;
|
||||
if (c->call_on_msig)
|
||||
c->call_on_msig (c);
|
||||
outb (MEOIR(c->port), 0);
|
||||
break;
|
||||
case LIV_EXCEP: /* receive exception */
|
||||
case LIV_RXDATA: /* receive interrupt */
|
||||
outb (REOIR(c->port), cx_receive_interrupt (c));
|
||||
if (c->call_on_rx && c->received_data) {
|
||||
c->call_on_rx (c, c->received_data,
|
||||
c->received_len);
|
||||
c->received_data = 0;
|
||||
}
|
||||
break;
|
||||
case LIV_TXDATA: /* transmit interrupt */
|
||||
cx_transmit_interrupt (c);
|
||||
outb (TEOIR(c->port), 0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Register event processing functions
|
||||
*/
|
||||
void cx_register_transmit (cx_chan_t *c,
|
||||
void (*func) (cx_chan_t *c, void *attachment, int len))
|
||||
{
|
||||
c->call_on_tx = func;
|
||||
}
|
||||
|
||||
void cx_register_receive (cx_chan_t *c,
|
||||
void (*func) (cx_chan_t *c, char *data, int len))
|
||||
{
|
||||
c->call_on_rx = func;
|
||||
}
|
||||
|
||||
void cx_register_modem (cx_chan_t *c, void (*func) (cx_chan_t *c))
|
||||
{
|
||||
c->call_on_msig = func;
|
||||
}
|
||||
|
||||
void cx_register_error (cx_chan_t *c, void (*func) (cx_chan_t *c, int data))
|
||||
{
|
||||
c->call_on_err = func;
|
||||
}
|
||||
|
||||
/*
|
||||
* Async protocol functions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Enable/disable transmitter.
|
||||
*/
|
||||
void cx_transmitter_ctl (cx_chan_t *c,int start)
|
||||
{
|
||||
outb (CAR(c->port), c->num & 3);
|
||||
cx_cmd (c->port, start ? CCR_ENTX : CCR_DISTX);
|
||||
}
|
||||
|
||||
/*
|
||||
* Discard all data queued in transmitter.
|
||||
*/
|
||||
void cx_flush_transmit (cx_chan_t *c)
|
||||
{
|
||||
outb (CAR(c->port), c->num & 3);
|
||||
cx_cmd (c->port, CCR_CLRTX);
|
||||
}
|
||||
|
||||
/*
|
||||
* Send the XON/XOFF flow control symbol.
|
||||
*/
|
||||
void cx_xflow_ctl (cx_chan_t *c, int on)
|
||||
{
|
||||
outb (CAR(c->port), c->num & 3);
|
||||
outb (STCR(c->port), STC_SNDSPC | (on ? STC_SSPC_1 : STC_SSPC_2));
|
||||
}
|
||||
|
||||
/*
|
||||
* Send the break signal for a given number of milliseconds.
|
||||
*/
|
||||
void cx_send_break (cx_chan_t *c, int msec)
|
||||
{
|
||||
static unsigned char buf [128];
|
||||
unsigned char *p;
|
||||
|
||||
p = buf;
|
||||
*p++ = 0; /* extended transmit command */
|
||||
*p++ = 0x81; /* send break */
|
||||
|
||||
if (msec > 10000) /* max 10 seconds */
|
||||
msec = 10000;
|
||||
if (msec < 10) /* min 10 msec */
|
||||
msec = 10;
|
||||
while (msec > 0) {
|
||||
int ms = 250; /* 250 msec */
|
||||
if (ms > msec)
|
||||
ms = msec;
|
||||
msec -= ms;
|
||||
*p++ = 0; /* extended transmit command */
|
||||
*p++ = 0x82; /* insert delay */
|
||||
*p++ = ms;
|
||||
}
|
||||
*p++ = 0; /* extended transmit command */
|
||||
*p++ = 0x83; /* stop break */
|
||||
|
||||
cx_send (c, buf, p-buf, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set async parameters.
|
||||
*/
|
||||
void cx_set_async_param (cx_chan_t *c, int baud, int bits, int parity,
|
||||
int stop2, int ignpar, int rtscts,
|
||||
int ixon, int ixany, int symstart, int symstop)
|
||||
{
|
||||
int clock, period;
|
||||
cx_cor1_async_t cor1;
|
||||
|
||||
/* Set character length and parity mode. */
|
||||
BYTE cor1 = 0;
|
||||
cor1.charlen = bits - 1;
|
||||
cor1.parmode = parity ? PARM_NORMAL : PARM_NOPAR;
|
||||
cor1.parity = parity==1 ? PAR_ODD : PAR_EVEN;
|
||||
cor1.ignpar = ignpar ? 1 : 0;
|
||||
|
||||
/* Enable/disable hardware CTS. */
|
||||
c->aopt.cor2.ctsae = rtscts ? 1 : 0;
|
||||
|
||||
/* Enable extended transmit command mode.
|
||||
* Unfortunately, there is no other method for sending break. */
|
||||
c->aopt.cor2.etc = 1;
|
||||
|
||||
/* Enable/disable hardware XON/XOFF. */
|
||||
c->aopt.cor2.ixon = ixon ? 1 : 0;
|
||||
c->aopt.cor2.ixany = ixany ? 1 : 0;
|
||||
|
||||
/* Set the number of stop bits. */
|
||||
if (stop2)
|
||||
c->aopt.cor3.stopb = STOPB_2;
|
||||
else
|
||||
c->aopt.cor3.stopb = STOPB_1;
|
||||
|
||||
/* Disable/enable passing XON/XOFF chars to the host. */
|
||||
c->aopt.cor3.scde = ixon ? 1 : 0;
|
||||
c->aopt.cor3.flowct = ixon ? FLOWCC_NOTPASS : FLOWCC_PASS;
|
||||
|
||||
c->aopt.schr1 = symstart; /* XON */
|
||||
c->aopt.schr2 = symstop; /* XOFF */
|
||||
|
||||
/* Set current channel number. */
|
||||
outb (CAR(c->port), c->num & 3);
|
||||
|
||||
/* Set up clock values. */
|
||||
if (baud) {
|
||||
c->rxbaud = c->txbaud = baud;
|
||||
|
||||
/* Receiver. */
|
||||
cx_clock (c->oscfreq, c->rxbaud, &clock, &period);
|
||||
c->opt.rcor.clk = clock;
|
||||
outb (RCOR(c->port), BYTE c->opt.rcor);
|
||||
outb (RBPR(c->port), period);
|
||||
|
||||
/* Transmitter. */
|
||||
cx_clock (c->oscfreq, c->txbaud, &clock, &period);
|
||||
c->opt.tcor.clk = clock;
|
||||
c->opt.tcor.ext1x = 0;
|
||||
outb (TCOR(c->port), BYTE c->opt.tcor);
|
||||
outb (TBPR(c->port), period);
|
||||
}
|
||||
outb (COR2(c->port), BYTE c->aopt.cor2);
|
||||
outb (COR3(c->port), BYTE c->aopt.cor3);
|
||||
outb (SCHR1(c->port), c->aopt.schr1);
|
||||
outb (SCHR2(c->port), c->aopt.schr2);
|
||||
|
||||
if (BYTE c->aopt.cor1 != BYTE cor1) {
|
||||
BYTE c->aopt.cor1 = BYTE cor1;
|
||||
outb (COR1(c->port), BYTE c->aopt.cor1);
|
||||
/* Any change to COR1 require reinitialization. */
|
||||
/* Unfortunately, it may cause transmitter glitches... */
|
||||
cx_cmd (c->port, CCR_INITCH);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Set mode: M_ASYNC or M_HDLC.
|
||||
* Both receiver and transmitter are disabled.
|
||||
*/
|
||||
int cx_set_mode (cx_chan_t *c, int mode)
|
||||
{
|
||||
if (mode == M_HDLC) {
|
||||
if (c->type == T_ASYNC)
|
||||
return -1;
|
||||
|
||||
if (c->mode == M_HDLC)
|
||||
return 0;
|
||||
|
||||
c->mode = M_HDLC;
|
||||
} else if (mode == M_ASYNC) {
|
||||
if (c->type == T_SYNC_RS232 ||
|
||||
c->type == T_SYNC_V35 ||
|
||||
c->type == T_SYNC_RS449)
|
||||
return -1;
|
||||
|
||||
if (c->mode == M_ASYNC)
|
||||
return 0;
|
||||
|
||||
c->mode = M_ASYNC;
|
||||
c->opt.tcor.ext1x = 0;
|
||||
c->opt.tcor.llm = 0;
|
||||
c->opt.rcor.dpll = 0;
|
||||
c->opt.rcor.encod = ENCOD_NRZ;
|
||||
if (! c->txbaud || ! c->rxbaud)
|
||||
c->txbaud = c->rxbaud = 9600;
|
||||
} else
|
||||
return -1;
|
||||
|
||||
cx_setup_chan (c);
|
||||
cx_start_chan (c, 0, 0);
|
||||
cx_enable_receive (c, 0);
|
||||
cx_enable_transmit (c, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set port type for old models of Sigma
|
||||
*/
|
||||
void cx_set_port (cx_chan_t *c, int iftype)
|
||||
{
|
||||
if (c->board->type == B_SIGMA_XXX) {
|
||||
switch (c->num) {
|
||||
case 0:
|
||||
if ((c->board->if0type != 0) == (iftype != 0))
|
||||
return;
|
||||
c->board->if0type = iftype;
|
||||
c->board->bcr0 &= ~BCR0_UMASK;
|
||||
if (c->board->if0type &&
|
||||
(c->type==T_UNIV_RS449 || c->type==T_UNIV_V35))
|
||||
c->board->bcr0 |= BCR0_UI_RS449;
|
||||
outb (BCR0(c->board->port), c->board->bcr0);
|
||||
break;
|
||||
case 8:
|
||||
if ((c->board->if8type != 0) == (iftype != 0))
|
||||
return;
|
||||
c->board->if8type = iftype;
|
||||
c->board->bcr0b &= ~BCR0_UMASK;
|
||||
if (c->board->if8type &&
|
||||
(c->type==T_UNIV_RS449 || c->type==T_UNIV_V35))
|
||||
c->board->bcr0b |= BCR0_UI_RS449;
|
||||
outb (BCR0(c->board->port+0x10), c->board->bcr0b);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Get port type for old models of Sigma
|
||||
* -1 Fixed port type or auto detect
|
||||
* 0 RS232
|
||||
* 1 V35
|
||||
* 2 RS449
|
||||
*/
|
||||
int cx_get_port (cx_chan_t *c)
|
||||
{
|
||||
int iftype;
|
||||
|
||||
if (c->board->type == B_SIGMA_XXX) {
|
||||
switch (c->num) {
|
||||
case 0:
|
||||
iftype = c->board->if0type; break;
|
||||
case 8:
|
||||
iftype = c->board->if8type; break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (iftype)
|
||||
switch (c->type) {
|
||||
case T_UNIV_V35: return 1;
|
||||
case T_UNIV_RS449: return 2;
|
||||
default: return -1;
|
||||
}
|
||||
else
|
||||
return 0;
|
||||
} else
|
||||
return -1;
|
||||
}
|
||||
|
||||
void cx_intr_off (cx_board_t *b)
|
||||
{
|
||||
outb (BCR0(b->port), b->bcr0 & ~BCR0_IRQ_MASK);
|
||||
if (b->chan[8].port || b->chan[12].port)
|
||||
outb (BCR0(b->port+0x10), b->bcr0b & ~BCR0_IRQ_MASK);
|
||||
}
|
||||
|
||||
void cx_intr_on (cx_board_t *b)
|
||||
{
|
||||
outb (BCR0(b->port), b->bcr0);
|
||||
if (b->chan[8].port || b->chan[12].port)
|
||||
outb (BCR0(b->port+0x10), b->bcr0b);
|
||||
}
|
||||
|
||||
int cx_checkintr (cx_board_t *b)
|
||||
{
|
||||
return (!(inw (BSR(b->port)) & BSR_NOINTR));
|
||||
}
|
||||
@ -1,488 +0,0 @@
|
||||
/*-
|
||||
* Defines for Cronyx-Sigma adapter driver.
|
||||
*
|
||||
* Copyright (C) 1994-2001 Cronyx Engineering.
|
||||
* Author: Serge Vakulenko, <vak@cronyx.ru>
|
||||
*
|
||||
* Copyright (C) 1998-2003 Cronyx Engineering.
|
||||
* Author: Roman Kurakin, <rik@cronyx.ru>
|
||||
*
|
||||
* This software is distributed with NO WARRANTIES, not even the implied
|
||||
* warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* Authors grant any other persons or organisations permission to use
|
||||
* or modify this software as long as this message is kept with the software,
|
||||
* all derivative works or modified versions.
|
||||
*
|
||||
* Cronyx Id: cxddk.h,v 1.1.2.1 2003/11/12 17:13:41 rik Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef port_t
|
||||
# ifdef _M_ALPHA /* port address on Alpha under */
|
||||
# define port_t unsigned long /* Windows NT is 32 bit long */
|
||||
# else
|
||||
# define port_t unsigned short /* all other architectures */
|
||||
# endif /* have 16-bit port addresses */
|
||||
#endif
|
||||
|
||||
#define NBRD 3 /* the max number of installed boards */
|
||||
#define NPORT 32 /* the number of i/o ports per board */
|
||||
#define DMABUFSZ 1600
|
||||
|
||||
/*
|
||||
* Asynchronous channel mode -------------------------------------------------
|
||||
*/
|
||||
|
||||
/* Parity */
|
||||
#define PAR_EVEN 0 /* even parity */
|
||||
#define PAR_ODD 1 /* odd parity */
|
||||
|
||||
/* Parity mode */
|
||||
#define PARM_NOPAR 0 /* no parity */
|
||||
#define PARM_FORCE 1 /* force parity (odd = force 1, even = 0) */
|
||||
#define PARM_NORMAL 2 /* normal parity */
|
||||
|
||||
/* Flow control transparency mode */
|
||||
#define FLOWCC_PASS 0 /* pass flow ctl chars as exceptions */
|
||||
#define FLOWCC_NOTPASS 1 /* don't pass flow ctl chars to the host */
|
||||
|
||||
/* Stop bit length */
|
||||
#define STOPB_1 2 /* 1 stop bit */
|
||||
#define STOPB_15 3 /* 1.5 stop bits */
|
||||
#define STOPB_2 4 /* 2 stop bits */
|
||||
|
||||
/* Action on break condition */
|
||||
#define BRK_INTR 0 /* generate an exception interrupt */
|
||||
#define BRK_NULL 1 /* translate to a NULL character */
|
||||
#define BRK_RESERVED 2 /* reserved */
|
||||
#define BRK_DISCARD 3 /* discard character */
|
||||
|
||||
/* Parity/framing error actions */
|
||||
#define PERR_INTR 0 /* generate an exception interrupt */
|
||||
#define PERR_NULL 1 /* translate to a NULL character */
|
||||
#define PERR_IGNORE 2 /* ignore error; char passed as good data */
|
||||
#define PERR_DISCARD 3 /* discard error character */
|
||||
#define PERR_FFNULL 5 /* translate to FF NULL char */
|
||||
|
||||
typedef struct { /* async channel option register 1 */
|
||||
unsigned charlen : 4; /* character length, 5..8 */
|
||||
unsigned ignpar : 1; /* ignore parity */
|
||||
unsigned parmode : 2; /* parity mode */
|
||||
unsigned parity : 1; /* parity */
|
||||
} cx_cor1_async_t;
|
||||
|
||||
typedef struct { /* async channel option register 2 */
|
||||
unsigned dsrae : 1; /* DSR automatic enable */
|
||||
unsigned ctsae : 1; /* CTS automatic enable */
|
||||
unsigned rtsao : 1; /* RTS automatic output enable */
|
||||
unsigned rlm : 1; /* remote loopback mode enable */
|
||||
unsigned zero : 1;
|
||||
unsigned etc : 1; /* embedded transmitter cmd enable */
|
||||
unsigned ixon : 1; /* in-band XON/XOFF enable */
|
||||
unsigned ixany : 1; /* XON on any character */
|
||||
} cx_cor2_async_t;
|
||||
|
||||
typedef struct { /* async channel option register 3 */
|
||||
unsigned stopb : 3; /* stop bit length */
|
||||
unsigned zero : 1;
|
||||
unsigned scde : 1; /* special char detection enable */
|
||||
unsigned flowct : 1; /* flow control transparency mode */
|
||||
unsigned rngde : 1; /* range detect enable */
|
||||
unsigned escde : 1; /* extended spec. char detect enable */
|
||||
} cx_cor3_async_t;
|
||||
|
||||
typedef struct { /* async channel option register 6 */
|
||||
unsigned parerr : 3; /* parity/framing error actions */
|
||||
unsigned brk : 2; /* action on break condition */
|
||||
unsigned inlcr : 1; /* translate NL to CR on input */
|
||||
unsigned icrnl : 1; /* translate CR to NL on input */
|
||||
unsigned igncr : 1; /* discard CR on input */
|
||||
} cx_cor6_async_t;
|
||||
|
||||
typedef struct { /* async channel option register 7 */
|
||||
unsigned ocrnl : 1; /* translate CR to NL on output */
|
||||
unsigned onlcr : 1; /* translate NL to CR on output */
|
||||
unsigned zero : 3;
|
||||
unsigned fcerr : 1; /* process flow ctl err chars enable */
|
||||
unsigned lnext : 1; /* LNext option enable */
|
||||
unsigned istrip : 1; /* strip 8-bit on input */
|
||||
} cx_cor7_async_t;
|
||||
|
||||
typedef struct { /* async channel options */
|
||||
cx_cor1_async_t cor1; /* channel option register 1 */
|
||||
cx_cor2_async_t cor2; /* channel option register 2 */
|
||||
cx_cor3_async_t cor3; /* option register 3 */
|
||||
cx_cor6_async_t cor6; /* channel option register 6 */
|
||||
cx_cor7_async_t cor7; /* channel option register 7 */
|
||||
unsigned char schr1; /* special character register 1 (XON) */
|
||||
unsigned char schr2; /* special character register 2 (XOFF) */
|
||||
unsigned char schr3; /* special character register 3 */
|
||||
unsigned char schr4; /* special character register 4 */
|
||||
unsigned char scrl; /* special character range low */
|
||||
unsigned char scrh; /* special character range high */
|
||||
unsigned char lnxt; /* LNext character */
|
||||
} cx_opt_async_t;
|
||||
|
||||
/*
|
||||
* HDLC channel mode ---------------------------------------------------------
|
||||
*/
|
||||
/* Address field length option */
|
||||
#define AFLO_1OCT 0 /* address field is 1 octet in length */
|
||||
#define AFLO_2OCT 1 /* address field is 2 octet in length */
|
||||
|
||||
/* Clear detect for X.21 data transfer phase */
|
||||
#define CLRDET_DISABLE 0 /* clear detect disabled */
|
||||
#define CLRDET_ENABLE 1 /* clear detect enabled */
|
||||
|
||||
/* Addressing mode */
|
||||
#define ADMODE_NOADDR 0 /* no address */
|
||||
#define ADMODE_4_1 1 /* 4 * 1 byte */
|
||||
#define ADMODE_2_2 2 /* 2 * 2 byte */
|
||||
|
||||
/* FCS append */
|
||||
#define FCS_NOTPASS 0 /* receive CRC is not passed to the host */
|
||||
#define FCS_PASS 1 /* receive CRC is passed to the host */
|
||||
|
||||
/* CRC modes */
|
||||
#define CRC_INVERT 0 /* CRC is transmitted inverted (CRC V.41) */
|
||||
#define CRC_DONT_INVERT 1 /* CRC is not transmitted inverted (CRC-16) */
|
||||
|
||||
/* Send sync pattern */
|
||||
#define SYNC_00 0 /* send 00h as pad char (NRZI encoding) */
|
||||
#define SYNC_AA 1 /* send AAh (Manchester/NRZ encoding) */
|
||||
|
||||
/* FCS preset */
|
||||
#define FCSP_ONES 0 /* FCS is preset to all ones (CRC V.41) */
|
||||
#define FCSP_ZEROS 1 /* FCS is preset to all zeros (CRC-16) */
|
||||
|
||||
/* idle mode */
|
||||
#define IDLE_FLAG 0 /* idle in flag */
|
||||
#define IDLE_MARK 1 /* idle in mark */
|
||||
|
||||
/* CRC polynomial select */
|
||||
#define POLY_V41 0 /* x^16+x^12+x^5+1 (HDLC, preset to 1) */
|
||||
#define POLY_16 1 /* x^16+x^15+x^2+1 (bisync, preset to 0) */
|
||||
|
||||
typedef struct { /* hdlc channel option register 1 */
|
||||
unsigned ifflags : 4; /* number of inter-frame flags sent */
|
||||
unsigned admode : 2; /* addressing mode */
|
||||
unsigned clrdet : 1; /* clear detect for X.21 data transfer phase */
|
||||
unsigned aflo : 1; /* address field length option */
|
||||
} cx_cor1_hdlc_t;
|
||||
|
||||
typedef struct { /* hdlc channel option register 2 */
|
||||
unsigned dsrae : 1; /* DSR automatic enable */
|
||||
unsigned ctsae : 1; /* CTS automatic enable */
|
||||
unsigned rtsao : 1; /* RTS automatic output enable */
|
||||
unsigned zero1 : 1;
|
||||
unsigned crcninv : 1; /* CRC invertion option */
|
||||
unsigned zero2 : 1;
|
||||
unsigned fcsapd : 1; /* FCS append */
|
||||
unsigned zero3 : 1;
|
||||
} cx_cor2_hdlc_t;
|
||||
|
||||
typedef struct { /* hdlc channel option register 3 */
|
||||
unsigned padcnt : 3; /* pad character count */
|
||||
unsigned idle : 1; /* idle mode */
|
||||
unsigned nofcs : 1; /* FCS disable */
|
||||
unsigned fcspre : 1; /* FCS preset */
|
||||
unsigned syncpat : 1; /* send sync pattern */
|
||||
unsigned sndpad : 1; /* send pad characters before flag enable */
|
||||
} cx_cor3_hdlc_t;
|
||||
|
||||
typedef struct { /* hdlc channel options */
|
||||
cx_cor1_hdlc_t cor1; /* hdlc channel option register 1 */
|
||||
cx_cor2_hdlc_t cor2; /* hdlc channel option register 2 */
|
||||
cx_cor3_hdlc_t cor3; /* hdlc channel option register 3 */
|
||||
unsigned char rfar1; /* receive frame address register 1 */
|
||||
unsigned char rfar2; /* receive frame address register 2 */
|
||||
unsigned char rfar3; /* receive frame address register 3 */
|
||||
unsigned char rfar4; /* receive frame address register 4 */
|
||||
unsigned char cpsr; /* CRC polynomial select */
|
||||
} cx_opt_hdlc_t;
|
||||
|
||||
/*
|
||||
* CD2400 channel state structure --------------------------------------------
|
||||
*/
|
||||
|
||||
/* Signal encoding */
|
||||
#define ENCOD_NRZ 0 /* NRZ mode */
|
||||
#define ENCOD_NRZI 1 /* NRZI mode */
|
||||
#define ENCOD_MANCHESTER 2 /* Manchester mode */
|
||||
|
||||
/* Clock source */
|
||||
#define CLK_0 0 /* clock 0 */
|
||||
#define CLK_1 1 /* clock 1 */
|
||||
#define CLK_2 2 /* clock 2 */
|
||||
#define CLK_3 3 /* clock 3 */
|
||||
#define CLK_4 4 /* clock 4 */
|
||||
#define CLK_EXT 6 /* external clock */
|
||||
#define CLK_RCV 7 /* receive clock */
|
||||
|
||||
/* Board type */
|
||||
#define B_SIGMA_XXX 0 /* old Sigmas */
|
||||
#define B_SIGMA_2X 1 /* Sigma-22 */
|
||||
#define B_SIGMA_800 2 /* Sigma-800 */
|
||||
|
||||
/* Channel type */
|
||||
#define T_NONE 0 /* no channel */
|
||||
#define T_ASYNC 1 /* pure asynchronous RS-232 channel */
|
||||
#define T_SYNC_RS232 2 /* pure synchronous RS-232 channel */
|
||||
#define T_SYNC_V35 3 /* pure synchronous V.35 channel */
|
||||
#define T_SYNC_RS449 4 /* pure synchronous RS-449 channel */
|
||||
#define T_UNIV_RS232 5 /* sync/async RS-232 channel */
|
||||
#define T_UNIV_RS449 6 /* sync/async RS-232/RS-449 channel */
|
||||
#define T_UNIV_V35 7 /* sync/async RS-232/V.35 channel */
|
||||
#define T_UNIV 8 /* sync/async, unknown interface */
|
||||
|
||||
#define M_ASYNC 0 /* asynchronous mode */
|
||||
#define M_HDLC 1 /* bit-sync mode (HDLC) */
|
||||
|
||||
typedef struct { /* channel option register 4 */
|
||||
unsigned thr : 4; /* FIFO threshold */
|
||||
unsigned zero : 1;
|
||||
unsigned cts_zd : 1; /* detect 1 to 0 transition on the CTS */
|
||||
unsigned cd_zd : 1; /* detect 1 to 0 transition on the CD */
|
||||
unsigned dsr_zd : 1; /* detect 1 to 0 transition on the DSR */
|
||||
} cx_cor4_t;
|
||||
|
||||
typedef struct { /* channel option register 5 */
|
||||
unsigned rx_thr : 4; /* receive flow control FIFO threshold */
|
||||
unsigned zero : 1;
|
||||
unsigned cts_od : 1; /* detect 0 to 1 transition on the CTS */
|
||||
unsigned cd_od : 1; /* detect 0 to 1 transition on the CD */
|
||||
unsigned dsr_od : 1; /* detect 0 to 1 transition on the DSR */
|
||||
} cx_cor5_t;
|
||||
|
||||
typedef struct { /* receive clock option register */
|
||||
unsigned clk : 3; /* receive clock source */
|
||||
unsigned encod : 2; /* signal encoding NRZ/NRZI/Manchester */
|
||||
unsigned dpll : 1; /* DPLL enable */
|
||||
unsigned zero : 1;
|
||||
unsigned tlval : 1; /* transmit line value */
|
||||
} cx_rcor_t;
|
||||
|
||||
typedef struct { /* transmit clock option register */
|
||||
unsigned zero1 : 1;
|
||||
unsigned llm : 1; /* local loopback mode */
|
||||
unsigned zero2 : 1;
|
||||
unsigned ext1x : 1; /* external 1x clock mode */
|
||||
unsigned zero3 : 1;
|
||||
unsigned clk : 3; /* transmit clock source */
|
||||
} cx_tcor_t;
|
||||
|
||||
typedef struct {
|
||||
cx_cor4_t cor4; /* channel option register 4 */
|
||||
cx_cor5_t cor5; /* channel option register 5 */
|
||||
cx_rcor_t rcor; /* receive clock option register */
|
||||
cx_tcor_t tcor; /* transmit clock option register */
|
||||
} cx_chan_opt_t;
|
||||
|
||||
typedef enum { /* line break mode */
|
||||
BRK_IDLE, /* normal line mode */
|
||||
BRK_SEND, /* start sending break */
|
||||
BRK_STOP, /* stop sending break */
|
||||
} cx_break_t;
|
||||
|
||||
#define BUS_NORMAL 0 /* normal bus timing */
|
||||
#define BUS_FAST 1 /* fast bus timing (Sigma-22 and -800) */
|
||||
#define BUS_FAST2 2 /* fast bus timing (Sigma-800) */
|
||||
#define BUS_FAST3 3 /* fast bus timing (Sigma-800) */
|
||||
|
||||
typedef struct { /* board options */
|
||||
unsigned char fast; /* bus master timing (Sigma-22 and -800) */
|
||||
} cx_board_opt_t;
|
||||
|
||||
#define NCHIP 4 /* the number of controllers per board */
|
||||
#define NCHAN 16 /* the number of channels on the board */
|
||||
|
||||
typedef struct {
|
||||
unsigned char tbuffer [2] [DMABUFSZ];
|
||||
unsigned char rbuffer [2] [DMABUFSZ];
|
||||
} cx_buf_t;
|
||||
|
||||
typedef struct _cx_chan_t {
|
||||
struct _cx_board_t *board; /* board pointer */
|
||||
unsigned char type; /* channel type */
|
||||
unsigned char num; /* channel number, 0..15 */
|
||||
port_t port; /* base port address */
|
||||
unsigned long oscfreq; /* oscillator frequency in Hz */
|
||||
unsigned long rxbaud; /* receiver speed */
|
||||
unsigned long txbaud; /* transmitter speed */
|
||||
unsigned char mode; /* channel mode */
|
||||
cx_chan_opt_t opt; /* common channel options */
|
||||
cx_opt_async_t aopt; /* async mode options */
|
||||
cx_opt_hdlc_t hopt; /* hdlc mode options */
|
||||
unsigned char *arbuf; /* receiver A dma buffer */
|
||||
unsigned char *brbuf; /* receiver B dma buffer */
|
||||
unsigned char *atbuf; /* transmitter A dma buffer */
|
||||
unsigned char *btbuf; /* transmitter B dma buffer */
|
||||
unsigned long arphys; /* receiver A phys address */
|
||||
unsigned long brphys; /* receiver B phys address */
|
||||
unsigned long atphys; /* transmitter A phys address */
|
||||
unsigned long btphys; /* transmitter B phys address */
|
||||
unsigned char dtr; /* DTR signal value */
|
||||
unsigned char rts; /* RTS signal value */
|
||||
|
||||
unsigned long rintr; /* receive interrupts */
|
||||
unsigned long tintr; /* transmit interrupts */
|
||||
unsigned long mintr; /* modem interrupts */
|
||||
unsigned long ibytes; /* input bytes */
|
||||
unsigned long ipkts; /* input packets */
|
||||
unsigned long ierrs; /* input errors */
|
||||
unsigned long obytes; /* output bytes */
|
||||
unsigned long opkts; /* output packets */
|
||||
unsigned long oerrs; /* output errors */
|
||||
|
||||
void *sys;
|
||||
int debug;
|
||||
int debug_shadow;
|
||||
void *attach [2];
|
||||
char *received_data;
|
||||
int received_len;
|
||||
int overflow;
|
||||
|
||||
void (*call_on_rx) (struct _cx_chan_t*, char*, int);
|
||||
void (*call_on_tx) (struct _cx_chan_t*, void*, int);
|
||||
void (*call_on_msig) (struct _cx_chan_t*);
|
||||
void (*call_on_err) (struct _cx_chan_t*, int);
|
||||
|
||||
} cx_chan_t;
|
||||
|
||||
typedef struct _cx_board_t {
|
||||
unsigned char type; /* board type */
|
||||
unsigned char num; /* board number, 0..2 */
|
||||
port_t port; /* base board port, 0..3f0 */
|
||||
unsigned char irq; /* irq {3 5 7 10 11 12 15} */
|
||||
unsigned char dma; /* DMA request {5 6 7} */
|
||||
char name[16]; /* board version name */
|
||||
unsigned char nuniv; /* number of universal channels */
|
||||
unsigned char nsync; /* number of sync. channels */
|
||||
unsigned char nasync; /* number of async. channels */
|
||||
unsigned char if0type; /* chan0 interface RS-232/RS-449/V.35 */
|
||||
unsigned char if8type; /* chan8 interface RS-232/RS-449/V.35 */
|
||||
unsigned short bcr0; /* BCR0 image */
|
||||
unsigned short bcr0b; /* BCR0b image */
|
||||
unsigned short bcr1; /* BCR1 image */
|
||||
unsigned short bcr1b; /* BCR1b image */
|
||||
cx_board_opt_t opt; /* board options */
|
||||
cx_chan_t chan[NCHAN]; /* channel structures */
|
||||
void *sys;
|
||||
} cx_board_t;
|
||||
|
||||
extern long cx_rxbaud, cx_txbaud;
|
||||
extern int cx_univ_mode, cx_sync_mode, cx_iftype;
|
||||
|
||||
extern cx_chan_opt_t chan_opt_dflt; /* default mode-independent options */
|
||||
extern cx_opt_async_t opt_async_dflt; /* default async options */
|
||||
extern cx_opt_hdlc_t opt_hdlc_dflt; /* default hdlc options */
|
||||
extern cx_board_opt_t board_opt_dflt; /* default board options */
|
||||
|
||||
struct _cr_dat_tst;
|
||||
int cx_probe_board (port_t port, int irq, int dma);
|
||||
void cx_init (cx_board_t *b, int num, port_t port, int irq, int dma);
|
||||
void cx_init_board (cx_board_t *b, int num, port_t port, int irq, int dma,
|
||||
int chain, int rev, int osc, int mod, int rev2, int osc2, int mod2);
|
||||
void cx_init_2x (cx_board_t *b, int num, port_t port, int irq, int dma,
|
||||
int rev, int osc);
|
||||
void cx_init_800 (cx_board_t *b, int num, port_t port, int irq, int dma,
|
||||
int chain);
|
||||
int cx_download (port_t port, const unsigned char *firmware, long bits,
|
||||
const struct _cr_dat_tst *tst);
|
||||
int cx_setup_board (cx_board_t *b, const unsigned char *firmware,
|
||||
long bits, const struct _cr_dat_tst *tst);
|
||||
void cx_setup_chan (cx_chan_t *c);
|
||||
void cx_update_chan (cx_chan_t *c);
|
||||
void cx_set_dtr (cx_chan_t *c, int on);
|
||||
void cx_set_rts (cx_chan_t *c, int on);
|
||||
void cx_led (cx_board_t *b, int on);
|
||||
void cx_cmd (port_t base, int cmd);
|
||||
void cx_disable_dma (cx_board_t *b);
|
||||
void cx_reinit_board (cx_board_t *b);
|
||||
int cx_get_dsr (cx_chan_t *c);
|
||||
int cx_get_cts (cx_chan_t *c);
|
||||
int cx_get_cd (cx_chan_t *c);
|
||||
void cx_clock (long hz, long ba, int *clk, int *div);
|
||||
|
||||
/* DDK errors */
|
||||
#define CX_FRAME 1
|
||||
#define CX_CRC 2
|
||||
#define CX_OVERRUN 3
|
||||
#define CX_OVERFLOW 4
|
||||
#define CX_UNDERRUN 5
|
||||
#define CX_BREAK 6
|
||||
|
||||
/* clock sources */
|
||||
#define CX_CLK_INT 0
|
||||
#define CX_CLK_EXT 6
|
||||
#define CX_CLK_RCV 7
|
||||
#define CX_CLK_DPLL 8
|
||||
#define CX_CLK_DPLL_EXT 14
|
||||
|
||||
/* functions dealing with interrupt vector in DOS */
|
||||
#if defined (MSDOS) || defined (__MSDOS__)
|
||||
int ddk_int_alloc (int irq, void (*func)(), void *arg);
|
||||
int ddk_int_restore (int irq);
|
||||
#endif
|
||||
|
||||
int cx_probe_irq (cx_board_t *b, int irq);
|
||||
void cx_int_handler (cx_board_t *b);
|
||||
|
||||
int cx_find (port_t *board_ports);
|
||||
int cx_open_board (cx_board_t *b, int num, port_t port, int irq, int dma);
|
||||
void cx_close_board (cx_board_t *b);
|
||||
|
||||
void cx_start_chan (cx_chan_t *c, cx_buf_t *cb, unsigned long phys);
|
||||
|
||||
/*
|
||||
Set port type for old models of Sigma
|
||||
*/
|
||||
void cx_set_port (cx_chan_t *c, int iftype);
|
||||
|
||||
/*
|
||||
Get port type for old models of Sigma
|
||||
-1 Fixed port type or auto detect
|
||||
0 RS232
|
||||
1 V35
|
||||
2 RS449
|
||||
*/
|
||||
int cx_get_port (cx_chan_t *c);
|
||||
|
||||
void cx_enable_receive (cx_chan_t *c, int on);
|
||||
void cx_enable_transmit (cx_chan_t *c, int on);
|
||||
int cx_receive_enabled (cx_chan_t *c);
|
||||
int cx_transmit_enabled (cx_chan_t *c);
|
||||
|
||||
void cx_set_baud (cx_chan_t *, unsigned long baud);
|
||||
int cx_set_mode (cx_chan_t *c, int mode);
|
||||
void cx_set_loop (cx_chan_t *c, int on);
|
||||
void cx_set_nrzi (cx_chan_t *c, int nrzi);
|
||||
void cx_set_dpll (cx_chan_t *c, int on);
|
||||
|
||||
unsigned long cx_get_baud (cx_chan_t *c);
|
||||
int cx_get_loop (cx_chan_t *c);
|
||||
int cx_get_nrzi (cx_chan_t *c);
|
||||
int cx_get_dpll (cx_chan_t *c);
|
||||
|
||||
int cx_send_packet (cx_chan_t *c, char *data, int len, void *attachment);
|
||||
int cx_buf_free (cx_chan_t *c);
|
||||
|
||||
void cx_register_transmit (cx_chan_t *c,
|
||||
void (*func) (cx_chan_t *c, void *attachment, int len));
|
||||
void cx_register_receive (cx_chan_t *c,
|
||||
void (*func) (cx_chan_t *c, char *data, int len));
|
||||
void cx_register_modem (cx_chan_t *c, void (*func) (cx_chan_t *c));
|
||||
void cx_register_error (cx_chan_t *c, void (*func) (cx_chan_t *c, int data));
|
||||
void cx_intr_off (cx_board_t *b);
|
||||
void cx_intr_on (cx_board_t *b);
|
||||
int cx_checkintr (cx_board_t *b);
|
||||
|
||||
/* Async functions */
|
||||
void cx_transmitter_ctl (cx_chan_t *c, int start);
|
||||
void cx_flush_transmit (cx_chan_t *c);
|
||||
void cx_xflow_ctl (cx_chan_t *c, int on);
|
||||
void cx_send_break (cx_chan_t *c, int msec);
|
||||
void cx_set_async_param (cx_chan_t *c, int baud, int bits, int parity,
|
||||
int stop2, int ignpar, int rtscts,
|
||||
int ixon, int ixany, int symstart, int symstop);
|
||||
@ -1,486 +0,0 @@
|
||||
/*-
|
||||
* Defines for Cronyx-Sigma adapter, based on Cirrus Logic multiprotocol
|
||||
* controller RISC processor CL-CD2400/2401.
|
||||
*
|
||||
* Copyright (C) 1994-2000 Cronyx Engineering.
|
||||
* Author: Serge Vakulenko, <vak@cronyx.ru>
|
||||
*
|
||||
* This software is distributed with NO WARRANTIES, not even the implied
|
||||
* warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* Authors grant any other persons or organisations permission to use
|
||||
* or modify this software as long as this message is kept with the software,
|
||||
* all derivative works or modified versions.
|
||||
*
|
||||
* Cronyx Id: cxreg.h,v 1.1.2.1 2003/11/12 17:13:41 rik Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#define REVCL_MIN 7 /* CD2400 min. revision number G */
|
||||
#define REVCL_MAX 13 /* CD2400 max. revision number M */
|
||||
#define REVCL31_MIN 0x33 /* CD2431 min. revision number C */
|
||||
#define REVCL31_MAX 0x34 /* CD2431 max. revision number D */
|
||||
|
||||
#define BRD_INTR_LEVEL 0x5a /* interrupt level (arbitrary PILR value) */
|
||||
|
||||
#define CS0(p) ((p) | 0x8000) /* chip select 0 */
|
||||
#define CS1(p) ((p) | 0xc000) /* chip select 1 */
|
||||
#define CS1A(p) ((p) | 0x8010) /* chip select 1 for agp-compatible models */
|
||||
#define BSR(p) (p) /* board status register, read only */
|
||||
#define BCR0(p) (p) /* board command register 0, write only */
|
||||
#define BCR1(p) ((p) | 0x2000) /* board command register 1, write only */
|
||||
|
||||
/*
|
||||
* For Sigma-800 only.
|
||||
*/
|
||||
#define BDET(p) ((p) | 0x2000) /* board detection register, read only */
|
||||
#define BCR2(p) ((p) | 0x4000) /* board command register 2, write only */
|
||||
|
||||
/*
|
||||
* Chip register address, B is chip base port, R is chip register number.
|
||||
*/
|
||||
#define R(b,r) ((b) | (((r)<<6 & 0x3c00) | ((r) & 0xf)))
|
||||
|
||||
/*
|
||||
* Interrupt acknowledge register, P is board port, L is interrupt level,
|
||||
* as prodrammed in PILR.
|
||||
*/
|
||||
#define IACK(p,l) (R(p,l) | 0x4000)
|
||||
|
||||
/*
|
||||
* Global registers.
|
||||
*/
|
||||
#define GFRCR(b) R(b,0x82) /* global firmware revision code register */
|
||||
#define CAR(b) R(b,0xec) /* channel access register */
|
||||
|
||||
/*
|
||||
* Option registers.
|
||||
*/
|
||||
#define CMR(b) R(b,0x18) /* channel mode register */
|
||||
#define COR1(b) R(b,0x13) /* channel option register 1 */
|
||||
#define COR2(b) R(b,0x14) /* channel option register 2 */
|
||||
#define COR3(b) R(b,0x15) /* channel option register 3 */
|
||||
#define COR4(b) R(b,0x16) /* channel option register 4 */
|
||||
#define COR5(b) R(b,0x17) /* channel option register 5 */
|
||||
#define COR6(b) R(b,0x1b) /* channel option register 6 */
|
||||
#define COR7(b) R(b,0x04) /* channel option register 7 */
|
||||
#define SCHR1(b) R(b,0x1c) /* special character register 1 */
|
||||
#define SCHR2(b) R(b,0x1d) /* special character register 2 */
|
||||
#define SCHR3(b) R(b,0x1e) /* special character register 3 */
|
||||
#define SCHR4(b) R(b,0x1f) /* special character register 4 */
|
||||
#define SCRL(b) R(b,0x20) /* special character range low */
|
||||
#define SCRH(b) R(b,0x21) /* special character range high */
|
||||
#define LNXT(b) R(b,0x2d) /* LNext character */
|
||||
#define RFAR1(b) R(b,0x1c) /* receive frame address register 1 */
|
||||
#define RFAR2(b) R(b,0x1d) /* receive frame address register 2 */
|
||||
#define RFAR3(b) R(b,0x1e) /* receive frame address register 3 */
|
||||
#define RFAR4(b) R(b,0x1f) /* receive frame address register 4 */
|
||||
#define CPSR(b) R(b,0xd4) /* CRC polynomial select register */
|
||||
|
||||
/*
|
||||
* Bit rate and clock option registers.
|
||||
*/
|
||||
#define RBPR(b) R(b,0xc9) /* receive baud rate period register */
|
||||
#define RCOR(b) R(b,0xca) /* receive clock option register */
|
||||
#define TBPR(b) R(b,0xc1) /* transmit baud rate period register */
|
||||
#define TCOR(b) R(b,0xc2) /* receive clock option register */
|
||||
|
||||
/*
|
||||
* Channel command and status registers.
|
||||
*/
|
||||
#define CCR(b) R(b,0x10) /* channel command register */
|
||||
#define STCR(b) R(b,0x11) /* special transmit command register */
|
||||
#define CSR(b) R(b,0x19) /* channel status register */
|
||||
#define MSVR(b) R(b,0xdc) /* modem signal value register */
|
||||
#define MSVR_RTS(b) R(b,0xdc) /* modem RTS setup register */
|
||||
#define MSVR_DTR(b) R(b,0xdd) /* modem DTR setup register */
|
||||
|
||||
/*
|
||||
* Interrupt registers.
|
||||
*/
|
||||
#define LIVR(b) R(b,0x0a) /* local interrupt vector register */
|
||||
#define IER(b) R(b,0x12) /* interrupt enable register */
|
||||
#define LICR(b) R(b,0x25) /* local interrupting channel register */
|
||||
#define STK(b) R(b,0xe0) /* stack register */
|
||||
|
||||
/*
|
||||
* Receive interrupt registers.
|
||||
*/
|
||||
#define RPILR(b) R(b,0xe3) /* receive priority interrupt level register */
|
||||
#define RIR(b) R(b,0xef) /* receive interrupt register */
|
||||
#define RISR(b) R(b,0x8a) /* receive interrupt status register */
|
||||
#define RISRL(b) R(b,0x8a) /* receive interrupt status register low */
|
||||
#define RISRH(b) R(b,0x8b) /* receive interrupt status register high */
|
||||
#define RFOC(b) R(b,0x33) /* receive FIFO output count */
|
||||
#define RDR(b) R(b,0xf8) /* receive data register */
|
||||
#define REOIR(b) R(b,0x87) /* receive end of interrupt register */
|
||||
|
||||
/*
|
||||
* Transmit interrupt registers.
|
||||
*/
|
||||
#define TPILR(b) R(b,0xe2) /* transmit priority interrupt level reg */
|
||||
#define TIR(b) R(b,0xee) /* transmit interrupt register */
|
||||
#define TISR(b) R(b,0x89) /* transmit interrupt status register */
|
||||
#define TFTC(b) R(b,0x83) /* transmit FIFO transfer count */
|
||||
#define TDR(b) R(b,0xf8) /* transmit data register */
|
||||
#define TEOIR(b) R(b,0x86) /* transmit end of interrupt register */
|
||||
|
||||
/*
|
||||
* Modem interrupt registers.
|
||||
*/
|
||||
#define MPILR(b) R(b,0xe1) /* modem priority interrupt level register */
|
||||
#define MIR(b) R(b,0xed) /* modem interrupt register */
|
||||
#define MISR(b) R(b,0x88) /* modem/timer interrupt status register */
|
||||
#define MEOIR(b) R(b,0x85) /* modem end of interrupt register */
|
||||
|
||||
/*
|
||||
* DMA registers.
|
||||
*/
|
||||
#define DMR(b) R(b,0xf4) /* DMA mode register */
|
||||
#define BERCNT(b) R(b,0x8d) /* bus error retry count */
|
||||
#define DMABSTS(b) R(b,0x1a) /* DMA buffer status */
|
||||
|
||||
/*
|
||||
* DMA receive registers.
|
||||
*/
|
||||
#define ARBADRL(b) R(b,0x40) /* A receive buffer address lower */
|
||||
#define ARBADRU(b) R(b,0x42) /* A receive buffer address upper */
|
||||
#define BRBADRL(b) R(b,0x44) /* B receive buffer address lower */
|
||||
#define BRBADRU(b) R(b,0x46) /* B receive buffer address upper */
|
||||
#define ARBCNT(b) R(b,0x48) /* A receive buffer byte count */
|
||||
#define BRBCNT(b) R(b,0x4a) /* B receive buffer byte count */
|
||||
#define ARBSTS(b) R(b,0x4c) /* A receive buffer status */
|
||||
#define BRBSTS(b) R(b,0x4d) /* B receive buffer status */
|
||||
#define RCBADRL(b) R(b,0x3c) /* receive current buffer address lower */
|
||||
#define RCBADRU(b) R(b,0x3e) /* receive current buffer address upper */
|
||||
|
||||
/*
|
||||
* DMA transmit registers.
|
||||
*/
|
||||
#define ATBADRL(b) R(b,0x50) /* A transmit buffer address lower */
|
||||
#define ATBADRU(b) R(b,0x52) /* A transmit buffer address upper */
|
||||
#define BTBADRL(b) R(b,0x54) /* B transmit buffer address lower */
|
||||
#define BTBADRU(b) R(b,0x56) /* B transmit buffer address upper */
|
||||
#define ATBCNT(b) R(b,0x58) /* A transmit buffer byte count */
|
||||
#define BTBCNT(b) R(b,0x5a) /* B transmit buffer byte count */
|
||||
#define ATBSTS(b) R(b,0x5c) /* A transmit buffer status */
|
||||
#define BTBSTS(b) R(b,0x5d) /* B transmit buffer status */
|
||||
#define TCBADRL(b) R(b,0x38) /* transmit current buffer address lower */
|
||||
#define TCBADRU(b) R(b,0x3a) /* transmit current buffer address upper */
|
||||
|
||||
/*
|
||||
* Timer registers.
|
||||
*/
|
||||
#define TPR(b) R(b,0xd8) /* timer period register */
|
||||
#define RTPR(b) R(b,0x26) /* receive timeout period register */
|
||||
#define RTPRL(b) R(b,0x26) /* receive timeout period register low */
|
||||
#define RTPTH(b) R(b,0x27) /* receive timeout period register high */
|
||||
#define GT1(b) R(b,0x28) /* general timer 1 */
|
||||
#define GT1L(b) R(b,0x28) /* general timer 1 low */
|
||||
#define GT1H(b) R(b,0x29) /* general timer 1 high */
|
||||
#define GT2(b) R(b,0x2a) /* general timer 2 */
|
||||
#define TTR(b) R(b,0x2a) /* transmit timer register */
|
||||
|
||||
/*
|
||||
* Board status register bits, for all models.
|
||||
*/
|
||||
#define BSR_NOINTR 0x01 /* no interrupt pending flag */
|
||||
#define BSR_NOCHAIN 0x80 /* no daisy chained board, all but Sigma-22 */
|
||||
|
||||
/*
|
||||
* For old Sigmas only.
|
||||
*/
|
||||
#define BSR_VAR_MASK 0x66 /* adapter variant mask */
|
||||
#define BSR_OSC_MASK 0x18 /* oscillator frequency mask */
|
||||
#define BSR_OSC_20 0x18 /* 20 MHz */
|
||||
#define BSR_OSC_18432 0x10 /* 18.432 MHz */
|
||||
|
||||
#define BSR_NODSR(n) (0x100 << (n)) /* DSR from channels 0-3, inverted */
|
||||
#define BSR_NOCD(n) (0x1000 << (n)) /* CD from channels 0-3, inverted */
|
||||
|
||||
/*
|
||||
* Board status register bits for Sigma-2x.
|
||||
*/
|
||||
#define BSR2X_OSC_33 0x08 /* oscillator 33/20 MHz bit */
|
||||
#define BSR2X_VAR_MASK 0x30 /* Sigma-2x variant mask */
|
||||
|
||||
/*
|
||||
* Board status register bits for Sigma-800.
|
||||
*/
|
||||
#define BSR800_NU0 0x02 /* no channels 0-3 installed */
|
||||
#define BSR800_NU1 0x04 /* no channels 4-7 installed */
|
||||
#define BSR800_LERR 0x08 /* firmware load error */
|
||||
#define BSR800_MIRQ 0x10 /* modem IRQ active */
|
||||
#define BSR800_TIRQ 0x20 /* transmit IRQ active */
|
||||
#define BSR800_RIRQ 0x40 /* receive IRQ active */
|
||||
|
||||
#define BDET_IB 0x08 /* identification bit */
|
||||
#define BDET_IB_NEG 0x80 /* negated identification bit */
|
||||
|
||||
/*
|
||||
* Sigma-800 control register 2 bits.
|
||||
*/
|
||||
#define BCR2_BUS0 0x01 /* bus timing control */
|
||||
#define BCR2_BUS1 0x02 /* bus timing control */
|
||||
#define BCR2_TMS 0x08 /* firmware download signal */
|
||||
#define BCR2_TDI 0x80 /* firmware download signal */
|
||||
|
||||
/*
|
||||
* Board revision mask.
|
||||
*/
|
||||
#define BSR_REV_MASK (BSR_OSC_MASK|BSR_VAR_MASK|BSR_NOCHAIN)
|
||||
#define BSR2X_REV_MASK (BSR_OSC_MASK|BSR_VAR_MASK)
|
||||
|
||||
/*
|
||||
* Sigma-2x variants.
|
||||
*/
|
||||
#define CRONYX_22 0x20
|
||||
#define CRONYX_24 0x00
|
||||
|
||||
/*
|
||||
* Sigma-XXX variants.
|
||||
*/
|
||||
#define CRONYX_100 0x64
|
||||
#define CRONYX_400 0x62
|
||||
#define CRONYX_500 0x60
|
||||
#define CRONYX_410 0x24
|
||||
#define CRONYX_810 0x20
|
||||
#define CRONYX_410s 0x04
|
||||
#define CRONYX_810s 0x00
|
||||
#define CRONYX_440 0x44
|
||||
#define CRONYX_840 0x40
|
||||
#define CRONYX_401 0x26
|
||||
#define CRONYX_801 0x22
|
||||
#define CRONYX_401s 0x06
|
||||
#define CRONYX_801s 0x02
|
||||
#define CRONYX_404 0x46
|
||||
#define CRONYX_703 0x42
|
||||
|
||||
/*
|
||||
* Board control register 0 bits.
|
||||
*/
|
||||
#define BCR0_IRQ_DIS 0x00 /* no interrupt generated */
|
||||
#define BCR0_IRQ_3 0x01 /* select IRQ number 3 */
|
||||
#define BCR0_IRQ_5 0x02 /* select IRQ number 5 */
|
||||
#define BCR0_IRQ_7 0x03 /* select IRQ number 7 */
|
||||
#define BCR0_IRQ_10 0x04 /* select IRQ number 10 */
|
||||
#define BCR0_IRQ_11 0x05 /* select IRQ number 11 */
|
||||
#define BCR0_IRQ_12 0x06 /* select IRQ number 12 */
|
||||
#define BCR0_IRQ_15 0x07 /* select IRQ number 15 */
|
||||
#define BCR0_IRQ_MASK 0x07 /* irq select mask */
|
||||
|
||||
#define BCR0_DMA_DIS 0x00 /* no interrupt generated */
|
||||
#define BCR0_DMA_5 0x10 /* select DMA channel 5 */
|
||||
#define BCR0_DMA_6 0x20 /* select DMA channel 6 */
|
||||
#define BCR0_DMA_7 0x30 /* select DMA channel 7 */
|
||||
#define BCR0_DMA_MASK 0x30 /* drq select mask */
|
||||
|
||||
/* For old Sigmas only. */
|
||||
#define BCR0_NORESET 0x08 /* CD2400 reset flag (inverted) */
|
||||
|
||||
#define BCR0_UM_ASYNC 0x00 /* channel 0 mode - async */
|
||||
#define BCR0_UM_SYNC 0x80 /* channel 0 mode - sync */
|
||||
#define BCR0_UI_RS232 0x00 /* channel 0 interface - RS-232 */
|
||||
#define BCR0_UI_RS449 0x40 /* channel 0 interface - RS-449/V.35 */
|
||||
#define BCR0_UMASK 0xc0 /* channel 0 interface mask */
|
||||
|
||||
/* For Sigma-22 only. */
|
||||
#define BCR02X_FAST 0x40 /* fast bus timing */
|
||||
#define BCR02X_LED 0x80 /* LED control */
|
||||
|
||||
/* For Sigma-800 only. */
|
||||
#define BCR0800_TCK 0x80 /* firmware download signal */
|
||||
|
||||
/*
|
||||
* Board control register 1 bits.
|
||||
*/
|
||||
/* For old Sigmas only. */
|
||||
#define BCR1_DTR(n) (0x100 << (n)) /* DTR for channels 0-3 sync */
|
||||
|
||||
/* For Sigma-800 only. */
|
||||
#define BCR1800_DTR(n) (1 << ((n) & 7)) /* DTR for channels 0-7 sync */
|
||||
|
||||
/*
|
||||
* Channel commands (CCR).
|
||||
*/
|
||||
#define CCR_CLRCH 0x40 /* clear channel */
|
||||
#define CCR_INITCH 0x20 /* initialize channel */
|
||||
#define CCR_RSTALL 0x10 /* reset all channels */
|
||||
#define CCR_ENTX 0x08 /* enable transmitter */
|
||||
#define CCR_DISTX 0x04 /* disable transmitter */
|
||||
#define CCR_ENRX 0x02 /* enable receiver */
|
||||
#define CCR_DISRX 0x01 /* disable receiver */
|
||||
#define CCR_CLRT1 0xc0 /* clear timer 1 */
|
||||
#define CCR_CLRT2 0xa0 /* clear timer 2 */
|
||||
#define CCR_CLRRCV 0x90 /* clear receiver */
|
||||
#define CCR_CLRTX 0x88 /* clear transmitter */
|
||||
|
||||
/*
|
||||
* Interrupt enable register (IER) bits.
|
||||
*/
|
||||
#define IER_MDM 0x80 /* modem status changed */
|
||||
#define IER_RET 0x20 /* receive exception timeout */
|
||||
#define IER_RXD 0x08 /* data received */
|
||||
#define IER_TIMER 0x04 /* timer expired */
|
||||
#define IER_TXMPTY 0x02 /* transmitter empty */
|
||||
#define IER_TXD 0x01 /* data transmitted */
|
||||
|
||||
/*
|
||||
* Modem signal values register bits (MSVR).
|
||||
*/
|
||||
#define MSV_DSR 0x80 /* state of Data Set Ready input */
|
||||
#define MSV_CD 0x40 /* state of Carrier Detect input */
|
||||
#define MSV_CTS 0x20 /* state of Clear to Send input */
|
||||
#define MSV_TXCOUT 0x10 /* TXCout/DTR pin output flag */
|
||||
#define MSV_PORTID 0x04 /* device is CL-CD2401 (not 2400) */
|
||||
#define MSV_DTR 0x02 /* state of Data Terminal Ready output */
|
||||
#define MSV_RTS 0x01 /* state of Request to Send output */
|
||||
#define MSV_BITS "\20\1rts\2dtr\3cd2400\5txcout\6cts\7cd\10dsr"
|
||||
|
||||
/*
|
||||
* DMA buffer status register bits (DMABSTS).
|
||||
*/
|
||||
#define DMABSTS_TDALIGN 0x80 /* internal data alignment in transmit FIFO */
|
||||
#define DMABSTS_RSTAPD 0x40 /* reset append mode */
|
||||
#define DMABSTS_CRTTBUF 0x20 /* internal current transmit buffer in use */
|
||||
#define DMABSTS_APPEND 0x10 /* append buffer is in use */
|
||||
#define DMABSTS_NTBUF 0x08 /* next transmit buffer is B (not A) */
|
||||
#define DMABSTS_TBUSY 0x04 /* current transmit buffer is in use */
|
||||
#define DMABSTS_NRBUF 0x02 /* next receive buffer is B (not A) */
|
||||
#define DMABSTS_RBUSY 0x01 /* current receive buffer is in use */
|
||||
|
||||
/*
|
||||
* Buffer status register bits ([AB][RT]BSTS).
|
||||
*/
|
||||
#define BSTS_BUSERR 0x80 /* bus error */
|
||||
#define BSTS_EOFR 0x40 /* end of frame */
|
||||
#define BSTS_EOBUF 0x20 /* end of buffer */
|
||||
#define BSTS_APPEND 0x08 /* append mode */
|
||||
#define BSTS_INTR 0x02 /* interrupt required */
|
||||
#define BSTS_OWN24 0x01 /* buffer is (free to be) used by CD2400 */
|
||||
#define BSTS_BITS "\20\1own24\2intr\4append\6eobuf\7eofr\10buserr"
|
||||
|
||||
/*
|
||||
* Receive interrupt status register (RISR) bits.
|
||||
*/
|
||||
#define RIS_OVERRUN 0x0008 /* overrun error */
|
||||
#define RIS_BB 0x0800 /* buffer B status (not A) */
|
||||
#define RIS_EOBUF 0x2000 /* end of buffer reached */
|
||||
#define RIS_EOFR 0x4000 /* frame reception complete */
|
||||
#define RIS_BUSERR 0x8000 /* bus error */
|
||||
|
||||
#define RISH_CLRDCT 0x0001 /* X.21 clear detect */
|
||||
#define RISH_RESIND 0x0004 /* residual indication */
|
||||
#define RISH_CRCERR 0x0010 /* CRC error */
|
||||
#define RISH_RXABORT 0x0020 /* abort sequence received */
|
||||
#define RISH_EOFR 0x0040 /* complete frame received */
|
||||
#define RISH_BITS "\20\1clrdct\3resind\4overrun\5crcerr\6rxabort\7eofr\14bb\16eobuf\17eofr\20buserr"
|
||||
|
||||
#define RISA_BREAK 0x0001 /* break signal detected */
|
||||
#define RISA_FRERR 0x0002 /* frame error (bad stop bits) */
|
||||
#define RISA_PARERR 0x0004 /* parity error */
|
||||
#define RISA_SCMASK 0x0070 /* special character detect mask */
|
||||
#define RISA_SCHR1 0x0010 /* special character 1 detected */
|
||||
#define RISA_SCHR2 0x0020 /* special character 2 detected */
|
||||
#define RISA_SCHR3 0x0030 /* special character 3 detected */
|
||||
#define RISA_SCHR4 0x0040 /* special character 4 detected */
|
||||
#define RISA_SCRANGE 0x0070 /* special character in range detected */
|
||||
#define RISA_TIMEOUT 0x0080 /* receive timeout, no data */
|
||||
#define RISA_BITS "\20\1break\2frerr\3parerr\4overrun\5schr1\6schr2\7schr4\10timeout\14bb\16eobuf\17eofr\20buserr"
|
||||
|
||||
#define RISB_CRCERR 0x0010 /* CRC error */
|
||||
#define RISB_RXABORT 0x0020 /* abort sequence received */
|
||||
#define RISB_EOFR 0x0040 /* complete frame received */
|
||||
|
||||
#define RISX_LEADCHG 0x0001 /* CTS lead change */
|
||||
#define RISX_PARERR 0x0004 /* parity error */
|
||||
#define RISX_SCMASK 0x0070 /* special character detect mask */
|
||||
#define RISX_SCHR1 0x0010 /* special character 1 detected */
|
||||
#define RISX_SCHR2 0x0020 /* special character 2 detected */
|
||||
#define RISX_SCHR3 0x0030 /* special character 3 detected */
|
||||
#define RISX_ALLZERO 0x0040 /* all 0 condition detected */
|
||||
#define RISX_ALLONE 0x0050 /* all 1 condition detected */
|
||||
#define RISX_ALTOZ 0x0060 /* alternating 1 0 condition detected */
|
||||
#define RISX_SYN 0x0070 /* SYN detected */
|
||||
#define RISX_LEAD 0x0080 /* leading value */
|
||||
|
||||
/*
|
||||
* Channel mode register (CMR) bits.
|
||||
*/
|
||||
#define CMR_RXDMA 0x80 /* DMA receive transfer mode */
|
||||
#define CMR_TXDMA 0x40 /* DMA transmit transfer mode */
|
||||
#define CMR_HDLC 0x00 /* HDLC protocol mode */
|
||||
#define CMR_BISYNC 0x01 /* BISYNC protocol mode */
|
||||
#define CMR_ASYNC 0x02 /* ASYNC protocol mode */
|
||||
#define CMR_X21 0x03 /* X.21 protocol mode */
|
||||
|
||||
/*
|
||||
* Modem interrupt status register (MISR) bits.
|
||||
*/
|
||||
#define MIS_CDSR 0x80 /* DSR changed */
|
||||
#define MIS_CCD 0x40 /* CD changed */
|
||||
#define MIS_CCTS 0x20 /* CTS changed */
|
||||
#define MIS_CGT2 0x02 /* GT2 timer expired */
|
||||
#define MIS_CGT1 0x01 /* GT1 timer expired */
|
||||
#define MIS_BITS "\20\1gt1\2gt2\6ccts\7ccd\10cdsr"
|
||||
|
||||
/*
|
||||
* Transmit interrupt status register (TISR) bits.
|
||||
*/
|
||||
#define TIS_BUSERR 0x80 /* Bus error */
|
||||
#define TIS_EOFR 0x40 /* End of frame */
|
||||
#define TIS_EOBUF 0x20 /* end of transmit buffer reached */
|
||||
#define TIS_UNDERRUN 0x10 /* transmit underrun */
|
||||
#define TIS_BB 0x08 /* buffer B status (not A) */
|
||||
#define TIS_TXEMPTY 0x02 /* transmitter empty */
|
||||
#define TIS_TXDATA 0x01 /* transmit data below threshold */
|
||||
#define TIS_BITS "\20\1txdata\2txempty\4bb\5underrun\6eobuf\7eofr\10buserr"
|
||||
|
||||
/*
|
||||
* Local interrupt vector register (LIVR) bits.
|
||||
*/
|
||||
#define LIV_EXCEP 0
|
||||
#define LIV_MODEM 1
|
||||
#define LIV_TXDATA 2
|
||||
#define LIV_RXDATA 3
|
||||
|
||||
/*
|
||||
* Transmit end of interrupt registers (TEOIR) bits.
|
||||
*/
|
||||
#define TEOI_TERMBUFF 0x80 /* force current buffer to be discarded */
|
||||
#define TEOI_EOFR 0x40 /* end of frame in interrupt mode */
|
||||
#define TEOI_SETTM2 0x20 /* set general timer 2 in sync mode */
|
||||
#define TEOI_SETTM1 0x10 /* set general timer 1 in sync mode */
|
||||
#define TEOI_NOTRANSF 0x08 /* no transfer of data on this interrupt */
|
||||
|
||||
/*
|
||||
* Receive end of interrupt registers (REOIR) bits.
|
||||
*/
|
||||
#define REOI_TERMBUFF 0x80 /* force current buffer to be terminated */
|
||||
#define REOI_DISCEXC 0x40 /* discard exception character */
|
||||
#define REOI_SETTM2 0x20 /* set general timer 2 */
|
||||
#define REOI_SETTM1 0x10 /* set general timer 1 */
|
||||
#define REOI_NOTRANSF 0x08 /* no transfer of data */
|
||||
#define REOI_GAP_MASK 0x07 /* optional gap size to leave in buffer */
|
||||
|
||||
/*
|
||||
* Special transmit command register (STCR) bits.
|
||||
*/
|
||||
#define STC_ABORTTX 0x40 /* abort transmission (HDLC mode) */
|
||||
#define STC_APPDCMP 0x20 /* append complete (async DMA mode) */
|
||||
#define STC_SNDSPC 0x08 /* send special characters (async mode) */
|
||||
#define STC_SSPC_MASK 0x07 /* special character select */
|
||||
#define STC_SSPC_1 0x01 /* send special character #1 */
|
||||
#define STC_SSPC_2 0x02 /* send special character #2 */
|
||||
#define STC_SSPC_3 0x03 /* send special character #3 */
|
||||
#define STC_SSPC_4 0x04 /* send special character #4 */
|
||||
|
||||
/*
|
||||
* Channel status register (CSR) bits, asynchronous mode.
|
||||
*/
|
||||
#define CSRA_RXEN 0x80 /* receiver enable */
|
||||
#define CSRA_RXFLOFF 0x40 /* receiver flow off */
|
||||
#define CSRA_RXFLON 0x20 /* receiver flow on */
|
||||
#define CSRA_TXEN 0x08 /* transmitter enable */
|
||||
#define CSRA_TXFLOFF 0x04 /* transmitter flow off */
|
||||
#define CSRA_TXFLON 0x02 /* transmitter flow on */
|
||||
#define CSRA_BITS "\20\2txflon\3txfloff\4txen\6rxflon\7rxfloff\10rxen"
|
||||
2546
sys/dev/cx/if_cx.c
2546
sys/dev/cx/if_cx.c
File diff suppressed because it is too large
Load Diff
@ -1,31 +0,0 @@
|
||||
/*-
|
||||
* Defines for Cronyx-Tau adapter driver.
|
||||
*
|
||||
* Copyright (C) 1999-2004 Cronyx Engineering.
|
||||
* Author: Kurakin Roman, <rik@cronyx.ru>
|
||||
*
|
||||
* This software is distributed with NO WARRANTIES, not even the implied
|
||||
* warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* Authors grant any other persons or organisations a permission to use,
|
||||
* modify and redistribute this software in source and binary forms,
|
||||
* as long as this message is kept with the software, all derivative
|
||||
* works or modified versions.
|
||||
*
|
||||
* Cronyx Id: ng_cx.h,v 1.1.2.3 2004/01/27 14:39:11 rik Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifdef NETGRAPH
|
||||
|
||||
#ifndef _CX_NETGRAPH_H_
|
||||
#define _CX_NETGRAPH_H_
|
||||
|
||||
#define NG_CX_NODE_TYPE "cx"
|
||||
#define NGM_CX_COOKIE 942763600
|
||||
#define NG_CX_HOOK_RAW "rawdata"
|
||||
#define NG_CX_HOOK_DEBUG "debug"
|
||||
|
||||
#endif /* _CX_NETGRAPH_H_ */
|
||||
|
||||
#endif /* NETGRAPH */
|
||||
@ -501,9 +501,6 @@ device cpufreq
|
||||
# V.35/RS-232/RS-530/RS-449/X.21/G.703/E1/E3/T3/STS-1
|
||||
# serial adaptor (requires sppp (default), or NETGRAPH if
|
||||
# NETGRAPH_CRONYX is configured)
|
||||
# ctau: Cronyx Tau sync dual port V.35/RS-232/RS-530/RS-449/X.21/G.703/E1
|
||||
# serial adaptor (requires sppp (default), or NETGRAPH if
|
||||
# NETGRAPH_CRONYX is configured)
|
||||
# ipw: Intel PRO/Wireless 2100 IEEE 802.11 adapter
|
||||
# iwi: Intel PRO/Wireless 2200BG/2225BG/2915ABG IEEE 802.11 adapters
|
||||
# Requires the iwi firmware module
|
||||
@ -526,11 +523,6 @@ device ce
|
||||
device cp
|
||||
hint.cs.0.at="isa"
|
||||
hint.cs.0.port="0x300"
|
||||
device ctau
|
||||
hint.ctau.0.at="isa"
|
||||
hint.ctau.0.port="0x240"
|
||||
hint.ctau.0.irq="15"
|
||||
hint.ctau.0.drq="7"
|
||||
#options NETGRAPH_CRONYX # Enable NETGRAPH support for Cronyx adapter(s)
|
||||
options ED_3C503
|
||||
options ED_HPP
|
||||
|
||||
@ -98,7 +98,6 @@ SUBDIR= \
|
||||
${_cpufreq} \
|
||||
${_crypto} \
|
||||
${_cryptodev} \
|
||||
${_ctau} \
|
||||
ctl \
|
||||
${_cxgb} \
|
||||
${_cxgbe} \
|
||||
@ -737,9 +736,6 @@ _glxsb= glxsb
|
||||
_pcfclock= pcfclock
|
||||
_pst= pst
|
||||
_sbni= sbni
|
||||
.if ${MK_SOURCELESS_UCODE} != "no"
|
||||
_ctau= ctau
|
||||
.endif
|
||||
.endif
|
||||
|
||||
.if ${MACHINE_CPUARCH} == "arm"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user