mlx5: Implement mlx5_core_modify_cq_by_mask().
Implement one CQ modify function supporting all firmware versions, instead of having more variants of CQ modify. MFC after: 1 week Sponsored by: NVIDIA Networking
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@ -86,6 +86,7 @@ enum {
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MLX5_CQ_MODIFY_PERIOD = 1 << 0,
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MLX5_CQ_MODIFY_COUNT = 1 << 1,
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MLX5_CQ_MODIFY_OVERRUN = 1 << 2,
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MLX5_CQ_MODIFY_EQN = 1 << 3,
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MLX5_CQ_MODIFY_PERIOD_MODE = 1 << 4,
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};
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@ -169,6 +170,10 @@ int mlx5_core_modify_cq_moderation_mode(struct mlx5_core_dev *dev,
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u16 cq_period,
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u16 cq_max_count,
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u8 cq_mode);
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int mlx5_core_modify_cq_by_mask(struct mlx5_core_dev *,
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struct mlx5_core_cq *, u32 mask,
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u16 cq_period, u16 cq_max_count,
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u8 cq_mode, u8 cq_eqn);
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int mlx5_debug_cq_add(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
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void mlx5_debug_cq_remove(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
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@ -219,18 +219,9 @@ int mlx5_core_modify_cq_moderation(struct mlx5_core_dev *dev,
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u16 cq_period,
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u16 cq_max_count)
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{
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u32 in[MLX5_ST_SZ_DW(modify_cq_in)] = {0};
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void *cqc;
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MLX5_SET(modify_cq_in, in, cqn, cq->cqn);
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cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context);
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MLX5_SET(cqc, cqc, cq_period, cq_period);
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MLX5_SET(cqc, cqc, cq_max_count, cq_max_count);
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MLX5_SET(modify_cq_in, in,
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modify_field_select_resize_field_select.modify_field_select.modify_field_select,
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MLX5_CQ_MODIFY_PERIOD | MLX5_CQ_MODIFY_COUNT);
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return mlx5_core_modify_cq(dev, cq, in, sizeof(in));
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return (mlx5_core_modify_cq_by_mask(dev, cq,
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MLX5_CQ_MODIFY_PERIOD | MLX5_CQ_MODIFY_COUNT,
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cq_period, cq_max_count, 0, 0));
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}
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int mlx5_core_modify_cq_moderation_mode(struct mlx5_core_dev *dev,
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@ -239,19 +230,34 @@ int mlx5_core_modify_cq_moderation_mode(struct mlx5_core_dev *dev,
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u16 cq_max_count,
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u8 cq_mode)
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{
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u32 in[MLX5_ST_SZ_DW(modify_cq_in)] = {0};
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return (mlx5_core_modify_cq_by_mask(dev, cq,
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MLX5_CQ_MODIFY_PERIOD | MLX5_CQ_MODIFY_COUNT | MLX5_CQ_MODIFY_PERIOD_MODE,
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cq_period, cq_max_count, cq_mode, 0));
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}
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int
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mlx5_core_modify_cq_by_mask(struct mlx5_core_dev *dev,
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struct mlx5_core_cq *cq, u32 mask,
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u16 cq_period, u16 cq_max_count, u8 cq_mode, u8 cq_eqn)
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{
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u32 in[MLX5_ST_SZ_DW(modify_cq_in)] = {};
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void *cqc;
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MLX5_SET(modify_cq_in, in, cqn, cq->cqn);
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cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context);
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MLX5_SET(cqc, cqc, cq_period, cq_period);
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MLX5_SET(cqc, cqc, cq_max_count, cq_max_count);
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MLX5_SET(cqc, cqc, cq_period_mode, cq_mode);
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MLX5_SET(modify_cq_in, in,
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modify_field_select_resize_field_select.modify_field_select.modify_field_select,
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MLX5_CQ_MODIFY_PERIOD | MLX5_CQ_MODIFY_COUNT | MLX5_CQ_MODIFY_PERIOD_MODE);
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if (mask & MLX5_CQ_MODIFY_PERIOD)
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MLX5_SET(cqc, cqc, cq_period, cq_period);
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if (mask & MLX5_CQ_MODIFY_COUNT)
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MLX5_SET(cqc, cqc, cq_max_count, cq_max_count);
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if (mask & MLX5_CQ_MODIFY_PERIOD_MODE)
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MLX5_SET(cqc, cqc, cq_period_mode, cq_mode);
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if (mask & MLX5_CQ_MODIFY_EQN)
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MLX5_SET(cqc, cqc, c_eqn, cq_eqn);
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return mlx5_core_modify_cq(dev, cq, in, sizeof(in));
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MLX5_SET(modify_cq_in, in,
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modify_field_select_resize_field_select.modify_field_select.modify_field_select, mask);
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return (mlx5_core_modify_cq(dev, cq, in, sizeof(in)));
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}
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int mlx5_init_cq_table(struct mlx5_core_dev *dev)
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