[atheros] teach these two boards about the new hints location as well.
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=328756
@ -106,22 +106,12 @@ hint.arge.1.pll_1000=0x03000101
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# MAC for arge1 is the second 6 bytes of the ART
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hint.arge.1.eeprommac=0x1fff0006
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# ath0: Where the ART is - last 64k in the flash
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hint.ath.0.eepromaddr=0x1fff0000
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hint.ath.0.eepromsize=16384
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# Where the ART is - last 64k in the first 8MB of flash
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hint.ar71xx_caldata.0.map.0.ath_fixup_addr=0x1fff0000
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hint.ar71xx_caldata.0.map.0.ath_fixup_size=16384
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# ath1: it's different; it's a PCIe attached device, so
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# we instead need to teach the PCIe bridge code about it
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# (ie, the 'early pci fixup' stuff that programs the PCIe
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# host registers on the NIC) and then we teach ath where
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# to find it.
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# ath1 hint - pcie slot 0
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# hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1fff4000
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# hint.pcib.0.bus.0.0.0.ath_fixup_size=16384
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# ath0 - eeprom comes from here
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# hint.ath.1.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware"
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# And now tell the ath(4) driver where to look!
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hint.ath.0.eeprom_firmware="ar71xx_caldata.0.map.0.eeprom_firmware"
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# flash layout:
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#
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@ -24,9 +24,12 @@ hint.arge.1.phymask=0x0 # No directly mapped PHYs
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hint.arge.1.media=1000
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hint.arge.1.fduplex=1
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# ath0: Where the ART is - last 64k in the flash
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hint.ath.0.eepromaddr=0x1fff0000
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hint.ath.0.eepromsize=16384
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# Where the ART is - last 64k in the first 8MB of flash
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hint.ar71xx_caldata.0.map.0.ath_fixup_addr=0x1fff0000
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hint.ar71xx_caldata.0.map.0.ath_fixup_size=16384
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# And now tell the ath(4) driver where to look!
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hint.ath.0.eeprom_firmware="ar71xx_caldata.0.map.0.eeprom_firmware"
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# The AP121 4MB flash layout:
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#
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