rk_armclk: Add the write mask to the register mux value

This was omitted in r334112 and r334996 which cause the PLL to not correctly
reparent, leaving the armclk to be derived from the APLL instead of the NPLL.
The arm core clock is now correctly set to 600Mhz via the assigned-clock present
in the DTB.

sys/arm64/rockchip/clk/rk_clk_armclk.c

@@ -105,7 +105,7 @@ rk_clk_armclk_set_mux(struct clknode *clk, int index)
 	DEVICE_LOCK(clk);
 	READ4(clk, sc->muxdiv_offset, &val);
 	val &= ~(sc->mux_mask >> sc->mux_shift);
-	val |= index << sc->mux_shift;
+	val |= index << sc->mux_shift | RK_ARMCLK_WRITE_MASK;
 	WRITE4(clk, sc->muxdiv_offset, val);
 	DEVICE_UNLOCK(clk);