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powerpc64: add missing TLB invalidations to radix

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Radix MMU code was missing TLB invalidations when some Level 3 PDEs were
modified. This caused TLB multi-hit machine check interrupts when
superpages were enabled.

Reviewed by:		jhibbits
MFC after:		2 weeks
Sponsored by:		Eldorado Research Institute (eldorado.org.br)
Differential Revision:	https://reviews.freebsd.org/D29511
This commit is contained in:
Leandro Lupori 2021-04-06 08:31:44 -03:00
parent 6c709cbf03
commit 28d14569c8
1 changed files with 4 additions and 1 deletions
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5
sys/powerpc/aim/mmu_radix.c
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@ -3184,6 +3184,7 @@ pmap_enter_l3e(pmap_t pmap, vm_offset_t va, pml3_entry_t newpde, u_int flags,
* a reserved PT page could be freed.
*/
(void)pmap_remove_l3e(pmap, l3e, va, &free, lockp);
pmap_invalidate_l3e_page(pmap, va, oldl3e);
} else {
if (pmap_remove_ptes(pmap, va, va + L3_PAGE_SIZE, l3e,
&free, lockp))
@ -3242,6 +3243,7 @@ pmap_enter_l3e(pmap_t pmap, vm_offset_t va, pml3_entry_t newpde, u_int flags,
* be any lingering 4KB page mappings in the TLB.)
*/
pte_store(l3e, newpde);
ptesync();
atomic_add_long(&pmap_l3e_mappings, 1);
CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
@ -4943,7 +4945,7 @@ pmap_demote_l3e_locked(pmap_t pmap, pml3_entry_t *l3e, vm_offset_t va,
* the read above and the store below.
*/
pde_store(l3e, mptepa);
ptesync();
pmap_invalidate_l3e_page(pmap, trunc_2mpage(va), oldpde);
/*
* Demote the PV entry.
*/
@ -5224,6 +5226,7 @@ mmu_radix_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
*/
if (sva + L3_PAGE_SIZE == va_next && eva >= va_next) {
pmap_remove_l3e(pmap, l3e, sva, &free, &lock);
anyvalid = true;
continue;
} else if (!pmap_demote_l3e_locked(pmap, l3e, sva,
&lock)) {