A rewrite of the i810 bits of the agp(4) driver. New driver supports
operations required by GEMified i915.ko. It also attaches to SandyBridge and IvyBridge CPU northbridges now. Sponsored by: The FreeBSD Foundation MFC after: 1 month
This commit is contained in:
Konstantin Belousov
parent
9280affe16
commit
28d86329af
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=235782
@ -239,7 +239,8 @@ agp_generic_attach(device_t dev)
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if (memsize <= agp_max[i][0])
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break;
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}
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if (i == agp_max_size) i = agp_max_size - 1;
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if (i == agp_max_size)
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i = agp_max_size - 1;
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sc->as_maxmem = agp_max[i][1] << 20U;
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/*
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@ -802,6 +803,13 @@ agp_unbind_user(device_t dev, agp_unbind *unbind)
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return AGP_UNBIND_MEMORY(dev, mem);
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}
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static int
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agp_chipset_flush(device_t dev)
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{
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return (AGP_CHIPSET_FLUSH(dev));
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}
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static int
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agp_open(struct cdev *kdev, int oflags, int devtype, struct thread *td)
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{
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@ -869,6 +877,8 @@ agp_ioctl(struct cdev *kdev, u_long cmd, caddr_t data, int fflag, struct thread
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case AGPIOC_UNBIND:
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return agp_unbind_user(dev, (agp_unbind *)data);
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case AGPIOC_CHIPSET_FLUSH:
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return agp_chipset_flush(dev);
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}
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return EINVAL;
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File diff suppressed because it is too large
Load Diff
101
sys/dev/agp/agp_i810.h
Normal file
101
sys/dev/agp/agp_i810.h
Normal file
@ -0,0 +1,101 @@
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/*-
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* Copyright (c) 2011 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Konstantin Belousov under sponsorship from
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* the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef AGP_AGP_I810_H
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#define AGP_AGP_I810_H
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#include <sys/param.h>
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#include <sys/sglist.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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/* Special gtt memory types */
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#define AGP_DCACHE_MEMORY 1
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#define AGP_PHYS_MEMORY 2
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/* New caching attributes for gen6/sandybridge */
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#define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2)
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#define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4)
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/* flag for GFDT type */
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#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
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struct intel_gtt {
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/* Size of memory reserved for graphics by the BIOS */
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u_int stolen_size;
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/* Total number of gtt entries. */
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u_int gtt_total_entries;
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/*
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* Part of the gtt that is mappable by the cpu, for those
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* chips where this is not the full gtt.
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*/
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u_int gtt_mappable_entries;
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/*
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* Always false.
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*/
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u_int do_idle_maps;
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/*
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* Share the scratch page dma with ppgtts.
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*/
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vm_paddr_t scratch_page_dma;
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};
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struct intel_gtt agp_intel_gtt_get(device_t dev);
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int agp_intel_gtt_chipset_flush(device_t dev);
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void agp_intel_gtt_unmap_memory(device_t dev, struct sglist *sg_list);
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void agp_intel_gtt_clear_range(device_t dev, u_int first_entry,
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u_int num_entries);
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int agp_intel_gtt_map_memory(device_t dev, vm_page_t *pages, u_int num_entries,
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struct sglist **sg_list);
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void agp_intel_gtt_insert_sg_entries(device_t dev, struct sglist *sg_list,
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u_int pg_start, u_int flags);
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void agp_intel_gtt_insert_pages(device_t dev, u_int first_entry,
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u_int num_entries, vm_page_t *pages, u_int flags);
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struct intel_gtt intel_gtt_get(void);
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int intel_gtt_chipset_flush(void);
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void intel_gtt_unmap_memory(struct sglist *sg_list);
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void intel_gtt_clear_range(u_int first_entry, u_int num_entries);
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int intel_gtt_map_memory(vm_page_t *pages, u_int num_entries,
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struct sglist **sg_list);
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void intel_gtt_insert_sg_entries(struct sglist *sg_list, u_int pg_start,
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u_int flags);
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void intel_gtt_insert_pages(u_int first_entry, u_int num_entries,
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vm_page_t *pages, u_int flags);
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vm_paddr_t intel_gtt_read_pte_paddr(u_int entry);
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u_int32_t intel_gtt_read_pte(u_int entry);
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device_t intel_gtt_get_bridge_device(void);
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void intel_gtt_write(u_int entry, uint32_t val);
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#endif
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@ -36,6 +36,14 @@
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#
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INTERFACE agp;
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CODE {
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static int
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null_agp_chipset_flush(device_t dev)
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{
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return (ENXIO);
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}
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};
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#
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# Return the current aperture size.
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#
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@ -132,3 +140,7 @@ METHOD int unbind_memory {
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device_t dev;
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struct agp_memory *handle;
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};
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METHOD int chipset_flush {
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device_t dev;
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} DEFAULT null_agp_chipset_flush;
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@ -73,7 +73,7 @@ struct agp_softc {
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struct agp_memory_list as_memory; /* list of allocated memory */
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int as_nextid; /* next memory block id */
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int as_isopen; /* user device is open */
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struct cdev *as_devnode; /* from make_dev */
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struct cdev *as_devnode; /* from make_dev */
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struct mtx as_lock; /* lock for access to GATT */
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};
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@ -176,10 +176,33 @@
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#define AGP_I810_GMADR 0x10
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#define AGP_I810_MMADR 0x14
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#define I810_PTE_VALID 0x00000001
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/*
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* Cache control
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*
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* Pre-Sandybridge bits
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*/
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#define I810_PTE_MAIN_UNCACHED 0x00000000
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#define I810_PTE_LOCAL 0x00000002 /* Non-snooped main phys memory */
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#define I830_PTE_SYSTEM_CACHED 0x00000006 /* Snooped main phys memory */
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/*
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* Sandybridge
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* LLC - Last Level Cache
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* MMC - Mid Level Cache
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*/
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#define GEN6_PTE_RESERVED 0x00000000
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#define GEN6_PTE_UNCACHED 0x00000002 /* Do not cache */
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#define GEN6_PTE_LLC 0x00000004 /* Cache in LLC */
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#define GEN6_PTE_LLC_MLC 0x00000006 /* Cache in LLC and MLC */
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#define GEN6_PTE_GFDT 0x00000008 /* Graphics Data Type */
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/*
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* Memory mapped register offsets for i810 chipset.
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*/
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#define AGP_I810_PGTBL_CTL 0x2020
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#define AGP_I810_PGTBL_ENABLED 0x00000001
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/**
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* This field determines the actual size of the global GTT on the 965
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* and G33
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@ -187,7 +210,23 @@
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#define AGP_I810_PGTBL_SIZE_MASK 0x0000000e
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#define AGP_I810_PGTBL_SIZE_512KB (0 << 1)
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#define AGP_I810_PGTBL_SIZE_256KB (1 << 1)
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#define AGP_I810_PGTBL_SIZE_128KB (2 << 1)
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#define AGP_I810_PGTBL_SIZE_128KB (2 << 1)
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#define AGP_I810_PGTBL_SIZE_1MB (3 << 1)
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#define AGP_I810_PGTBL_SIZE_2MB (4 << 1)
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#define AGP_I810_PGTBL_SIZE_1_5MB (5 << 1)
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#define AGP_G33_GCC1_SIZE_MASK (3 << 8)
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#define AGP_G33_GCC1_SIZE_1M (1 << 8)
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#define AGP_G33_GCC1_SIZE_2M (2 << 8)
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#define AGP_G4x_GCC1_SIZE_MASK (0xf << 8)
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#define AGP_G4x_GCC1_SIZE_1M (0x1 << 8)
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#define AGP_G4x_GCC1_SIZE_2M (0x3 << 8)
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#define AGP_G4x_GCC1_SIZE_VT_EN (0x8 << 8)
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#define AGP_G4x_GCC1_SIZE_VT_1M \
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(AGP_G4x_GCC1_SIZE_1M | AGP_G4x_GCC1_SIZE_VT_EN)
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#define AGP_G4x_GCC1_SIZE_VT_1_5M ((0x2 << 8) | AGP_G4x_GCC1_SIZE_VT_EN)
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#define AGP_G4x_GCC1_SIZE_VT_2M \
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(AGP_G4x_GCC1_SIZE_2M | AGP_G4x_GCC1_SIZE_VT_EN)
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#define AGP_I810_DRT 0x3000
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#define AGP_I810_DRT_UNPOPULATED 0x00
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#define AGP_I810_DRT_POPULATED 0x01
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@ -207,6 +246,7 @@
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#define AGP_I830_GCC1_GMASIZE 0x01
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#define AGP_I830_GCC1_GMASIZE_64 0x01
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#define AGP_I830_GCC1_GMASIZE_128 0x00
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#define AGP_I830_HIC 0x70
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/*
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* Config registers for 852GM/855GM/865G device 0
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@ -243,6 +283,9 @@
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#define AGP_I915_GCC1_GMS_STOLEN_48M 0x60
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#define AGP_I915_GCC1_GMS_STOLEN_64M 0x70
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#define AGP_I915_DEVEN 0x54
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#define AGP_SB_DEVEN_D2EN 0x10 /* SB+ has IGD enabled bit */
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#define AGP_SB_DEVEN_D2EN_ENABLED 0x10 /* in different place */
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#define AGP_SB_DEVEN_D2EN_DISABLED 0x00
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#define AGP_I915_DEVEN_D2F0 0x08
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#define AGP_I915_DEVEN_D2F0_ENABLED 0x08
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#define AGP_I915_DEVEN_D2F0_DISABLED 0x00
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@ -250,6 +293,7 @@
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#define AGP_I915_MSAC_GMASIZE 0x02
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#define AGP_I915_MSAC_GMASIZE_128 0x02
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#define AGP_I915_MSAC_GMASIZE_256 0x00
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#define AGP_I915_IFPADDR 0x60
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/*
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* G965 registers
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@ -262,6 +306,8 @@
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#define AGP_I965_PGTBL_SIZE_1MB (3 << 1)
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#define AGP_I965_PGTBL_SIZE_2MB (4 << 1)
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#define AGP_I965_PGTBL_SIZE_1_5MB (5 << 1)
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#define AGP_I965_PGTBL_CTL2 0x20c4
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#define AGP_I965_IFPADDR 0x70
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/*
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* G33 registers
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@ -275,11 +321,42 @@
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/*
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* G4X registers
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*/
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#define AGP_G4X_GMADR 0x20
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#define AGP_G4X_MMADR 0x10
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#define AGP_G4X_GTTADR 0x18
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#define AGP_G4X_GCC1_GMS_STOLEN_96M 0xa0
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#define AGP_G4X_GCC1_GMS_STOLEN_160M 0xb0
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#define AGP_G4X_GCC1_GMS_STOLEN_224M 0xc0
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#define AGP_G4X_GCC1_GMS_STOLEN_352M 0xd0
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/*
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* SandyBridge/IvyBridge registers
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*/
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#define AGP_SNB_GCC1 0x50
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#define AGP_SNB_GMCH_GMS_STOLEN_MASK 0xF8
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#define AGP_SNB_GMCH_GMS_STOLEN_32M (1 << 3)
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#define AGP_SNB_GMCH_GMS_STOLEN_64M (2 << 3)
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#define AGP_SNB_GMCH_GMS_STOLEN_96M (3 << 3)
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#define AGP_SNB_GMCH_GMS_STOLEN_128M (4 << 3)
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#define AGP_SNB_GMCH_GMS_STOLEN_160M (5 << 3)
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#define AGP_SNB_GMCH_GMS_STOLEN_192M (6 << 3)
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#define AGP_SNB_GMCH_GMS_STOLEN_224M (7 << 3)
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#define AGP_SNB_GMCH_GMS_STOLEN_256M (8 << 3)
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#define AGP_SNB_GMCH_GMS_STOLEN_288M (9 << 3)
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#define AGP_SNB_GMCH_GMS_STOLEN_320M (0xa << 3)
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#define AGP_SNB_GMCH_GMS_STOLEN_352M (0xb << 3)
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#define AGP_SNB_GMCH_GMS_STOLEN_384M (0xc << 3)
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#define AGP_SNB_GMCH_GMS_STOLEN_416M (0xd << 3)
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#define AGP_SNB_GMCH_GMS_STOLEN_448M (0xe << 3)
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#define AGP_SNB_GMCH_GMS_STOLEN_480M (0xf << 3)
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#define AGP_SNB_GMCH_GMS_STOLEN_512M (0x10 << 3)
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#define AGP_SNB_GTT_SIZE_0M (0 << 8)
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#define AGP_SNB_GTT_SIZE_1M (1 << 8)
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#define AGP_SNB_GTT_SIZE_2M (2 << 8)
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#define AGP_SNB_GTT_SIZE_MASK (3 << 8)
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#define AGP_SNB_GFX_MODE 0x02520
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/*
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* NVIDIA nForce/nForce2 registers
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*/
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@ -122,4 +122,10 @@ int agp_unbind_memory(device_t dev, void *handle);
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*/
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void agp_memory_info(device_t dev, void *handle, struct agp_memory_info *mi);
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#define AGP_NORMAL_MEMORY 0
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#define AGP_USER_TYPES (1 << 16)
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#define AGP_USER_MEMORY (AGP_USER_TYPES)
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#define AGP_USER_CACHED_MEMORY (AGP_USER_TYPES + 1)
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#endif /* !_PCI_AGPVAR_H_ */
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@ -33,4 +33,16 @@ EXPORT_SYMS= agp_find_device \
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agp_unbind_memory \
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agp_memory_info
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.if ${MACHINE_CPUARCH} == "i386" || ${MACHINE_CPUARCH} == "amd64"
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EXPORT_SYMS+= intel_gtt_clear_range \
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intel_gtt_insert_pages \
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intel_gtt_get \
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intel_gtt_chipset_flush \
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intel_gtt_unmap_memory \
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intel_gtt_map_memory \
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intel_gtt_insert_sg_entries \
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intel_gtt_get_bridge_device
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.endif
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.include <bsd.kmod.mk>
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@ -88,6 +88,7 @@
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#define AGPIOC_DEALLOCATE _IOW (AGPIOC_BASE, 7, int)
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#define AGPIOC_BIND _IOW (AGPIOC_BASE, 8, agp_bind)
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#define AGPIOC_UNBIND _IOW (AGPIOC_BASE, 9, agp_unbind)
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#define AGPIOC_CHIPSET_FLUSH _IO (AGPIOC_BASE, 10)
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typedef struct _agp_version {
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u_int16_t major;
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