dts: Update our copy from files from Linux 4.16
This commit is contained in:
parent
16ae49e2be
commit
29087c4e73
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/vendor/device-tree/dist/; revision=332836 svn path=/vendor/device-tree/4.16/; revision=332837; tag=vendor/device-tree/4.16
@ -21,10 +21,26 @@ Boards:
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Root node property compatible must contain, depending on board:
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- Allo.com Sparky: "allo,sparky"
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- Cubietech CubieBoard6: "cubietech,cubieboard6"
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- LeMaker Guitar Base Board rev. B: "lemaker,guitar-bb-rev-b", "lemaker,guitar"
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S700 SoC
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========
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Required root node properties:
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- compatible : must contain "actions,s700"
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Boards:
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Root node property compatible must contain, depending on board:
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- Cubietech CubieBoard7: "cubietech,cubieboard7"
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S900 SoC
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========
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27
Bindings/arm/arm-dsu-pmu.txt
Normal file
27
Bindings/arm/arm-dsu-pmu.txt
Normal file
@ -0,0 +1,27 @@
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* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
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ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
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with a shared L3 memory system, control logic and external interfaces to
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form a multicore cluster. The PMU enables to gather various statistics on
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the operations of the DSU. The PMU provides independent 32bit counters that
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can count any of the supported events, along with a 64bit cycle counter.
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The PMU is accessed via CPU system registers and has no MMIO component.
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** DSU PMU required properties:
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- compatible : should be one of :
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"arm,dsu-pmu"
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- interrupts : Exactly 1 SPI must be listed.
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- cpus : List of phandles for the CPUs connected to this DSU instance.
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** Example:
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dsu-pmu-0 {
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compatible = "arm,dsu-pmu";
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interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
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cpus = <&cpu_0>, <&cpu_1>;
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};
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@ -90,38 +90,6 @@ System Timer (ST) required properties:
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Its subnodes can be:
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- watchdog: compatible should be "atmel,at91rm9200-wdt"
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TC/TCLIB Timer required properties:
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- compatible: Should be "atmel,<chip>-tcb".
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<chip> can be "at91rm9200" or "at91sam9x5"
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- reg: Should contain registers location and length
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- interrupts: Should contain all interrupts for the TC block
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Note that you can specify several interrupt cells if the TC
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block has one interrupt per channel.
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- clock-names: tuple listing input clock names.
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Required elements: "t0_clk", "slow_clk"
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Optional elements: "t1_clk", "t2_clk"
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- clocks: phandles to input clocks.
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Examples:
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One interrupt per TC block:
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tcb0: timer@fff7c000 {
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compatible = "atmel,at91rm9200-tcb";
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reg = <0xfff7c000 0x100>;
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interrupts = <18 4>;
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clocks = <&tcb0_clk>;
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clock-names = "t0_clk";
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};
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One interrupt per TC channel in a TC block:
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tcb1: timer@fffdc000 {
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compatible = "atmel,at91rm9200-tcb";
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reg = <0xfffdc000 0x100>;
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interrupts = <26 4 27 4 28 4>;
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clocks = <&tcb1_clk>;
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clock-names = "t0_clk";
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};
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RSTC Reset Controller required properties:
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- compatible: Should be "atmel,<chip>-rstc".
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<chip> can be "at91sam9260" or "at91sam9g45" or "sama5d3"
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@ -10,6 +10,15 @@ compatible = "axentia,linea",
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and following the rules from atmel-at91.txt for a sama5d31 SoC.
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Nattis v2 board with Natte v2 power board
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-----------------------------------------
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Required root node properties:
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compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea",
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"atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
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and following the rules from above for the axentia,linea CPU module.
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TSE-850 v3 board
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----------------
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@ -17,21 +17,23 @@ Further, syscon nodes that map platform-specific registers used for general
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system control is required:
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- compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
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- compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"
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- compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
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"brcm,brcmstb-cpu-biu-ctrl",
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"syscon"
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- compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
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hif-cpubiuctrl node
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cpu-biu-ctrl node
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-------------------
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SoCs with Broadcom Brahma15 ARM-based CPUs have a specific Bus Interface Unit
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(BIU) block which controls and interfaces the CPU complex to the different
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Memory Controller Ports (MCP), one per memory controller (MEMC). This BIU block
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offers a feature called Write Pairing which consists in collapsing two adjacent
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cache lines into a single (bursted) write transaction towards the memory
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controller (MEMC) to maximize write bandwidth.
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SoCs with Broadcom Brahma15 ARM-based and Brahma53 ARM64-based CPUs have a
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specific Bus Interface Unit (BIU) block which controls and interfaces the CPU
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complex to the different Memory Controller Ports (MCP), one per memory
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controller (MEMC). This BIU block offers a feature called Write Pairing which
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consists in collapsing two adjacent cache lines into a single (bursted) write
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transaction towards the memory controller (MEMC) to maximize write bandwidth.
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Required properties:
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- compatible: must be "brcm,bcm7445-hif-cpubiuctrl", "syscon"
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- compatible: must be "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon"
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Optional properties:
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@ -52,7 +54,7 @@ example:
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};
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hif_cpubiuctrl: syscon@3e2400 {
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compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";
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compatible = "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon";
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reg = <0x3e2400 0x5b4>;
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brcm,write-pairing;
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};
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@ -169,6 +169,7 @@ described below.
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"arm,cortex-r5"
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"arm,cortex-r7"
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"brcm,brahma-b15"
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"brcm,brahma-b53"
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"brcm,vulcan"
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"cavium,thunder"
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"cavium,thunder2"
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42
Bindings/arm/firmware/sdei.txt
Normal file
42
Bindings/arm/firmware/sdei.txt
Normal file
@ -0,0 +1,42 @@
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* Software Delegated Exception Interface (SDEI)
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Firmware implementing the SDEI functions described in ARM document number
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ARM DEN 0054A ("Software Delegated Exception Interface") can be used by
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Linux to receive notification of events such as those generated by
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firmware-first error handling, or from an IRQ that has been promoted to
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a firmware-assisted NMI.
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The interface provides a number of API functions for registering callbacks
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and enabling/disabling events. Functions are invoked by trapping to the
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privilege level of the SDEI firmware (specified as part of the binding
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below) and passing arguments in a manner specified by the "SMC Calling
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Convention (ARM DEN 0028B):
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r0 => 32-bit Function ID / return value
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{r1 - r3} => Parameters
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Note that the immediate field of the trapping instruction must be set
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to #0.
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The SDEI_EVENT_REGISTER function registers a callback in the kernel
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text to handle the specified event number.
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The sdei node should be a child node of '/firmware' and have required
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properties:
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- compatible : should contain:
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* "arm,sdei-1.0" : For implementations complying to SDEI version 1.x.
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- method : The method of calling the SDEI firmware. Permitted
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values are:
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* "smc" : SMC #0, with the register assignments specified in this
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binding.
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* "hvc" : HVC #0, with the register assignments specified in this
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binding.
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Example:
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firmware {
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sdei {
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compatible = "arm,sdei-1.0";
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method = "smc";
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};
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};
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@ -14,3 +14,22 @@ following property before the previous one:
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Example:
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compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710";
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Power management
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----------------
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For power management (particularly DVFS and AVS), the North Bridge
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Power Management component is needed:
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Required properties:
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- compatible : should contain "marvell,armada-3700-nb-pm", "syscon";
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- reg : the register start and length for the North Bridge
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Power Management
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Example:
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nb_pm: syscon@14000 {
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compatible = "marvell,armada-3700-nb-pm", "syscon";
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reg = <0x14000 0x60>;
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}
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@ -20,4 +20,5 @@ ethsys: clock-controller@1b000000 {
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compatible = "mediatek,mt2701-ethsys", "syscon";
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reg = <0 0x1b000000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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@ -55,7 +55,7 @@ Note: child nodes can be added for auto probing from device tree.
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Example: adding device info in dtsi file
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adc: adc@12D10000 {
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adc: adc@12d10000 {
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compatible = "samsung,exynos-adc-v1";
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reg = <0x12D10000 0x100>;
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interrupts = <0 106 0>;
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@ -71,7 +71,7 @@ adc: adc@12D10000 {
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Example: adding device info in dtsi file for Exynos3250 with additional sclk
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adc: adc@126C0000 {
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adc: adc@126c0000 {
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compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2;
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reg = <0x126C0000 0x100>;
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interrupts = <0 137 0>;
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@ -87,7 +87,7 @@ adc: adc@126C0000 {
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Example: Adding child nodes in dts file
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adc@12D10000 {
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adc@12d10000 {
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/* NTC thermistor is a hwmon device */
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ncp15wb473@0 {
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@ -72,7 +72,7 @@ Optional nodes:
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- compatible: only "samsung,secure-firmware" is currently supported
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- reg: address of non-secure SYSRAM used for communication with firmware
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firmware@203F000 {
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firmware@203f000 {
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compatible = "samsung,secure-firmware";
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reg = <0x0203F000 0x1000>;
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};
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@ -104,12 +104,16 @@ Boards:
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compatible = "renesas,salvator-x", "renesas,r8a7796"
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- Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
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compatible = "renesas,salvator-xs", "renesas,r8a7795"
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- Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S)
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compatible = "renesas,salvator-xs", "renesas,r8a7796"
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- SILK (RTP0RC7794LCB00011S)
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compatible = "renesas,silk", "renesas,r8a7794"
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- SK-RZG1E (YR8A77450S000BE)
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compatible = "renesas,sk-rzg1e", "renesas,r8a7745"
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- SK-RZG1M (YR8A77430S000BE)
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compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
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- V3MSK
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compatible = "renesas,v3msk", "renesas,r8a77970"
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- Wheat
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compatible = "renesas,wheat", "renesas,r8a7792"
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9
Bindings/arm/stm32.txt
Normal file
9
Bindings/arm/stm32.txt
Normal file
@ -0,0 +1,9 @@
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STMicroelectronics STM32 Platforms Device Tree Bindings
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Each device tree must specify which STM32 SoC it uses,
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using one of the following compatible strings:
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st,stm32f429
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st,stm32f469
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st,stm32f746
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st,stm32h743
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@ -1,6 +1,11 @@
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Technologic Systems Platforms Device Tree Bindings
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--------------------------------------------------
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TS-4600 is a System-on-Module based on the Freescale i.MX28 System-on-Chip.
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It can be mounted on a carrier board providing additional peripheral connectors.
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Required root node properties:
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- compatible = "technologic,imx28-ts4600", "fsl,imx28"
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TS-4800 board
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Required root node properties:
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- compatible = "technologic,imx51-ts4800", "fsl,imx51";
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@ -10,3 +15,9 @@ It can be mounted on a carrier board providing additional peripheral connectors.
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Required root node properties:
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- compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl"
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- compatible = "technologic,imx6q-ts4900", "fsl,imx6q"
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TS-7970 is a System-on-Module based on the Freescale i.MX6 System-on-Chip.
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It can be mounted on a carrier board providing additional peripheral connectors.
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Required root node properties:
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- compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl"
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- compatible = "technologic,imx6q-ts7970", "fsl,imx6q"
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@ -19,6 +19,7 @@ Required standard properties:
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- compatible shall be one of the following generic types:
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"ti,sysc"
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"ti,sysc-omap2"
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"ti,sysc-omap4"
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"ti,sysc-omap4-simple"
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@ -26,6 +27,8 @@ Required standard properties:
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or one of the following derivative types for hardware
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needing special workarounds:
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"ti,sysc-omap2-timer"
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"ti,sysc-omap4-timer"
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"ti,sysc-omap3430-sr"
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"ti,sysc-omap3630-sr"
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"ti,sysc-omap4-sr"
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@ -49,6 +52,26 @@ Required standard properties:
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Optional properties:
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- ti,sysc-mask shall contain mask of supported register bits for the
|
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SYSCONFIG register as documented in the Technical Reference
|
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Manual (TRM) for the interconnect target module
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- ti,sysc-midle list of master idle modes supported by the interconnect
|
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target module as documented in the TRM for SYSCONFIG
|
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register MIDLEMODE bits
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- ti,sysc-sidle list of slave idle modes supported by the interconnect
|
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target module as documented in the TRM for SYSCONFIG
|
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register SIDLEMODE bits
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- ti,sysc-delay-us delay needed after OCP softreset before accssing
|
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SYSCONFIG register again
|
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|
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- ti,syss-mask optional mask of reset done status bits as described in the
|
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TRM for SYSSTATUS registers, typically 1 with some devices
|
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having separate reset done bits for children like OHCI and
|
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EHCI
|
||||
|
||||
- clocks clock specifier for each name in the clock-names as
|
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specified in the binding documentation for ti-clkctrl,
|
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typically available for all interconnect targets on TI SoCs
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@ -61,6 +84,9 @@ Optional properties:
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- ti,hwmods optional TI interconnect module name to use legacy
|
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hwmod platform data
|
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- ti,no-reset-on-init interconnect target module should not be reset at init
|
||||
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||||
- ti,no-idle-on-init interconnect target module should not be idled at init
|
||||
|
||||
Example: Single instance of MUSB controller on omap4 using interconnect ranges
|
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using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
|
||||
@ -74,6 +100,17 @@ using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
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reg-names = "rev", "sysc", "syss";
|
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clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
|
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clock-names = "fck";
|
||||
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
||||
SYSC_OMAP2_SOFTRESET |
|
||||
SYSC_OMAP2_AUTOIDLE)>;
|
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
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<SYSC_IDLE_NO>,
|
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<SYSC_IDLE_SMART>;
|
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
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<SYSC_IDLE_NO>,
|
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<SYSC_IDLE_SMART>,
|
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<SYSC_IDLE_SMART_WKUP>;
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ti,syss-mask = <1>;
|
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x2b000 0x1000>;
|
||||
|
@ -120,3 +120,18 @@ e.g.
|
||||
While this property does not represent a real hardware, the address
|
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and the size are expressed in #address-cells and #size-cells,
|
||||
respectively, of the root node.
|
||||
|
||||
linux,initrd-start and linux,initrd-end
|
||||
---------------------------------------
|
||||
|
||||
These properties hold the physical start and end address of an initrd that's
|
||||
loaded by the bootloader. Note that linux,initrd-start is inclusive, but
|
||||
linux,initrd-end is exclusive.
|
||||
e.g.
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
linux,initrd-start = <0x82000000>;
|
||||
linux,initrd-end = <0x82800000>;
|
||||
};
|
||||
};
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|
@ -5,8 +5,11 @@ controllers within the SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "amlogic,gxbb-clkc" for GXBB SoC,
|
||||
or "amlogic,gxl-clkc" for GXL and GXM SoC.
|
||||
- compatible: should be:
|
||||
"amlogic,gxbb-clkc" for GXBB SoC,
|
||||
"amlogic,gxl-clkc" for GXL and GXM SoC,
|
||||
"amlogic,axg-clkc" for AXG SoC.
|
||||
|
||||
- reg: physical base address of the clock controller and length of memory
|
||||
mapped region.
|
||||
|
||||
|
@ -32,7 +32,7 @@ Example 1: Examples of clock controller nodes are listed below.
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
cmu_dmc: clock-controller@105C0000 {
|
||||
cmu_dmc: clock-controller@105c0000 {
|
||||
compatible = "samsung,exynos3250-cmu-dmc";
|
||||
reg = <0x105C0000 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
|
@ -180,7 +180,7 @@ Example 2: UART controller node that consumes the clock generated by the
|
||||
peri clock controller. Refer to the standard clock bindings for
|
||||
information about 'clocks' and 'clock-names' property.
|
||||
|
||||
serial@12C00000 {
|
||||
serial@12c00000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C00000 0x100>;
|
||||
interrupts = <0 146 0>;
|
||||
|
@ -41,7 +41,7 @@ Example 2: UART controller node that consumes the clock generated by the clock
|
||||
controller. Refer to the standard clock bindings for information
|
||||
about 'clocks' and 'clock-names' property.
|
||||
|
||||
serial@12C20000 {
|
||||
serial@12c20000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C00000 0x100>;
|
||||
interrupts = <0 51 0>;
|
||||
|
@ -472,7 +472,7 @@ Example 2: Examples of clock controller nodes are listed below.
|
||||
Example 3: UART controller node that consumes the clock generated by the clock
|
||||
controller.
|
||||
|
||||
serial_0: serial@14C10000 {
|
||||
serial_0: serial@14c10000 {
|
||||
compatible = "samsung,exynos5433-uart";
|
||||
reg = <0x14C10000 0x100>;
|
||||
interrupts = <0 421 0>;
|
||||
|
@ -13,12 +13,18 @@ Required Properties:
|
||||
- "hisilicon,hi3660-pmuctrl"
|
||||
- "hisilicon,hi3660-sctrl"
|
||||
- "hisilicon,hi3660-iomcu"
|
||||
- "hisilicon,hi3660-stub-clk"
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- mboxes: Phandle to the mailbox for sending message to MCU.
|
||||
(See: ../mailbox/hisilicon,hi3660-mailbox.txt for more info)
|
||||
|
||||
Each clock is assigned an identifier and client nodes use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
|
22
Bindings/clock/qcom,a53pll.txt
Normal file
22
Bindings/clock/qcom,a53pll.txt
Normal file
@ -0,0 +1,22 @@
|
||||
Qualcomm MSM8916 A53 PLL Binding
|
||||
--------------------------------
|
||||
The A53 PLL on MSM8916 platforms is the main CPU PLL used used for frequencies
|
||||
above 1GHz.
|
||||
|
||||
Required properties :
|
||||
- compatible : Shall contain only one of the following:
|
||||
|
||||
"qcom,msm8916-a53pll"
|
||||
|
||||
- reg : shall contain base register location and length
|
||||
|
||||
- #clock-cells : must be set to <0>
|
||||
|
||||
Example:
|
||||
|
||||
a53pll: clock@b016000 {
|
||||
compatible = "qcom,msm8916-a53pll";
|
||||
reg = <0xb016000 0x40>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
59
Bindings/clock/qcom,spmi-clkdiv.txt
Normal file
59
Bindings/clock/qcom,spmi-clkdiv.txt
Normal file
@ -0,0 +1,59 @@
|
||||
Qualcomm Technologies, Inc. SPMI PMIC clock divider (clkdiv)
|
||||
|
||||
clkdiv configures the clock frequency of a set of outputs on the PMIC.
|
||||
These clocks are typically wired through alternate functions on
|
||||
gpio pins.
|
||||
|
||||
=======================
|
||||
Properties
|
||||
=======================
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be "qcom,spmi-clkdiv".
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: base address of CLKDIV peripherals.
|
||||
|
||||
- qcom,num-clkdivs
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: number of CLKDIV peripherals.
|
||||
|
||||
- clocks:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: reference to the xo clock.
|
||||
|
||||
- clock-names:
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: must be "xo".
|
||||
|
||||
- #clock-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: shall contain 1.
|
||||
|
||||
=======
|
||||
Example
|
||||
=======
|
||||
|
||||
pm8998_clk_divs: clock-controller@5b00 {
|
||||
compatible = "qcom,spmi-clkdiv";
|
||||
reg = <0x5b00>;
|
||||
#clock-cells = <1>;
|
||||
qcom,num-clkdivs = <3>;
|
||||
clocks = <&xo_board>;
|
||||
clock-names = "xo";
|
||||
|
||||
assigned-clocks = <&pm8998_clk_divs 1>,
|
||||
<&pm8998_clk_divs 2>,
|
||||
<&pm8998_clk_divs 3>;
|
||||
assigned-clock-rates = <9600000>,
|
||||
<9600000>,
|
||||
<9600000>;
|
||||
};
|
@ -78,6 +78,7 @@ second cell is the clock index for the specified type.
|
||||
2 hwaccel index (n in CLKCGnHWACSR)
|
||||
3 fman 0 for fm1, 1 for fm2
|
||||
4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
|
||||
4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8
|
||||
5 coreclk must be 0
|
||||
|
||||
3. Example
|
||||
|
@ -49,6 +49,7 @@ Optional child node properties:
|
||||
- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
|
||||
divider.
|
||||
- silabs,pll-master: boolean, multisynth can change pll frequency.
|
||||
- silabs,pll-reset: boolean, clock output can reset its pll.
|
||||
- silabs,disable-state : clock output disable state, shall be
|
||||
0 = clock output is driven LOW when disabled
|
||||
1 = clock output is driven HIGH when disabled
|
||||
|
63
Bindings/clock/sprd.txt
Normal file
63
Bindings/clock/sprd.txt
Normal file
@ -0,0 +1,63 @@
|
||||
Spreadtrum Clock Binding
|
||||
------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: should contain the following compatible strings:
|
||||
- "sprd,sc9860-pmu-gate"
|
||||
- "sprd,sc9860-pll"
|
||||
- "sprd,sc9860-ap-clk"
|
||||
- "sprd,sc9860-aon-prediv"
|
||||
- "sprd,sc9860-apahb-gate"
|
||||
- "sprd,sc9860-aon-gate"
|
||||
- "sprd,sc9860-aonsecure-clk"
|
||||
- "sprd,sc9860-agcp-gate"
|
||||
- "sprd,sc9860-gpu-clk"
|
||||
- "sprd,sc9860-vsp-clk"
|
||||
- "sprd,sc9860-vsp-gate"
|
||||
- "sprd,sc9860-cam-clk"
|
||||
- "sprd,sc9860-cam-gate"
|
||||
- "sprd,sc9860-disp-clk"
|
||||
- "sprd,sc9860-disp-gate"
|
||||
- "sprd,sc9860-apapb-gate"
|
||||
|
||||
- #clock-cells: must be 1
|
||||
|
||||
- clocks : Should be the input parent clock(s) phandle for the clock, this
|
||||
property here just simply shows which clock group the clocks'
|
||||
parents are in, since each clk node would represent many clocks
|
||||
which are defined in the driver. The detailed dependency
|
||||
relationship (i.e. how many parents and which are the parents)
|
||||
are implemented in driver code.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- reg: Contain the registers base address and length. It must be configured
|
||||
only if no 'sprd,syscon' under the node.
|
||||
|
||||
- sprd,syscon: phandle to the syscon which is in the same address area with
|
||||
the clock, and so we can get regmap for the clocks from the
|
||||
syscon device.
|
||||
|
||||
Example:
|
||||
|
||||
pmu_gate: pmu-gate {
|
||||
compatible = "sprd,sc9860-pmu-gate";
|
||||
sprd,syscon = <&pmu_regs>;
|
||||
clocks = <&ext_26m>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pll: pll {
|
||||
compatible = "sprd,sc9860-pll";
|
||||
sprd,syscon = <&ana_regs>;
|
||||
clocks = <&pmu_gate 0>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
ap_clk: clock-controller@20000000 {
|
||||
compatible = "sprd,sc9860-ap-clk";
|
||||
reg = <0 0x20000000 0 0x400>;
|
||||
clocks = <&ext_26m>, <&pll 0>,
|
||||
<&pmu_gate 0>;
|
||||
#clock-cells = <1>;
|
||||
};
|
@ -4,13 +4,14 @@ Allwinner Display Engine 2.0 Clock Control Binding
|
||||
Required properties :
|
||||
- compatible: must contain one of the following compatibles:
|
||||
- "allwinner,sun8i-a83t-de2-clk"
|
||||
- "allwinner,sun8i-h3-de2-clk"
|
||||
- "allwinner,sun8i-v3s-de2-clk"
|
||||
- "allwinner,sun50i-h5-de2-clk"
|
||||
|
||||
- reg: Must contain the registers base address and length
|
||||
- clocks: phandle to the clocks feeding the display engine subsystem.
|
||||
Three are needed:
|
||||
- "mod": the display engine module clock
|
||||
- "mod": the display engine module clock (on A83T it's the DE PLL)
|
||||
- "bus": the bus clock for the whole display engine subsystem
|
||||
- clock-names: Must contain the clock names described just above
|
||||
- resets: phandle to the reset control for the display engine subsystem.
|
||||
@ -19,7 +20,7 @@ Required properties :
|
||||
|
||||
Example:
|
||||
de2_clocks: clock@1000000 {
|
||||
compatible = "allwinner,sun8i-a83t-de2-clk";
|
||||
compatible = "allwinner,sun8i-h3-de2-clk";
|
||||
reg = <0x01000000 0x100000>;
|
||||
clocks = <&ccu CLK_BUS_DE>,
|
||||
<&ccu CLK_DE>;
|
||||
|
22
Bindings/crypto/arm-cryptocell.txt
Normal file
22
Bindings/crypto/arm-cryptocell.txt
Normal file
@ -0,0 +1,22 @@
|
||||
Arm TrustZone CryptoCell cryptographic engine
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "arm,cryptocell-712-ree".
|
||||
- reg: Base physical address of the engine and length of memory mapped region.
|
||||
- interrupts: Interrupt number for the device.
|
||||
|
||||
Optional properties:
|
||||
- interrupt-parent: The phandle for the interrupt controller that services
|
||||
interrupts for this device.
|
||||
- clocks: Reference to the crypto engine clock.
|
||||
- dma-coherent: Present if dma operations are coherent.
|
||||
|
||||
Examples:
|
||||
|
||||
arm_cc712: crypto@80000000 {
|
||||
compatible = "arm,cryptocell-712-ree";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = < 0 30 4 >;
|
||||
reg = < 0x80000000 0x10000 >;
|
||||
|
||||
};
|
@ -75,7 +75,7 @@ Required properties:
|
||||
- clock-frequency: must be present in the i2c controller node.
|
||||
|
||||
Example:
|
||||
atecc508a@C0 {
|
||||
atecc508a@c0 {
|
||||
compatible = "atmel,atecc508a";
|
||||
reg = <0xC0>;
|
||||
};
|
||||
|
@ -1,7 +1,8 @@
|
||||
Inside Secure SafeXcel cryptographic engine
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "inside-secure,safexcel-eip197".
|
||||
- compatible: Should be "inside-secure,safexcel-eip197" or
|
||||
"inside-secure,safexcel-eip97".
|
||||
- reg: Base physical address of the engine and length of memory mapped region.
|
||||
- interrupts: Interrupt numbers for the rings and engine.
|
||||
- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
|
||||
|
@ -2,7 +2,9 @@ Exynos Pseudo Random Number Generator
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should be "samsung,exynos4-rng".
|
||||
- compatible : One of:
|
||||
- "samsung,exynos4-rng" for Exynos4210 and Exynos4412
|
||||
- "samsung,exynos5250-prng" for Exynos5250+
|
||||
- reg : Specifies base physical address and size of the registers map.
|
||||
- clocks : Phandle to clock-controller plus clock-specifier pair.
|
||||
- clock-names : "secss" as a clock name.
|
||||
|
19
Bindings/crypto/st,stm32-cryp.txt
Normal file
19
Bindings/crypto/st,stm32-cryp.txt
Normal file
@ -0,0 +1,19 @@
|
||||
* STMicroelectronics STM32 CRYP
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "st,stm32f756-cryp".
|
||||
- reg: The address and length of the peripheral registers space
|
||||
- clocks: The input clock of the CRYP instance
|
||||
- interrupts: The CRYP interrupt
|
||||
|
||||
Optional properties:
|
||||
- resets: The input reset of the CRYP instance
|
||||
|
||||
Example:
|
||||
crypto@50060000 {
|
||||
compatible = "st,stm32f756-cryp";
|
||||
reg = <0x50060000 0x400>;
|
||||
interrupts = <79>;
|
||||
clocks = <&rcc 0 STM32F7_AHB2_CLOCK(CRYP)>;
|
||||
resets = <&rcc STM32F7_AHB2_RESET(CRYP)>;
|
||||
};
|
@ -20,7 +20,7 @@ Optional properties:
|
||||
|
||||
Example : NoC Probe nodes in Device Tree are listed below.
|
||||
|
||||
nocp_mem0_0: nocp@10CA1000 {
|
||||
nocp_mem0_0: nocp@10ca1000 {
|
||||
compatible = "samsung,exynos5420-nocp";
|
||||
reg = <0x10CA1000 0x200>;
|
||||
};
|
||||
|
@ -48,6 +48,10 @@ Required properties:
|
||||
Documentation/devicetree/bindings/reset/reset.txt,
|
||||
the reset-names should be "hdmitx_apb", "hdmitx", "hdmitx_phy"
|
||||
|
||||
Optional properties:
|
||||
- hdmi-supply: Optional phandle to an external 5V regulator to power the HDMI
|
||||
logic, as described in the file ../regulator/regulator.txt
|
||||
|
||||
Required nodes:
|
||||
|
||||
The connections to the HDMI ports are modeled using the OF graph
|
||||
|
@ -64,6 +64,10 @@ Required properties:
|
||||
- reg-names: should contain the names of the previous memory regions
|
||||
- interrupts: should contain the VENC Vsync interrupt number
|
||||
|
||||
Optional properties:
|
||||
- power-domains: Optional phandle to associated power domain as described in
|
||||
the file ../power/power_domain.txt
|
||||
|
||||
Required nodes:
|
||||
|
||||
The connections to the VPU output video ports are modeled using the OF graph
|
||||
|
@ -54,7 +54,7 @@ Video interfaces:
|
||||
|
||||
Example:
|
||||
|
||||
dsi@11C80000 {
|
||||
dsi@11c80000 {
|
||||
compatible = "samsung,exynos4210-mipi-dsi";
|
||||
reg = <0x11C80000 0x10000>;
|
||||
interrupts = <0 79 0>;
|
||||
|
@ -16,6 +16,7 @@ Required properties:
|
||||
- ddc: phandle to the hdmi ddc node
|
||||
- phy: phandle to the hdmi phy node
|
||||
- samsung,syscon-phandle: phandle for system controller node for PMU.
|
||||
- #sound-dai-cells: should be 0.
|
||||
|
||||
Required properties for Exynos 4210, 4212, 5420 and 5433:
|
||||
- clocks: list of clock IDs from SoC clock driver.
|
||||
|
25
Bindings/display/ilitek,ili9225.txt
Normal file
25
Bindings/display/ilitek,ili9225.txt
Normal file
@ -0,0 +1,25 @@
|
||||
Ilitek ILI9225 display panels
|
||||
|
||||
This binding is for display panels using an Ilitek ILI9225 controller in SPI
|
||||
mode.
|
||||
|
||||
Required properties:
|
||||
- compatible: "vot,v220hf01a-t", "ilitek,ili9225"
|
||||
- rs-gpios: Register select signal
|
||||
- reset-gpios: Reset pin
|
||||
|
||||
The node for this driver must be a child node of a SPI controller, hence
|
||||
all mandatory properties described in ../spi/spi-bus.txt must be specified.
|
||||
|
||||
Optional properties:
|
||||
- rotation: panel rotation in degrees counter clockwise (0,90,180,270)
|
||||
|
||||
Example:
|
||||
display@0{
|
||||
compatible = "vot,v220hf01a-t", "ilitek,ili9225";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <12000000>;
|
||||
rs-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
|
||||
rotation = <270>;
|
||||
};
|
49
Bindings/display/panel/ilitek,ili9322.txt
Normal file
49
Bindings/display/panel/ilitek,ili9322.txt
Normal file
@ -0,0 +1,49 @@
|
||||
Ilitek ILI9322 TFT panel driver with SPI control bus
|
||||
|
||||
This is a driver for 320x240 TFT panels, accepting a variety of input
|
||||
streams that get adapted and scaled to the panel. The panel output has
|
||||
960 TFT source driver pins and 240 TFT gate driver pins, VCOM, VCOML and
|
||||
VCOMH outputs.
|
||||
|
||||
Required properties:
|
||||
- compatible: "dlink,dir-685-panel", "ilitek,ili9322"
|
||||
(full system-specific compatible is always required to look up configuration)
|
||||
- reg: address of the panel on the SPI bus
|
||||
|
||||
Optional properties:
|
||||
- vcc-supply: core voltage supply, see regulator/regulator.txt
|
||||
- iovcc-supply: voltage supply for the interface input/output signals,
|
||||
see regulator/regulator.txt
|
||||
- vci-supply: voltage supply for analog parts, see regulator/regulator.txt
|
||||
- reset-gpios: a GPIO spec for the reset pin, see gpio/gpio.txt
|
||||
|
||||
The following optional properties only apply to RGB and YUV input modes and
|
||||
can be omitted for BT.656 input modes:
|
||||
|
||||
- pixelclk-active: see display/panel/display-timing.txt
|
||||
- de-active: see display/panel/display-timing.txt
|
||||
- hsync-active: see display/panel/display-timing.txt
|
||||
- vsync-active: see display/panel/display-timing.txt
|
||||
|
||||
The panel must obey the rules for a SPI slave device as specified in
|
||||
spi/spi-bus.txt
|
||||
|
||||
The device node can contain one 'port' child node with one child
|
||||
'endpoint' node, according to the bindings defined in
|
||||
media/video-interfaces.txt. This node should describe panel's video bus.
|
||||
|
||||
Example:
|
||||
|
||||
panel: display@0 {
|
||||
compatible = "dlink,dir-685-panel", "ilitek,ili9322";
|
||||
reg = <0>;
|
||||
vcc-supply = <&vdisp>;
|
||||
iovcc-supply = <&vdisp>;
|
||||
vci-supply = <&vdisp>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&display_out>;
|
||||
};
|
||||
};
|
||||
};
|
7
Bindings/display/panel/mitsubishi,aa070mc01.txt
Normal file
7
Bindings/display/panel/mitsubishi,aa070mc01.txt
Normal file
@ -0,0 +1,7 @@
|
||||
Mitsubishi "AA070MC01 7.0" WVGA TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "mitsubishi,aa070mc01-ca1"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
@ -78,6 +78,16 @@ used for panels that implement compatible control signals.
|
||||
while active. Active high reset signals can be supported by inverting the
|
||||
GPIO specifier polarity flag.
|
||||
|
||||
Power
|
||||
-----
|
||||
|
||||
- power-supply: display panels require power to be supplied. While several
|
||||
panels need more than one power supply with panel-specific constraints
|
||||
governing the order and timings of the power supplies, in many cases a single
|
||||
power supply is sufficient, either because the panel has a single power rail,
|
||||
or because all its power rails can be driven by the same supply. In that case
|
||||
the power-supply property specifies the supply powering the panel as a phandle
|
||||
to a regulator.
|
||||
|
||||
Backlight
|
||||
---------
|
||||
|
@ -32,6 +32,7 @@ Optional properties:
|
||||
- label: See panel-common.txt.
|
||||
- gpios: See panel-common.txt.
|
||||
- backlight: See panel-common.txt.
|
||||
- power-supply: See panel-common.txt.
|
||||
- data-mirror: If set, reverse the bit order described in the data mappings
|
||||
below on all data lanes, transmitting bits for slots 6 to 0 instead of
|
||||
0 to 6.
|
||||
|
41
Bindings/display/panel/sgd,gktw70sdae4se.txt
Normal file
41
Bindings/display/panel/sgd,gktw70sdae4se.txt
Normal file
@ -0,0 +1,41 @@
|
||||
Solomon Goldentek Display GKTW70SDAE4SE LVDS Display Panel
|
||||
==========================================================
|
||||
|
||||
The GKTW70SDAE4SE is a 7" WVGA TFT-LCD display panel.
|
||||
|
||||
These DT bindings follow the LVDS panel bindings defined in panel-lvds.txt
|
||||
with the following device-specific properties.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Shall contain "sgd,gktw70sdae4se" and "panel-lvds", in that order.
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
panel {
|
||||
compatible = "sgd,gktw70sdae4se", "panel-lvds";
|
||||
|
||||
width-mm = <153>;
|
||||
height-mm = <86>;
|
||||
|
||||
data-mapping = "jeida-18";
|
||||
|
||||
panel-timing {
|
||||
clock-frequency = <32000000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <39>;
|
||||
hfront-porch = <39>;
|
||||
vback-porch = <29>;
|
||||
vfront-porch = <13>;
|
||||
hsync-len = <47>;
|
||||
vsync-len = <2>;
|
||||
};
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&lvds_encoder>;
|
||||
};
|
||||
};
|
||||
};
|
@ -1,7 +1,7 @@
|
||||
Simple display panel
|
||||
|
||||
Required properties:
|
||||
- power-supply: regulator to provide the supply voltage
|
||||
- power-supply: See panel-common.txt
|
||||
|
||||
Optional properties:
|
||||
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
|
||||
|
29
Bindings/display/panel/tianma,tm070rvhg71.txt
Normal file
29
Bindings/display/panel/tianma,tm070rvhg71.txt
Normal file
@ -0,0 +1,29 @@
|
||||
Tianma Micro-electronics TM070RVHG71 7.0" WXGA TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "tianma,tm070rvhg71"
|
||||
- power-supply: single regulator to provide the supply voltage
|
||||
- backlight: phandle of the backlight device attached to the panel
|
||||
|
||||
Required nodes:
|
||||
- port: LVDS port mapping to connect this display
|
||||
|
||||
This panel needs single power supply voltage. Its backlight is conntrolled
|
||||
via PWM signal.
|
||||
|
||||
Example:
|
||||
--------
|
||||
|
||||
Example device-tree definition when connected to iMX6Q based board
|
||||
|
||||
panel: panel-lvds0 {
|
||||
compatible = "tianma,tm070rvhg71";
|
||||
backlight = <&backlight_lvds>;
|
||||
power-supply = <®_lvds>;
|
||||
|
||||
port {
|
||||
panel_in_lvds0: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
};
|
@ -1,7 +1,7 @@
|
||||
Toshiba 8.9" WXGA (1280x768) TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "toshiba,lt089ac29000.txt"
|
||||
- compatible: should be "toshiba,lt089ac29000"
|
||||
- power-supply: as specified in the base binding
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
|
@ -2,7 +2,7 @@ Toppoly TD028TTEC1 Panel
|
||||
========================
|
||||
|
||||
Required properties:
|
||||
- compatible: "toppoly,td028ttec1"
|
||||
- compatible: "tpo,td028ttec1"
|
||||
|
||||
Optional properties:
|
||||
- label: a symbolic name for the panel
|
||||
@ -14,7 +14,7 @@ Example
|
||||
-------
|
||||
|
||||
lcd-panel: td028ttec1@0 {
|
||||
compatible = "toppoly,td028ttec1";
|
||||
compatible = "tpo,td028ttec1";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <100000>;
|
||||
spi-cpol;
|
@ -3,6 +3,8 @@
|
||||
Required Properties:
|
||||
|
||||
- compatible: must be one of the following.
|
||||
- "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU
|
||||
- "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU
|
||||
- "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
|
||||
- "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
|
||||
- "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
|
||||
@ -27,10 +29,10 @@ Required Properties:
|
||||
- clock-names: Name of the clocks. This property is model-dependent.
|
||||
- R8A7779 uses a single functional clock. The clock doesn't need to be
|
||||
named.
|
||||
- R8A779[0123456] use one functional clock per channel and one clock per
|
||||
LVDS encoder (if available). The functional clocks must be named "du.x"
|
||||
with "x" being the channel numerical index. The LVDS clocks must be
|
||||
named "lvds.x" with "x" being the LVDS encoder numerical index.
|
||||
- All other DU instances use one functional clock per channel and one
|
||||
clock per LVDS encoder (if available). The functional clocks must be
|
||||
named "du.x" with "x" being the channel numerical index. The LVDS clocks
|
||||
must be named "lvds.x" with "x" being the LVDS encoder numerical index.
|
||||
- In addition to the functional and encoder clocks, all DU versions also
|
||||
support externally supplied pixel clocks. Those clocks are optional.
|
||||
When supplied they must be named "dclkin.x" with "x" being the input
|
||||
@ -49,16 +51,18 @@ bindings specified in Documentation/devicetree/bindings/graph.txt.
|
||||
The following table lists for each supported model the port number
|
||||
corresponding to each DU output.
|
||||
|
||||
Port 0 Port1 Port2 Port3
|
||||
Port0 Port1 Port2 Port3
|
||||
-----------------------------------------------------------------------------
|
||||
R8A7779 (H1) DPAD 0 DPAD 1 - -
|
||||
R8A7790 (H2) DPAD LVDS 0 LVDS 1 -
|
||||
R8A7791 (M2-W) DPAD LVDS 0 - -
|
||||
R8A7792 (V2H) DPAD 0 DPAD 1 - -
|
||||
R8A7793 (M2-N) DPAD LVDS 0 - -
|
||||
R8A7794 (E2) DPAD 0 DPAD 1 - -
|
||||
R8A7795 (H3) DPAD HDMI 0 HDMI 1 LVDS
|
||||
R8A7796 (M3-W) DPAD HDMI LVDS -
|
||||
R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - -
|
||||
R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - -
|
||||
R8A7779 (R-Car H1) DPAD 0 DPAD 1 - -
|
||||
R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 -
|
||||
R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - -
|
||||
R8A7792 (R-Car V2H) DPAD 0 DPAD 1 - -
|
||||
R8A7793 (R-Car M2-N) DPAD 0 LVDS 0 - -
|
||||
R8A7794 (R-Car E2) DPAD 0 DPAD 1 - -
|
||||
R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0
|
||||
R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 -
|
||||
|
||||
|
||||
Example: R8A7795 (R-Car H3) ES2.0 DU
|
||||
|
@ -7,6 +7,7 @@ buffer to an external LCD interface.
|
||||
Required properties:
|
||||
- compatible: value should be one of the following
|
||||
"rockchip,rk3036-vop";
|
||||
"rockchip,rk3126-vop";
|
||||
"rockchip,rk3288-vop";
|
||||
"rockchip,rk3368-vop";
|
||||
"rockchip,rk3366-vop";
|
||||
|
@ -15,6 +15,10 @@ Required properties:
|
||||
"de_be1-lcd1"
|
||||
"de_be0-lcd0-hdmi"
|
||||
"de_be1-lcd1-hdmi"
|
||||
"mixer0-lcd0"
|
||||
"mixer0-lcd0-hdmi"
|
||||
"mixer1-lcd1-hdmi"
|
||||
"mixer1-lcd1-tve"
|
||||
|
||||
Example:
|
||||
|
||||
|
35
Bindings/display/sitronix,st7735r.txt
Normal file
35
Bindings/display/sitronix,st7735r.txt
Normal file
@ -0,0 +1,35 @@
|
||||
Sitronix ST7735R display panels
|
||||
|
||||
This binding is for display panels using a Sitronix ST7735R controller in SPI
|
||||
mode.
|
||||
|
||||
Required properties:
|
||||
- compatible: "jianda,jd-t18003-t01", "sitronix,st7735r"
|
||||
- dc-gpios: Display data/command selection (D/CX)
|
||||
- reset-gpios: Reset signal (RSTX)
|
||||
|
||||
The node for this driver must be a child node of a SPI controller, hence
|
||||
all mandatory properties described in ../spi/spi-bus.txt must be specified.
|
||||
|
||||
Optional properties:
|
||||
- rotation: panel rotation in degrees counter clockwise (0,90,180,270)
|
||||
- backlight: phandle of the backlight device attached to the panel
|
||||
|
||||
Example:
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "gpio-backlight";
|
||||
gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
|
||||
}
|
||||
|
||||
...
|
||||
|
||||
display@0{
|
||||
compatible = "jianda,jd-t18003-t01", "sitronix,st7735r";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <32000000>;
|
||||
dc-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>;
|
||||
rotation = <270>;
|
||||
backlight = &backlight;
|
||||
};
|
@ -119,7 +119,7 @@ Example:
|
||||
/ {
|
||||
...
|
||||
|
||||
vtg_main_slave: sti-vtg-main-slave@fe85A800 {
|
||||
vtg_main_slave: sti-vtg-main-slave@fe85a800 {
|
||||
compatible = "st,vtg";
|
||||
reg = <0xfe85A800 0x300>;
|
||||
interrupts = <GIC_SPI 175 IRQ_TYPE_NONE>;
|
||||
|
@ -10,7 +10,11 @@
|
||||
- "lcd" for the clock feeding the output pixel clock & IP clock.
|
||||
- resets: reset to be used by the device (defined by use of RCC macro).
|
||||
Required nodes:
|
||||
- Video port for RGB output.
|
||||
- Video port for DPI RGB output: ltdc has one video port with up to 2
|
||||
endpoints:
|
||||
- for external dpi rgb panel or bridge, using gpios.
|
||||
- for internal dpi input of the MIPI DSI host controller.
|
||||
Note: These 2 endpoints cannot be activated simultaneously.
|
||||
|
||||
* STMicroelectronics STM32 DSI controller specific extensions to Synopsys
|
||||
DesignWare MIPI DSI host controller
|
||||
|
@ -93,6 +93,7 @@ Required properties:
|
||||
* allwinner,sun6i-a31s-tcon
|
||||
* allwinner,sun7i-a20-tcon
|
||||
* allwinner,sun8i-a33-tcon
|
||||
* allwinner,sun8i-a83t-tcon-lcd
|
||||
* allwinner,sun8i-v3s-tcon
|
||||
- reg: base address and size of memory-mapped region
|
||||
- interrupts: interrupt associated to this IP
|
||||
@ -121,6 +122,14 @@ Required properties:
|
||||
On SoCs other than the A33 and V3s, there is one more clock required:
|
||||
- 'tcon-ch1': The clock driving the TCON channel 1
|
||||
|
||||
On SoCs that support LVDS (all SoCs but the A13, H3, H5 and V3s), you
|
||||
need one more reset line:
|
||||
- 'lvds': The reset line driving the LVDS logic
|
||||
|
||||
And on the A23, A31, A31s and A33, you need one more clock line:
|
||||
- 'lvds-alt': An alternative clock source, separate from the TCON channel 0
|
||||
clock, that can be used to drive the LVDS clock
|
||||
|
||||
DRC
|
||||
---
|
||||
|
||||
@ -216,6 +225,7 @@ supported.
|
||||
|
||||
Required properties:
|
||||
- compatible: value must be one of:
|
||||
* allwinner,sun8i-a83t-de2-mixer-0
|
||||
* allwinner,sun8i-v3s-de2-mixer
|
||||
- reg: base address and size of the memory-mapped region.
|
||||
- clocks: phandles to the clocks feeding the mixer
|
||||
@ -245,6 +255,7 @@ Required properties:
|
||||
* allwinner,sun6i-a31s-display-engine
|
||||
* allwinner,sun7i-a20-display-engine
|
||||
* allwinner,sun8i-a33-display-engine
|
||||
* allwinner,sun8i-a83t-display-engine
|
||||
* allwinner,sun8i-v3s-display-engine
|
||||
|
||||
- allwinner,pipelines: list of phandle to the display engine
|
||||
|
@ -206,21 +206,33 @@ of the following host1x client modules:
|
||||
- "nvidia,tegra132-sor": for Tegra132
|
||||
- "nvidia,tegra210-sor": for Tegra210
|
||||
- "nvidia,tegra210-sor1": for Tegra210
|
||||
- "nvidia,tegra186-sor": for Tegra186
|
||||
- "nvidia,tegra186-sor1": for Tegra186
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt outputs from the controller.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- sor: clock input for the SOR hardware
|
||||
- source: source clock for the SOR clock
|
||||
- out: SOR output clock
|
||||
- parent: input for the pixel clock
|
||||
- dp: reference clock for the SOR clock
|
||||
- safe: safe reference for the SOR clock during power up
|
||||
|
||||
For Tegra186 and later:
|
||||
- pad: SOR pad output clock (on Tegra186 and later)
|
||||
|
||||
Obsolete:
|
||||
- source: source clock for the SOR clock (obsolete, use "out" instead)
|
||||
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- sor
|
||||
|
||||
Required properties on Tegra186 and later:
|
||||
- nvidia,interface: index of the SOR interface
|
||||
|
||||
Optional properties:
|
||||
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
|
||||
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
|
||||
|
@ -47,6 +47,11 @@ Required properties:
|
||||
- clocks: handle to fclk
|
||||
- clock-names: "fck"
|
||||
|
||||
Optional properties:
|
||||
- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
|
||||
in bytes per second
|
||||
|
||||
|
||||
HDMI
|
||||
----
|
||||
|
||||
|
@ -28,6 +28,10 @@ Required properties:
|
||||
- ti,hwmods: "dss_dispc"
|
||||
- interrupts: the DISPC interrupt
|
||||
|
||||
Optional properties:
|
||||
- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
|
||||
in bytes per second
|
||||
|
||||
|
||||
RFBI
|
||||
----
|
||||
|
@ -37,6 +37,10 @@ Required properties:
|
||||
- clocks: handle to fclk
|
||||
- clock-names: "fck"
|
||||
|
||||
Optional properties:
|
||||
- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
|
||||
in bytes per second
|
||||
|
||||
|
||||
RFBI
|
||||
----
|
||||
|
@ -36,6 +36,10 @@ Required properties:
|
||||
- clocks: handle to fclk
|
||||
- clock-names: "fck"
|
||||
|
||||
Optional properties:
|
||||
- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
|
||||
in bytes per second
|
||||
|
||||
|
||||
RFBI
|
||||
----
|
||||
|
@ -36,6 +36,10 @@ Required properties:
|
||||
- clocks: handle to fclk
|
||||
- clock-names: "fck"
|
||||
|
||||
Optional properties:
|
||||
- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
|
||||
in bytes per second
|
||||
|
||||
|
||||
RFBI
|
||||
----
|
||||
|
@ -11,7 +11,11 @@ Required properties:
|
||||
interrupts.
|
||||
|
||||
Optional properties:
|
||||
- clocks: Optional reference to the clock used by the XOR engine.
|
||||
- clocks: Optional reference to the clocks used by the XOR engine.
|
||||
- clock-names: mandatory if there is a second clock, in this case the
|
||||
name must be "core" for the first clock and "reg" for the second
|
||||
one
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
|
@ -47,8 +47,8 @@ When the OS is not in control of the management interface (i.e. it's a guest),
|
||||
the channel nodes appear on their own, not under a management node.
|
||||
|
||||
Required properties:
|
||||
- compatible: must contain "qcom,hidma-1.0" for initial HW or "qcom,hidma-1.1"
|
||||
for MSI capable HW.
|
||||
- compatible: must contain "qcom,hidma-1.0" for initial HW or
|
||||
"qcom,hidma-1.1"/"qcom,hidma-1.2" for MSI capable HW.
|
||||
- reg: Addresses for the transfer and event channel
|
||||
- interrupts: Should contain the event interrupt
|
||||
- desc-count: Number of asynchronous requests this channel can handle
|
||||
|
@ -64,6 +64,6 @@ Example:
|
||||
reg = <0xe0000000 0x1000>;
|
||||
interrupts = <0 35 0x4>;
|
||||
dmas = <&dmahost 12 0 1>,
|
||||
<&dmahost 13 0 1 0>;
|
||||
<&dmahost 13 1 0>;
|
||||
dma-names = "rx", "rx";
|
||||
};
|
||||
|
@ -15,7 +15,7 @@ Optional properties:
|
||||
|
||||
Example:
|
||||
|
||||
dma: dma-controller@801C0000 {
|
||||
dma: dma-controller@801c0000 {
|
||||
compatible = "stericsson,db8500-dma40", "stericsson,dma40";
|
||||
reg = <0x801C0000 0x1000 0x40010000 0x800>;
|
||||
reg-names = "base", "lcpa";
|
||||
|
78
Bindings/eeprom/at24.txt
Normal file
78
Bindings/eeprom/at24.txt
Normal file
@ -0,0 +1,78 @@
|
||||
EEPROMs (I2C)
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Must be a "<manufacturer>,<model>" pair. The following <model>
|
||||
values are supported (assuming "atmel" as manufacturer):
|
||||
|
||||
"atmel,24c00",
|
||||
"atmel,24c01",
|
||||
"atmel,24cs01",
|
||||
"atmel,24c02",
|
||||
"atmel,24cs02",
|
||||
"atmel,24mac402",
|
||||
"atmel,24mac602",
|
||||
"atmel,spd",
|
||||
"atmel,24c04",
|
||||
"atmel,24cs04",
|
||||
"atmel,24c08",
|
||||
"atmel,24cs08",
|
||||
"atmel,24c16",
|
||||
"atmel,24cs16",
|
||||
"atmel,24c32",
|
||||
"atmel,24cs32",
|
||||
"atmel,24c64",
|
||||
"atmel,24cs64",
|
||||
"atmel,24c128",
|
||||
"atmel,24c256",
|
||||
"atmel,24c512",
|
||||
"atmel,24c1024",
|
||||
|
||||
If <manufacturer> is not "atmel", then a fallback must be used
|
||||
with the same <model> and "atmel" as manufacturer.
|
||||
|
||||
Example:
|
||||
compatible = "microchip,24c128", "atmel,24c128";
|
||||
|
||||
Supported manufacturers are:
|
||||
|
||||
"catalyst",
|
||||
"microchip",
|
||||
"nxp",
|
||||
"ramtron",
|
||||
"renesas",
|
||||
"st",
|
||||
|
||||
Some vendors use different model names for chips which are just
|
||||
variants of the above. Known such exceptions are listed below:
|
||||
|
||||
"renesas,r1ex24002" - the fallback is "atmel,24c02"
|
||||
|
||||
- reg: The I2C address of the EEPROM.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- pagesize: The length of the pagesize for writing. Please consult the
|
||||
manual of your device, that value varies a lot. A wrong value
|
||||
may result in data loss! If not specified, a safety value of
|
||||
'1' is used which will be very slow.
|
||||
|
||||
- read-only: This parameterless property disables writes to the eeprom.
|
||||
|
||||
- size: Total eeprom size in bytes.
|
||||
|
||||
- no-read-rollover: This parameterless property indicates that the
|
||||
multi-address eeprom does not automatically roll over
|
||||
reads to the next slave address. Please consult the
|
||||
manual of your device.
|
||||
|
||||
- wp-gpios: GPIO to which the write-protect pin of the chip is connected.
|
||||
|
||||
Example:
|
||||
|
||||
eeprom@52 {
|
||||
compatible = "atmel,24c32";
|
||||
reg = <0x52>;
|
||||
pagesize = <32>;
|
||||
wp-gpios = <&gpio1 3 0>;
|
||||
};
|
@ -11,7 +11,9 @@ Required properties:
|
||||
- spi-max-frequency : max spi frequency to use
|
||||
- pagesize : size of the eeprom page
|
||||
- size : total eeprom size in bytes
|
||||
- address-width : number of address bits (one of 8, 16, or 24)
|
||||
- address-width : number of address bits (one of 8, 9, 16, or 24).
|
||||
For 9 bits, the MSB of the address is sent as bit 3 of the instruction
|
||||
byte, before the address byte.
|
||||
|
||||
Optional properties:
|
||||
- spi-cpha : SPI shifted clock phase, as per spi-bus bindings.
|
||||
|
@ -1,47 +0,0 @@
|
||||
EEPROMs (I2C)
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "<manufacturer>,<type>", like these:
|
||||
|
||||
"atmel,24c00", "atmel,24c01", "atmel,24c02", "atmel,24c04",
|
||||
"atmel,24c08", "atmel,24c16", "atmel,24c32", "atmel,24c64",
|
||||
"atmel,24c128", "atmel,24c256", "atmel,24c512", "atmel,24c1024"
|
||||
|
||||
"catalyst,24c32"
|
||||
|
||||
"microchip,24c128"
|
||||
|
||||
"ramtron,24c64"
|
||||
|
||||
"renesas,r1ex24002"
|
||||
|
||||
The following manufacturers values have been deprecated:
|
||||
"at", "at24"
|
||||
|
||||
If there is no specific driver for <manufacturer>, a generic
|
||||
device with <type> and manufacturer "atmel" should be used.
|
||||
Possible types are:
|
||||
"24c00", "24c01", "24c02", "24c04", "24c08", "24c16", "24c32", "24c64",
|
||||
"24c128", "24c256", "24c512", "24c1024", "spd"
|
||||
|
||||
- reg : the I2C address of the EEPROM
|
||||
|
||||
Optional properties:
|
||||
|
||||
- pagesize : the length of the pagesize for writing. Please consult the
|
||||
manual of your device, that value varies a lot. A wrong value
|
||||
may result in data loss! If not specified, a safety value of
|
||||
'1' is used which will be very slow.
|
||||
|
||||
- read-only: this parameterless property disables writes to the eeprom
|
||||
|
||||
- size: total eeprom size in bytes
|
||||
|
||||
Example:
|
||||
|
||||
eeprom@52 {
|
||||
compatible = "atmel,24c32";
|
||||
reg = <0x52>;
|
||||
pagesize = <32>;
|
||||
};
|
@ -21,7 +21,7 @@ Documentation/devicetree/bindings/gpio/gpio.txt
|
||||
|
||||
Example:
|
||||
|
||||
gpioa: gpio@FF140000 {
|
||||
gpioa: gpio@ff140000 {
|
||||
compatible = "abilis,tb10x-gpio";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
@ -1,10 +1,17 @@
|
||||
AXP209 GPIO controller
|
||||
AXP209 GPIO & pinctrl controller
|
||||
|
||||
This driver follows the usual GPIO bindings found in
|
||||
Documentation/devicetree/bindings/gpio/gpio.txt
|
||||
|
||||
This driver follows the usual pinctrl bindings found in
|
||||
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
|
||||
|
||||
This driver employs the per-pin muxing pattern.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "x-powers,axp209-gpio"
|
||||
- compatible: Should be one of:
|
||||
- "x-powers,axp209-gpio"
|
||||
- "x-powers,axp813-gpio"
|
||||
- #gpio-cells: Should be two. The first cell is the pin number and the
|
||||
second is the GPIO flags.
|
||||
- gpio-controller: Marks the device node as a GPIO controller.
|
||||
@ -28,3 +35,41 @@ axp209: pmic@34 {
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
The GPIOs can be muxed to other functions and therefore, must be a subnode of
|
||||
axp_gpio.
|
||||
|
||||
Example:
|
||||
|
||||
&axp_gpio {
|
||||
gpio0_adc: gpio0-adc {
|
||||
pins = "GPIO0";
|
||||
function = "adc";
|
||||
};
|
||||
};
|
||||
|
||||
&example_node {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpio0_adc>;
|
||||
};
|
||||
|
||||
GPIOs and their functions
|
||||
-------------------------
|
||||
|
||||
Each GPIO is independent from the other (i.e. GPIO0 in gpio_in function does
|
||||
not force GPIO1 and GPIO2 to be in gpio_in function as well).
|
||||
|
||||
axp209
|
||||
------
|
||||
GPIO | Functions
|
||||
------------------------
|
||||
GPIO0 | gpio_in, gpio_out, ldo, adc
|
||||
GPIO1 | gpio_in, gpio_out, ldo, adc
|
||||
GPIO2 | gpio_in, gpio_out
|
||||
|
||||
axp813
|
||||
------
|
||||
GPIO | Functions
|
||||
------------------------
|
||||
GPIO0 | gpio_in, gpio_out, ldo, adc
|
||||
GPIO1 | gpio_in, gpio_out, ldo
|
||||
|
@ -27,7 +27,7 @@ Optional properties:
|
||||
|
||||
Example:
|
||||
|
||||
gpio1: stp@E100BB0 {
|
||||
gpio1: stp@e100bb0 {
|
||||
compatible = "lantiq,gpio-stp-xway";
|
||||
reg = <0xE100BB0 0x40>;
|
||||
#gpio-cells = <2>;
|
||||
|
@ -290,7 +290,7 @@ pins 50..69.
|
||||
|
||||
Example 2:
|
||||
|
||||
gpio_pio_i: gpio-controller@14B0 {
|
||||
gpio_pio_i: gpio-controller@14b0 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
|
||||
reg = <0x1480 0x18>;
|
||||
|
@ -5,7 +5,7 @@ Required Properties:
|
||||
- compatible: should contain one or more of the following:
|
||||
- "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO controller.
|
||||
- "renesas,gpio-r8a7745": for R8A7745 (RZ/G1E) compatible GPIO controller.
|
||||
- "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller.
|
||||
- "renesas,gpio-r8a7778": for R8A7778 (R-Car M1) compatible GPIO controller.
|
||||
- "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller.
|
||||
- "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller.
|
||||
- "renesas,gpio-r8a7791": for R8A7791 (R-Car M2-W) compatible GPIO controller.
|
||||
|
@ -17,6 +17,7 @@ Required properties:
|
||||
+ rockchip,rk3066-mali
|
||||
+ rockchip,rk3188-mali
|
||||
+ rockchip,rk3228-mali
|
||||
+ rockchip,rk3328-mali
|
||||
+ stericsson,db8500-mali
|
||||
|
||||
- reg: Physical base address and length of the GPU registers
|
||||
|
@ -22,8 +22,9 @@ Required properties for pwm-tacho node:
|
||||
- compatible : should be "aspeed,ast2400-pwm-tacho" for AST2400 and
|
||||
"aspeed,ast2500-pwm-tacho" for AST2500.
|
||||
|
||||
- clocks : a fixed clock providing input clock frequency(PWM
|
||||
and Fan Tach clock)
|
||||
- clocks : phandle to clock provider with the clock number in the second cell
|
||||
|
||||
- resets : phandle to reset controller with the reset number in the second cell
|
||||
|
||||
fan subnode format:
|
||||
===================
|
||||
@ -48,19 +49,14 @@ Required properties for each child node:
|
||||
|
||||
Examples:
|
||||
|
||||
pwm_tacho_fixed_clk: fixedclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
pwm_tacho: pwmtachocontroller@1e786000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#cooling-cells = <2>;
|
||||
reg = <0x1E786000 0x1000>;
|
||||
compatible = "aspeed,ast2500-pwm-tacho";
|
||||
clocks = <&pwm_tacho_fixed_clk>;
|
||||
clocks = <&syscon ASPEED_CLK_APB>;
|
||||
resets = <&syscon ASPEED_RESET_PWM>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
|
||||
|
||||
|
@ -54,7 +54,7 @@ Optional properties:
|
||||
|
||||
|
||||
Example:
|
||||
i2c@12CA0000 {
|
||||
i2c@12ca0000 {
|
||||
compatible = "acme,some-i2c-device";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
@ -11,7 +11,7 @@ Required properties:
|
||||
|
||||
Examples:
|
||||
|
||||
lpi2c7: lpi2c7@40A50000 {
|
||||
lpi2c7: lpi2c7@40a50000 {
|
||||
compatible = "fsl,imx8dv-lpi2c";
|
||||
reg = <0x40A50000 0x10000>;
|
||||
interrupt-parent = <&intc>;
|
||||
|
@ -1,7 +1,11 @@
|
||||
Amlogic Meson I2C controller
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "amlogic,meson6-i2c" or "amlogic,meson-gxbb-i2c"
|
||||
- compatible: must be:
|
||||
"amlogic,meson6-i2c" for Meson8 and compatible SoCs
|
||||
"amlogic,meson-gxbb-i2c" for GXBB and compatible SoCs
|
||||
"amlogic,meson-axg-i2c"for AXG and compatible SoCs
|
||||
|
||||
- reg: physical address and length of the device registers
|
||||
- interrupts: a single interrupt specifier
|
||||
- clocks: clock for the device
|
||||
|
@ -5,6 +5,7 @@ The MediaTek's I2C controller is used to interface with I2C devices.
|
||||
Required properties:
|
||||
- compatible: value should be either of the following.
|
||||
"mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for MediaTek MT2701
|
||||
"mediatek,mt2712-i2c": for MediaTek MT2712
|
||||
"mediatek,mt6577-i2c": for MediaTek MT6577
|
||||
"mediatek,mt6589-i2c": for MediaTek MT6589
|
||||
"mediatek,mt7622-i2c": for MediaTek MT7622
|
||||
|
@ -1,10 +1,19 @@
|
||||
* NXP PCA954x I2C bus switch
|
||||
|
||||
The driver supports NXP PCA954x and PCA984x I2C mux/switch devices.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must contain one of the following.
|
||||
"nxp,pca9540", "nxp,pca9542", "nxp,pca9543", "nxp,pca9544",
|
||||
"nxp,pca9545", "nxp,pca9546", "nxp,pca9547", "nxp,pca9548"
|
||||
"nxp,pca9540",
|
||||
"nxp,pca9542",
|
||||
"nxp,pca9543",
|
||||
"nxp,pca9544",
|
||||
"nxp,pca9545",
|
||||
"nxp,pca9546", "nxp,pca9846",
|
||||
"nxp,pca9547", "nxp,pca9847",
|
||||
"nxp,pca9548", "nxp,pca9848",
|
||||
"nxp,pca9849"
|
||||
|
||||
- reg: The I2C address of the device.
|
||||
|
||||
|
@ -25,6 +25,15 @@ default frequency is 100kHz
|
||||
whenever you're using the "allwinner,sun6i-a31-i2c"
|
||||
compatible.
|
||||
|
||||
- clocks: : pointers to the reference clocks for this device, the
|
||||
first one is the one used for the clock on the i2c bus,
|
||||
the second one is the clock used to acces the registers
|
||||
of the controller
|
||||
|
||||
- clock-names : names of used clocks, mandatory if the second clock is
|
||||
used, the name must be "core", and "reg" (the latter is
|
||||
only for Armada 7K/8K).
|
||||
|
||||
Examples:
|
||||
|
||||
i2c@11000 {
|
||||
@ -42,3 +51,14 @@ For the Armada XP:
|
||||
interrupts = <29>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
For the Armada 7040:
|
||||
|
||||
i2c@701000 {
|
||||
compatible = "marvell,mv78230-i2c";
|
||||
reg = <0x701000 0x20>;
|
||||
interrupts = <29>;
|
||||
clock-frequency = <100000>;
|
||||
clock-names = "core", "reg";
|
||||
clocks = <&core_clock>, <®_clock>;
|
||||
};
|
||||
|
@ -15,7 +15,6 @@ Required properties:
|
||||
- "clkin" for the reference clock (typically XTAL)
|
||||
- "core" for the SAR ADC core clock
|
||||
optional clocks:
|
||||
- "sana" for the analog clock
|
||||
- "adc_clk" for the ADC (sampling) clock
|
||||
- "adc_sel" for the ADC (sampling) clock mux
|
||||
- vref-supply: the regulator supply for the ADC reference voltage
|
||||
|
@ -8,6 +8,7 @@ Required properties:
|
||||
- reg: memory window mapping address and length
|
||||
- clocks: Input clock used to derive the sample clock. Expected to be the
|
||||
SoC's APB clock.
|
||||
- resets: Reset controller phandle
|
||||
- #io-channel-cells: Must be set to <1> to indicate channels are selected
|
||||
by index.
|
||||
|
||||
@ -15,6 +16,7 @@ Example:
|
||||
adc@1e6e9000 {
|
||||
compatible = "aspeed,ast2400-adc";
|
||||
reg = <0x1e6e9000 0xb0>;
|
||||
clocks = <&clk_apb>;
|
||||
clocks = <&syscon ASPEED_CLK_APB>;
|
||||
resets = <&syscon ASPEED_RESET_ADC>;
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
@ -17,6 +17,11 @@ Required properties:
|
||||
This property uses the IRQ edge types values: IRQ_TYPE_EDGE_RISING ,
|
||||
IRQ_TYPE_EDGE_FALLING or IRQ_TYPE_EDGE_BOTH
|
||||
|
||||
Optional properties:
|
||||
- dmas: Phandle to dma channel for the ADC.
|
||||
- dma-names: Must be "rx" when dmas property is being used.
|
||||
See ../../dma/dma.txt for details.
|
||||
|
||||
Example:
|
||||
|
||||
adc: adc@fc030000 {
|
||||
@ -31,4 +36,6 @@ adc: adc@fc030000 {
|
||||
vddana-supply = <&vdd_3v3_lp_reg>;
|
||||
vref-supply = <&vdd_3v3_lp_reg>;
|
||||
atmel,trigger-edge-type = <IRQ_TYPE_EDGE_BOTH>;
|
||||
dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
|
||||
dma-names = "rx";
|
||||
}
|
||||
|
13
Bindings/iio/adc/sigma-delta-modulator.txt
Normal file
13
Bindings/iio/adc/sigma-delta-modulator.txt
Normal file
@ -0,0 +1,13 @@
|
||||
Device-Tree bindings for sigma delta modulator
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "ads1201", "sd-modulator". "sd-modulator" can be use
|
||||
as a generic SD modulator if modulator not specified in compatible list.
|
||||
- #io-channel-cells = <0>: See the IIO bindings section "IIO consumers".
|
||||
|
||||
Example node:
|
||||
|
||||
ads1202: adc@0 {
|
||||
compatible = "sd-modulator";
|
||||
#io-channel-cells = <0>;
|
||||
};
|
@ -62,6 +62,15 @@ Required properties:
|
||||
- st,adc-channels: List of single-ended channels muxed for this ADC.
|
||||
It can have up to 16 channels on stm32f4 or 20 channels on stm32h7, numbered
|
||||
from 0 to 15 or 19 (resp. for in0..in15 or in0..in19).
|
||||
- st,adc-diff-channels: List of differential channels muxed for this ADC.
|
||||
Depending on part used, some channels can be configured as differential
|
||||
instead of single-ended (e.g. stm32h7). List here positive and negative
|
||||
inputs pairs as <vinp vinn>, <vinp vinn>,... vinp and vinn are numbered
|
||||
from 0 to 19 on stm32h7)
|
||||
Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is required.
|
||||
Both properties can be used together. Some channels can be used as
|
||||
single-ended and some other ones as differential (mixed). But channels
|
||||
can't be configured both as single-ended and differential (invalid).
|
||||
- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers" in
|
||||
Documentation/devicetree/bindings/iio/iio-bindings.txt
|
||||
|
||||
@ -111,3 +120,18 @@ Example:
|
||||
...
|
||||
other adc child nodes follow...
|
||||
};
|
||||
|
||||
Example to setup:
|
||||
- channel 1 as single-ended
|
||||
- channels 2 & 3 as differential (with resp. 6 & 7 negative inputs)
|
||||
|
||||
adc: adc@40022000 {
|
||||
compatible = "st,stm32h7-adc-core";
|
||||
...
|
||||
adc1: adc@0 {
|
||||
compatible = "st,stm32h7-adc";
|
||||
...
|
||||
st,adc-channels = <1>;
|
||||
st,adc-diff-channels = <2 6>, <3 7>;
|
||||
};
|
||||
};
|
||||
|
128
Bindings/iio/adc/st,stm32-dfsdm-adc.txt
Normal file
128
Bindings/iio/adc/st,stm32-dfsdm-adc.txt
Normal file
@ -0,0 +1,128 @@
|
||||
STMicroelectronics STM32 DFSDM ADC device driver
|
||||
|
||||
|
||||
STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
|
||||
interface external sigma delta modulators to STM32 micro controllers.
|
||||
It is mainly targeted for:
|
||||
- Sigma delta modulators (motor control, metering...)
|
||||
- PDM microphones (audio digital microphone)
|
||||
|
||||
It features up to 8 serial digital interfaces (SPI or Manchester) and
|
||||
up to 4 filters on stm32h7.
|
||||
|
||||
Each child node match with a filter instance.
|
||||
|
||||
Contents of a STM32 DFSDM root node:
|
||||
------------------------------------
|
||||
Required properties:
|
||||
- compatible: Should be "st,stm32h7-dfsdm".
|
||||
- reg: Offset and length of the DFSDM block register set.
|
||||
- clocks: IP and serial interfaces clocking. Should be set according
|
||||
to rcc clock ID and "clock-names".
|
||||
- clock-names: Input clock name "dfsdm" must be defined,
|
||||
"audio" is optional. If defined CLKOUT is based on the audio
|
||||
clock, else "dfsdm" is used.
|
||||
- #interrupt-cells = <1>;
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
|
||||
Optional properties:
|
||||
- spi-max-frequency: Requested only for SPI master mode.
|
||||
SPI clock OUT frequency (Hz). This clock must be set according
|
||||
to "clock" property. Frequency must be a multiple of the rcc
|
||||
clock frequency. If not, SPI CLKOUT frequency will not be
|
||||
accurate.
|
||||
|
||||
Contents of a STM32 DFSDM child nodes:
|
||||
--------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be:
|
||||
"st,stm32-dfsdm-adc" for sigma delta ADCs
|
||||
"st,stm32-dfsdm-dmic" for audio digital microphone.
|
||||
- reg: Specifies the DFSDM filter instance used.
|
||||
- interrupts: IRQ lines connected to each DFSDM filter instance.
|
||||
- st,adc-channels: List of single-ended channels muxed for this ADC.
|
||||
valid values:
|
||||
"st,stm32h7-dfsdm" compatibility: 0 to 7.
|
||||
- st,adc-channel-names: List of single-ended channel names.
|
||||
- st,filter-order: SinC filter order from 0 to 5.
|
||||
0: FastSinC
|
||||
[1-5]: order 1 to 5.
|
||||
For audio purpose it is recommended to use order 3 to 5.
|
||||
- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers".
|
||||
|
||||
Required properties for "st,stm32-dfsdm-adc" compatibility:
|
||||
- io-channels: From common IIO binding. Used to pipe external sigma delta
|
||||
modulator or internal ADC output to DFSDM channel.
|
||||
This is not required for "st,stm32-dfsdm-pdm" compatibility as
|
||||
PDM microphone is binded in Audio DT node.
|
||||
|
||||
Required properties for "st,stm32-dfsdm-pdm" compatibility:
|
||||
- #sound-dai-cells: Must be set to 0.
|
||||
- dma: DMA controller phandle and DMA request line associated to the
|
||||
filter instance (specified by the field "reg")
|
||||
- dma-names: Must be "rx"
|
||||
|
||||
Optional properties:
|
||||
- st,adc-channel-types: Single-ended channel input type.
|
||||
- "SPI_R": SPI with data on rising edge (default)
|
||||
- "SPI_F": SPI with data on falling edge
|
||||
- "MANCH_R": manchester codec, rising edge = logic 0
|
||||
- "MANCH_F": manchester codec, falling edge = logic 1
|
||||
- st,adc-channel-clk-src: Conversion clock source.
|
||||
- "CLKIN": external SPI clock (CLKIN x)
|
||||
- "CLKOUT": internal SPI clock (CLKOUT) (default)
|
||||
- "CLKOUT_F": internal SPI clock divided by 2 (falling edge).
|
||||
- "CLKOUT_R": internal SPI clock divided by 2 (rising edge).
|
||||
|
||||
- st,adc-alt-channel: Must be defined if two sigma delta modulator are
|
||||
connected on same SPI input.
|
||||
If not set, channel n is connected to SPI input n.
|
||||
If set, channel n is connected to SPI input n + 1.
|
||||
|
||||
- st,filter0-sync: Set to 1 to synchronize with DFSDM filter instance 0.
|
||||
Used for multi microphones synchronization.
|
||||
|
||||
Example of a sigma delta adc connected on DFSDM SPI port 0
|
||||
and a pdm microphone connected on DFSDM SPI port 1:
|
||||
|
||||
ads1202: simple_sd_adc@0 {
|
||||
compatible = "ads1202";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
dfsdm: dfsdm@40017000 {
|
||||
compatible = "st,stm32h7-dfsdm";
|
||||
reg = <0x40017000 0x400>;
|
||||
clocks = <&rcc DFSDM1_CK>;
|
||||
clock-names = "dfsdm";
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dfsdm_adc0: filter@0 {
|
||||
compatible = "st,stm32-dfsdm-adc";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <0>;
|
||||
interrupts = <110>;
|
||||
st,adc-channels = <0>;
|
||||
st,adc-channel-names = "sd_adc0";
|
||||
st,adc-channel-types = "SPI_F";
|
||||
st,adc-channel-clk-src = "CLKOUT";
|
||||
io-channels = <&ads1202 0>;
|
||||
st,filter-order = <3>;
|
||||
};
|
||||
dfsdm_pdm1: filter@1 {
|
||||
compatible = "st,stm32-dfsdm-dmic";
|
||||
reg = <1>;
|
||||
interrupts = <111>;
|
||||
dmas = <&dmamux1 102 0x400 0x00>;
|
||||
dma-names = "rx";
|
||||
st,adc-channels = <1>;
|
||||
st,adc-channel-names = "dmic1";
|
||||
st,adc-channel-types = "SPI_R";
|
||||
st,adc-channel-clk-src = "CLKOUT";
|
||||
st,filter-order = <5>;
|
||||
};
|
||||
}
|
@ -1,9 +1,11 @@
|
||||
Maxim MAX30102 heart rate and pulse oximeter sensor
|
||||
Maxim MAX30105 optical particle-sensing module
|
||||
|
||||
* https://datasheets.maximintegrated.com/en/ds/MAX30102.pdf
|
||||
* https://datasheets.maximintegrated.com/en/ds/MAX30105.pdf
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "maxim,max30102"
|
||||
- compatible: must be "maxim,max30102" or "maxim,max30105"
|
||||
- reg: the I2C address of the sensor
|
||||
- interrupt-parent: should be the phandle for the interrupt controller
|
||||
- interrupts: the sole interrupt generated by the device
|
||||
@ -12,8 +14,10 @@ Required properties:
|
||||
interrupt client node bindings.
|
||||
|
||||
Optional properties:
|
||||
- maxim,red-led-current-microamp: configuration for RED LED current
|
||||
- maxim,red-led-current-microamp: configuration for red LED current
|
||||
- maxim,ir-led-current-microamp: configuration for IR LED current
|
||||
- maxim,green-led-current-microamp: configuration for green LED current
|
||||
(max30105 only)
|
||||
|
||||
Note that each step is approximately 200 microamps, ranging from 0 uA to
|
||||
50800 uA.
|
||||
|
23
Bindings/iio/light/uvis25.txt
Normal file
23
Bindings/iio/light/uvis25.txt
Normal file
@ -0,0 +1,23 @@
|
||||
* ST UVIS25 uv sensor
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "st,uvis25"
|
||||
- reg: i2c address of the sensor / spi cs line
|
||||
|
||||
Optional properties:
|
||||
- interrupt-parent: should be the phandle for the interrupt controller
|
||||
- interrupts: interrupt mapping for IRQ. It should be configured with
|
||||
flags IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or
|
||||
IRQ_TYPE_EDGE_FALLING.
|
||||
|
||||
Refer to interrupt-controller/interrupts.txt for generic interrupt
|
||||
client node bindings.
|
||||
|
||||
Example:
|
||||
|
||||
uvis25@47 {
|
||||
compatible = "st,uvis25";
|
||||
reg = <0x47>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <0 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
@ -31,7 +31,7 @@ device-specific compatible properties, which should be used in addition to the
|
||||
|
||||
- vdd-supply: phandle of the regulator that provides the supply voltage.
|
||||
- post-power-on-delay-ms: time required by the device after enabling its regulators
|
||||
before it is ready for communication. Must be used with 'vdd-supply'.
|
||||
or powering it on, before it is ready for communication.
|
||||
|
||||
Example:
|
||||
|
||||
|
@ -45,7 +45,7 @@ Optional Properties specific to linux:
|
||||
|
||||
|
||||
Example:
|
||||
keypad@100A0000 {
|
||||
keypad@100a0000 {
|
||||
compatible = "samsung,s5pv210-keypad";
|
||||
reg = <0x100A0000 0x100>;
|
||||
interrupts = <173>;
|
||||
|
@ -66,7 +66,7 @@ Example: An example of touchscreen node
|
||||
reg = <0x180a6000 0xc30>;
|
||||
};
|
||||
|
||||
touchscreen: touchscreen@180A6000 {
|
||||
touchscreen: touchscreen@180a6000 {
|
||||
compatible = "brcm,iproc-touchscreen";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
@ -1,17 +1,23 @@
|
||||
* MELFAS MMS114 touchscreen controller
|
||||
* MELFAS MMS114/MMS152 touchscreen controller
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "melfas,mms114"
|
||||
- compatible: should be one of:
|
||||
- "melfas,mms114"
|
||||
- "melfas,mms152"
|
||||
- reg: I2C address of the chip
|
||||
- interrupts: interrupt to which the chip is connected
|
||||
- x-size: horizontal resolution of touchscreen
|
||||
- y-size: vertical resolution of touchscreen
|
||||
- touchscreen-size-x: See [1]
|
||||
- touchscreen-size-y: See [1]
|
||||
|
||||
Optional properties:
|
||||
- contact-threshold:
|
||||
- moving-threshold:
|
||||
- x-invert: invert X axis
|
||||
- y-invert: invert Y axis
|
||||
- touchscreen-fuzz-x: See [1]
|
||||
- touchscreen-fuzz-y: See [1]
|
||||
- touchscreen-fuzz-pressure: See [1]
|
||||
- touchscreen-inverted-x: See [1]
|
||||
- touchscreen-inverted-y: See [1]
|
||||
- touchscreen-swapped-x-y: See [1]
|
||||
|
||||
[1]: Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt
|
||||
|
||||
Example:
|
||||
|
||||
@ -22,12 +28,13 @@ Example:
|
||||
compatible = "melfas,mms114";
|
||||
reg = <0x48>;
|
||||
interrupts = <39 0>;
|
||||
x-size = <720>;
|
||||
y-size = <1280>;
|
||||
contact-threshold = <10>;
|
||||
moving-threshold = <10>;
|
||||
x-invert;
|
||||
y-invert;
|
||||
touchscreen-size-x = <720>;
|
||||
touchscreen-size-y = <1280>;
|
||||
touchscreen-fuzz-x = <10>;
|
||||
touchscreen-fuzz-y = <10>;
|
||||
touchscreen-fuzz-pressure = <10>;
|
||||
touchscreen-inverted-x;
|
||||
touchscreen-inverted-y;
|
||||
};
|
||||
|
||||
/* ... */
|
||||
|
@ -23,6 +23,8 @@ Optional properties:
|
||||
- touchscreen-inverted-y : See touchscreen.txt
|
||||
- touchscreen-swapped-x-y : See touchscreen.txt
|
||||
- silead,max-fingers : maximum number of fingers the touchscreen can detect
|
||||
- silead,home-button : Boolean, set to true on devices which have a
|
||||
capacitive home-button build into the touchscreen
|
||||
- vddio-supply : regulator phandle for controller VDDIO
|
||||
- avdd-supply : regulator phandle for controller AVDD
|
||||
|
||||
|
@ -12,7 +12,7 @@ Required properties:
|
||||
registers
|
||||
- interrupt-controller: Identifies the node as an interrupt controller
|
||||
- #interrupt-cells: Specifies the number of cells needed to encode an
|
||||
interrupt source. The value shall be 1
|
||||
interrupt source. The value shall be 2
|
||||
|
||||
Please refer to interrupts.txt in this directory for details of the common
|
||||
Interrupt Controllers bindings used by client devices.
|
||||
@ -32,6 +32,6 @@ local_intc: local_intc {
|
||||
compatible = "brcm,bcm2836-l1-intc";
|
||||
reg = <0x40000000 0x100>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&local_intc>;
|
||||
};
|
||||
|
30
Bindings/interrupt-controller/google,goldfish-pic.txt
Normal file
30
Bindings/interrupt-controller/google,goldfish-pic.txt
Normal file
@ -0,0 +1,30 @@
|
||||
Android Goldfish PIC
|
||||
|
||||
Android Goldfish programmable interrupt device used by Android
|
||||
emulator.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should contain "google,goldfish-pic"
|
||||
- reg : <registers mapping>
|
||||
- interrupts : <interrupt mapping>
|
||||
|
||||
Example for mips when used in cascade mode:
|
||||
|
||||
cpuintc {
|
||||
#interrupt-cells = <0x1>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
};
|
||||
|
||||
interrupt-controller@1f000000 {
|
||||
compatible = "google,goldfish-pic";
|
||||
reg = <0x1f000000 0x1000>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <0x1>;
|
||||
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <0x2>;
|
||||
};
|
@ -14,6 +14,7 @@ Required properties:
|
||||
- "renesas,irqc-r8a7794" (R-Car E2)
|
||||
- "renesas,intc-ex-r8a7795" (R-Car H3)
|
||||
- "renesas,intc-ex-r8a7796" (R-Car M3-W)
|
||||
- "renesas,intc-ex-r8a77965" (R-Car M3-N)
|
||||
- "renesas,intc-ex-r8a77970" (R-Car V3M)
|
||||
- "renesas,intc-ex-r8a77995" (R-Car D3)
|
||||
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
|
||||
|
@ -16,6 +16,9 @@ Required Properties:
|
||||
- "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU.
|
||||
- "renesas,ipmmu-r8a7794" for the R8A7794 (R-Car E2) IPMMU.
|
||||
- "renesas,ipmmu-r8a7795" for the R8A7795 (R-Car H3) IPMMU.
|
||||
- "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU.
|
||||
- "renesas,ipmmu-r8a77970" for the R8A77970 (R-Car V3M) IPMMU.
|
||||
- "renesas,ipmmu-r8a77995" for the R8A77995 (R-Car D3) IPMMU.
|
||||
- "renesas,ipmmu-vmsa" for generic R-Car Gen2 VMSA-compatible IPMMU.
|
||||
|
||||
- reg: Base address and size of the IPMMU registers.
|
||||
|
@ -56,7 +56,7 @@ Examples:
|
||||
iommus = <&sysmmu_gsc0>;
|
||||
};
|
||||
|
||||
sysmmu_gsc0: sysmmu@13E80000 {
|
||||
sysmmu_gsc0: sysmmu@13e80000 {
|
||||
compatible = "samsung,exynos-sysmmu";
|
||||
reg = <0x13E80000 0x1000>;
|
||||
interrupt-parent = <&combiner>;
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user