Merge commit 468a0cb5f from llvm git (by Craig Topper):
[X86] Add X87 FCMOV support to X86FlagsCopyLowering. Fixes PR44396 Merge commit 86f48999f from llvm git (by Craig Topper): [X86] Fix typo in getCMovOpcode. The 64-bit HasMemoryOperand line was using CMOV32rm instead of CMOV64rm. Not sure how to test this. We have no test coverage that passes true for HasMemoryOperand. This fixes 'Assertion failed: (MI.findRegisterDefOperand(X86::EFLAGS) && "Expected a def of EFLAGS for this instruction!"), function runOnMachineFunction' when compiling the misc/gpsim port for i386. Reported by: yuri Upstream PR: https://bugs.llvm.org/show_bug.cgi?id=44396 MFC after: 1 week
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=356256
@ -115,6 +115,10 @@ class X86FlagsCopyLoweringPass : public MachineFunctionPass {
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MachineBasicBlock::iterator TestPos, DebugLoc TestLoc,
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MachineInstr &CMovI, MachineOperand &FlagUse,
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CondRegArray &CondRegs);
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void rewriteFCMov(MachineBasicBlock &TestMBB,
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MachineBasicBlock::iterator TestPos, DebugLoc TestLoc,
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MachineInstr &CMovI, MachineOperand &FlagUse,
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CondRegArray &CondRegs);
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void rewriteCondJmp(MachineBasicBlock &TestMBB,
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MachineBasicBlock::iterator TestPos, DebugLoc TestLoc,
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MachineInstr &JmpI, CondRegArray &CondRegs);
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@ -334,6 +338,28 @@ static MachineBasicBlock &splitBlock(MachineBasicBlock &MBB,
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return NewMBB;
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}
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static X86::CondCode getCondFromFCMOV(unsigned Opcode) {
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switch (Opcode) {
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default: return X86::COND_INVALID;
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case X86::CMOVBE_Fp32: case X86::CMOVBE_Fp64: case X86::CMOVBE_Fp80:
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return X86::COND_BE;
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case X86::CMOVB_Fp32: case X86::CMOVB_Fp64: case X86::CMOVB_Fp80:
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return X86::COND_B;
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case X86::CMOVE_Fp32: case X86::CMOVE_Fp64: case X86::CMOVE_Fp80:
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return X86::COND_E;
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case X86::CMOVNBE_Fp32: case X86::CMOVNBE_Fp64: case X86::CMOVNBE_Fp80:
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return X86::COND_A;
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case X86::CMOVNB_Fp32: case X86::CMOVNB_Fp64: case X86::CMOVNB_Fp80:
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return X86::COND_AE;
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case X86::CMOVNE_Fp32: case X86::CMOVNE_Fp64: case X86::CMOVNE_Fp80:
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return X86::COND_NE;
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case X86::CMOVNP_Fp32: case X86::CMOVNP_Fp64: case X86::CMOVNP_Fp80:
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return X86::COND_NP;
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case X86::CMOVP_Fp32: case X86::CMOVP_Fp64: case X86::CMOVP_Fp80:
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return X86::COND_P;
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}
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}
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bool X86FlagsCopyLoweringPass::runOnMachineFunction(MachineFunction &MF) {
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LLVM_DEBUG(dbgs() << "********** " << getPassName() << " : " << MF.getName()
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<< " **********\n");
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@ -593,6 +619,8 @@ bool X86FlagsCopyLoweringPass::runOnMachineFunction(MachineFunction &MF) {
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// Otherwise we can just rewrite in-place.
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if (X86::getCondFromCMov(MI) != X86::COND_INVALID) {
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rewriteCMov(*TestMBB, TestPos, TestLoc, MI, *FlagUse, CondRegs);
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} else if (getCondFromFCMOV(MI.getOpcode()) != X86::COND_INVALID) {
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rewriteFCMov(*TestMBB, TestPos, TestLoc, MI, *FlagUse, CondRegs);
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} else if (X86::getCondFromSETCC(MI) != X86::COND_INVALID) {
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rewriteSetCC(*TestMBB, TestPos, TestLoc, MI, *FlagUse, CondRegs);
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} else if (MI.getOpcode() == TargetOpcode::COPY) {
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@ -851,6 +879,51 @@ void X86FlagsCopyLoweringPass::rewriteCMov(MachineBasicBlock &TestMBB,
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LLVM_DEBUG(dbgs() << " fixed cmov: "; CMovI.dump());
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}
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void X86FlagsCopyLoweringPass::rewriteFCMov(MachineBasicBlock &TestMBB,
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MachineBasicBlock::iterator TestPos,
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DebugLoc TestLoc,
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MachineInstr &CMovI,
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MachineOperand &FlagUse,
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CondRegArray &CondRegs) {
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// First get the register containing this specific condition.
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X86::CondCode Cond = getCondFromFCMOV(CMovI.getOpcode());
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unsigned CondReg;
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bool Inverted;
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std::tie(CondReg, Inverted) =
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getCondOrInverseInReg(TestMBB, TestPos, TestLoc, Cond, CondRegs);
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MachineBasicBlock &MBB = *CMovI.getParent();
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// Insert a direct test of the saved register.
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insertTest(MBB, CMovI.getIterator(), CMovI.getDebugLoc(), CondReg);
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auto getFCMOVOpcode = [](unsigned Opcode, bool Inverted) {
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switch (Opcode) {
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default: llvm_unreachable("Unexpected opcode!");
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case X86::CMOVBE_Fp32: case X86::CMOVNBE_Fp32:
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case X86::CMOVB_Fp32: case X86::CMOVNB_Fp32:
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case X86::CMOVE_Fp32: case X86::CMOVNE_Fp32:
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case X86::CMOVP_Fp32: case X86::CMOVNP_Fp32:
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return Inverted ? X86::CMOVE_Fp32 : X86::CMOVNE_Fp32;
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case X86::CMOVBE_Fp64: case X86::CMOVNBE_Fp64:
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case X86::CMOVB_Fp64: case X86::CMOVNB_Fp64:
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case X86::CMOVE_Fp64: case X86::CMOVNE_Fp64:
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case X86::CMOVP_Fp64: case X86::CMOVNP_Fp64:
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return Inverted ? X86::CMOVE_Fp64 : X86::CMOVNE_Fp64;
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case X86::CMOVBE_Fp80: case X86::CMOVNBE_Fp80:
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case X86::CMOVB_Fp80: case X86::CMOVNB_Fp80:
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case X86::CMOVE_Fp80: case X86::CMOVNE_Fp80:
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case X86::CMOVP_Fp80: case X86::CMOVNP_Fp80:
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return Inverted ? X86::CMOVE_Fp80 : X86::CMOVNE_Fp80;
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}
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};
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// Rewrite the CMov to use the !ZF flag from the test.
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CMovI.setDesc(TII->get(getFCMOVOpcode(CMovI.getOpcode(), Inverted)));
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FlagUse.setIsKill(true);
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LLVM_DEBUG(dbgs() << " fixed fcmov: "; CMovI.dump());
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}
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void X86FlagsCopyLoweringPass::rewriteCondJmp(
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MachineBasicBlock &TestMBB, MachineBasicBlock::iterator TestPos,
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DebugLoc TestLoc, MachineInstr &JmpI, CondRegArray &CondRegs) {
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@ -2198,7 +2198,7 @@ unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) {
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default: llvm_unreachable("Illegal register size!");
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case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr;
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case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr;
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case 8: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV64rr;
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case 8: return HasMemoryOperand ? X86::CMOV64rm : X86::CMOV64rr;
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}
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}
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