Add support for radeon RS880 IGP chips to drm.
Approved by: re (kib) MFC after: 0 days
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fb6891522e
commit
2aadd82afe
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=196142
@ -330,6 +330,11 @@
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{0x1002, 0x9614, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP, "ATI Radeon 3300 Graphics"}, \
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{0x1002, 0x9615, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP, "ATI Radeon 3200 Graphics"}, \
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{0x1002, 0x9616, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP, "ATI Radeon 3000 Graphics"}, \
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{0x1002, 0x9710, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP, "ATI Radeon HD 4200"}, \
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{0x1002, 0x9711, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP, "ATI Radeon 4100"}, \
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{0x1002, 0x9712, CHIP_RS880|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP, "ATI Mobility Radeon HD 4200"}, \
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{0x1002, 0x9713, CHIP_RS880|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP, "ATI Mobility Radeon 4100"}, \
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{0x1002, 0x9714, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP, "ATI RS880"}, \
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{0x1002, 0x9440, CHIP_RV770|RADEON_NEW_MEMMAP, "ATI Radeon 4800 Series"}, \
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{0x1002, 0x9441, CHIP_RV770|RADEON_NEW_MEMMAP, "ATI Radeon 4870 X2"}, \
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{0x1002, 0x9442, CHIP_RV770|RADEON_NEW_MEMMAP, "ATI Radeon 4800 Series"}, \
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@ -318,7 +318,8 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
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pfp = RV670_pfp_microcode;
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break;
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case CHIP_RS780:
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DRM_INFO("Loading RS780 Microcode\n");
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case CHIP_RS880:
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DRM_INFO("Loading RS780/RS880 Microcode\n");
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cp = RS780_cp_microcode;
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pfp = RS780_pfp_microcode;
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break;
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@ -722,6 +723,7 @@ static void r600_gfx_init(struct drm_device *dev,
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break;
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case CHIP_RV610:
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case CHIP_RS780:
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case CHIP_RS880:
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case CHIP_RV620:
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dev_priv->r600_max_pipes = 1;
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dev_priv->r600_max_tile_pipes = 1;
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@ -856,7 +858,8 @@ static void r600_gfx_init(struct drm_device *dev,
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780))
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
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RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
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else
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RADEON_WRITE(R600_DB_DEBUG, 0);
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@ -874,7 +877,8 @@ static void r600_gfx_init(struct drm_device *dev,
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sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
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if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
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sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
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R600_FETCH_FIFO_HIWATER(0xa) |
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R600_DONE_FIFO_HIWATER(0xe0) |
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@ -917,7 +921,8 @@ static void r600_gfx_init(struct drm_device *dev,
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R600_NUM_ES_STACK_ENTRIES(0));
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} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
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/* no vertex cache */
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sq_config &= ~R600_VC_ENABLE;
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@ -974,7 +979,8 @@ static void r600_gfx_init(struct drm_device *dev,
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if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780))
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
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RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
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else
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RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
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@ -1017,6 +1023,7 @@ static void r600_gfx_init(struct drm_device *dev,
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break;
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case CHIP_RV610:
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case CHIP_RS780:
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case CHIP_RS880:
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case CHIP_RV620:
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gs_prim_buffer_depth = 32;
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break;
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@ -1062,6 +1069,7 @@ static void r600_gfx_init(struct drm_device *dev,
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switch (dev_priv->flags & RADEON_FAMILY_MASK) {
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case CHIP_RV610:
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case CHIP_RS780:
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case CHIP_RS880:
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case CHIP_RV620:
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tc_cntl = R600_TC_L2_SIZE(8);
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break;
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@ -145,6 +145,7 @@ enum radeon_family {
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CHIP_RV635,
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CHIP_RV670,
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CHIP_RS780,
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CHIP_RS880,
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CHIP_RV770,
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CHIP_RV740,
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CHIP_RV730,
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