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a10_ahci: Correct clock indices for new bindings

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r329104 imported 4.15 DTS which brought CCU to a10/a20. In the process, they
swapped the ordering of 'clocks' for allwinner,sun4i-a10-ahci on both
sun4i-a10 and sun7i-a20 from PLL, Gate to Gate, PLL.

Swap it in the driver.
This commit is contained in:
Kyle Evans 2018-06-14 18:34:02 +00:00
parent dcc1299f0b
commit 2ac5ef02d4
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=335168
1 changed files with 6 additions and 6 deletions
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12
sys/arm/allwinner/a10_ahci.c
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@ -313,16 +313,16 @@ ahci_a10_attach(device_t dev)
return (ENXIO);
/* Enable clocks */
error = clk_get_by_ofw_index(dev, 0, 0, &clk_pll);
if (error != 0) {
device_printf(dev, "Cannot get PLL clock\n");
goto fail;
}
error = clk_get_by_ofw_index(dev, 0, 1, &clk_gate);
error = clk_get_by_ofw_index(dev, 0, 0, &clk_gate);
if (error != 0) {
device_printf(dev, "Cannot get gate clock\n");
goto fail;
}
error = clk_get_by_ofw_index(dev, 0, 1, &clk_pll);
if (error != 0) {
device_printf(dev, "Cannot get PLL clock\n");
goto fail;
}
error = clk_set_freq(clk_pll, PLL_FREQ, CLK_SET_ROUND_DOWN);
if (error != 0) {
device_printf(dev, "Cannot set PLL frequency\n");