Go back to filtering all PHY addresses above 16 since at least two
cards still have issues with them. Maybe this is a silicon rev? In any case, doing the filtering only for the AX88790 for the moment.
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=190586
@ -1101,8 +1101,14 @@ ed_miibus_readreg(device_t dev, int phy, int reg)
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* the internal PHY, a bit has to be set, when accessing the external
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* PHYs, it must be clear. See Errata 1, page 51, in the AX88790
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* datasheet for more details.
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*
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* Also, PHYs above 16 appear to be phantoms on some cards, but not
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* others. Registers read for this are often the same as prior values
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* read. Filter all register requests to 17-31.
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*/
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if (sc->chip_type == ED_CHIP_TYPE_AX88790) {
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if (phy > 0x10)
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return (0);
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if (phy == 0x10)
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ed_asic_outb(sc, ED_AX88X90_GPIO,
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ED_AX88X90_GPIO_INT_PHY);
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@ -1130,15 +1136,10 @@ ed_miibus_writereg(device_t dev, int phy, int reg, int data)
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struct ed_softc *sc;
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sc = device_get_softc(dev);
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/*
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* The AX88790 has an interesting quirk. It has an internal phy that
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* needs a special bit set to access, but can also have additional
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* external PHYs set for things like HomeNET media. When accessing
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* the internal PHY, a bit has to be set, when accessing the external
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* PHYs, it must be clear. See Errata 1, page 51, in the AX88790
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* datasheet for more details.
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*/
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/* See ed_miibus_readreg for details */
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if (sc->chip_type == ED_CHIP_TYPE_AX88790) {
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if (phy > 0x10)
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return (0);
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if (phy == 0x10)
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ed_asic_outb(sc, ED_AX88X90_GPIO,
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ED_AX88X90_GPIO_INT_PHY);
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