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Commit FIFO configuration fixes from OpenWRT. This fixes performance

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issues with if_arge on the AR913x and AR724x.

Reference: https://dev.openwrt.org/ticket/6754
Submitted by: Luiz Otavio O Souza
This commit is contained in:
Adrian Chadd 2011-03-13 08:28:21 +00:00
parent fce6d67665
commit 2b60eabf75
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=219589
1 changed files with 28 additions and 4 deletions
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32
sys/mips/atheros/if_arge.c
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@ -79,6 +79,7 @@ MODULE_DEPEND(arge, miibus, 1, 1, 1);
#include <mips/atheros/ar71xxreg.h>
#include <mips/atheros/if_argevar.h>
#include <mips/atheros/ar71xx_setup.h>
#include <mips/atheros/ar71xx_cpudef.h>
#undef ARGE_DEBUG
@ -400,8 +401,18 @@ arge_attach(device_t dev)
ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0,
FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT);
ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0fff0000);
ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x00001fff);
switch (ar71xx_soc) {
case AR71XX_SOC_AR7240:
case AR71XX_SOC_AR7241:
case AR71XX_SOC_AR7242:
ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0010ffff);
ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x015500aa);
break;
default:
ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0fff0000);
ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x00001fff);
}
ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMATCH,
FIFO_RX_FILTMATCH_DEFAULT);
@ -663,6 +674,7 @@ static void
arge_set_pll(struct arge_softc *sc, int media, int duplex)
{
uint32_t cfg, ifcontrol, rx_filtmask;
uint32_t fifo_tx;
int if_speed;
cfg = ARGE_READ(sc, AR71XX_MAC_CFG2);
@ -701,13 +713,25 @@ arge_set_pll(struct arge_softc *sc, int media, int duplex)
"Unknown media %d\n", media);
}
ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD,
0x008001ff);
switch (ar71xx_soc) {
case AR71XX_SOC_AR7240:
case AR71XX_SOC_AR7241:
case AR71XX_SOC_AR7242:
fifo_tx = 0x01f00140;
break;
case AR71XX_SOC_AR9130:
case AR71XX_SOC_AR9132:
fifo_tx = 0x00780fff;
break;
default:
fifo_tx = 0x008001ff;
}
ARGE_WRITE(sc, AR71XX_MAC_CFG2, cfg);
ARGE_WRITE(sc, AR71XX_MAC_IFCONTROL, ifcontrol);
ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
rx_filtmask);
ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD, fifo_tx);
/* set PLL registers */
if (sc->arge_mac_unit == 0)