Updates for the Mellanox ethernet driver

> List of fixes:
  * use correct format for GID printouts
  * double array indexing
  * spelling in printouts
  * void pointer arithmetic
  * allow more receive rings
  * correct maximum number of transmit rings
  * use "const" instead of "static" for constants
  * check for invalid VLAN tags
  * check for lack of IRQ resources
> Added more hardware specific defines
> Added more verbose printouts of firmware status codes

Sponsored by:	Mellanox Technologies
MFC after:	3 days
This commit is contained in:
Hans Petter Selasky 2015-03-04 09:30:03 +00:00
parent 75d07abd2d
commit 2b8859521d
Notes: svn2git 2020-12-20 02:59:44 +00:00
svn path=/head/; revision=279584
10 changed files with 74 additions and 30 deletions

View File

@ -757,6 +757,19 @@ static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
"in_mod=0x%x, op_mod=0x%x, fw status = 0x%x\n",
cmd_to_str(op), op, (unsigned long long) in_param, in_modifier,
op_modifier, context->fw_status);
switch(context->fw_status) {
case CMD_STAT_BAD_PARAM:
mlx4_err(dev, "Parameter is not supported, "
"parameter is out of range\n");
break;
case CMD_STAT_EXCEED_LIM:
mlx4_err(dev, "Required capability exceeded "
"device limits\n");
break;
default:
break;
}
goto out;
}

View File

@ -241,8 +241,8 @@ static void *mlx4_en_add(struct mlx4_dev *dev)
DEF_RX_RINGS)));
} else {
mdev->profile.prof[i].rx_ring_num = rounddown_pow_of_two(
min_t(int, dev->caps.comp_pool/
dev->caps.num_ports - 1 , MAX_MSIX_P_PORT - 1));
min_t(int, dev->caps.comp_pool /
dev->caps.num_ports, MAX_MSIX_P_PORT));
}
}

View File

@ -1305,7 +1305,7 @@ int mlx4_en_start_port(struct net_device *dev)
cq = priv->tx_cq[i];
err = mlx4_en_activate_cq(priv, cq, i);
if (err) {
en_err(priv, "Failed allocating Tx CQ\n");
en_err(priv, "Failed activating Tx CQ\n");
goto tx_err;
}
err = mlx4_en_set_cq_moder(priv, cq);
@ -1323,7 +1323,7 @@ int mlx4_en_start_port(struct net_device *dev)
err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn,
i / priv->num_tx_rings_p_up);
if (err) {
en_err(priv, "Failed allocating Tx ring\n");
en_err(priv, "Failed activating Tx ring %d\n", i);
mlx4_en_deactivate_cq(priv, cq);
goto tx_err;
}
@ -2189,6 +2189,7 @@ int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
mlx4_en_destroy_netdev(dev);
return err;
}
static int mlx4_en_set_ring_size(struct net_device *dev,
int rx_size, int tx_size)
{
@ -2409,7 +2410,6 @@ static void mlx4_en_sysctl_conf(struct mlx4_en_priv *priv)
"Enable adaptive rx coalescing");
}
static void mlx4_en_sysctl_stat(struct mlx4_en_priv *priv)
{
struct net_device *dev;

View File

@ -500,7 +500,7 @@ static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
goto fail;
/* Unmap buffer */
pci_unmap_single(mdev->pdev, dma, frag_info[nr].frag_size,
pci_unmap_single(mdev->pdev, dma, frag_info->frag_size,
PCI_DMA_FROMDEVICE);
}
/* Adjust size of last fragment to match actual length */

View File

@ -710,16 +710,16 @@ u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb)
{
struct mlx4_en_priv *priv = netdev_priv(dev);
u32 rings_p_up = priv->num_tx_rings_p_up;
u32 vlan_tag = 0;
u32 up = 0;
u32 queue_index;
#if (MLX4_EN_NUM_UP > 1)
/* Obtain VLAN information if present */
if (mb->m_flags & M_VLANTAG) {
vlan_tag = mb->m_pkthdr.ether_vtag;
up = (vlan_tag >> 13);
u32 vlan_tag = mb->m_pkthdr.ether_vtag;
up = (vlan_tag >> 13) % MLX4_EN_NUM_UP;
}
#endif
/* check if flowid is set */
if (M_HASHTYPE_GET(mb) != M_HASHTYPE_NONE)
queue_index = mb->m_pkthdr.flowid;

View File

@ -1303,8 +1303,9 @@ static ssize_t show_port_ib_mtu(struct device *dev,
port_mtu_attr);
struct mlx4_dev *mdev = info->dev;
/* When port type is eth, port mtu value isn't used. */
if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
return -EINVAL;
sprintf(buf, "%d\n",
ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
@ -2899,6 +2900,12 @@ static void mlx4_enable_msi_x(struct mlx4_dev *dev)
goto retry;
}
kfree(entries);
/* if error, or can't alloc even 1 IRQ */
if (err < 0) {
mlx4_err(dev, "No IRQs left, device can't "
"be started.\n");
goto no_irq;
}
goto no_msi;
}
@ -2926,6 +2933,10 @@ static void mlx4_enable_msi_x(struct mlx4_dev *dev)
for (i = 0; i < 2; ++i)
priv->eq_table.eq[i].irq = dev->pdev->irq;
return;
no_irq:
dev->caps.num_comp_vectors = 0;
dev->caps.comp_pool = 0;
}
static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
@ -3301,6 +3312,13 @@ static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
mutex_init(&priv->msix_ctl.pool_lock);
mlx4_enable_msi_x(dev);
/* no MSIX and no shared IRQ */
if (!dev->caps.num_comp_vectors && !dev->caps.comp_pool) {
err = -ENOSPC;
goto err_free_eq;
}
if ((mlx4_is_mfunc(dev)) &&
!(dev->flags & MLX4_FLAG_MSI_X)) {
err = -ENOSYS;

View File

@ -36,6 +36,7 @@
#include <linux/mlx4/cmd.h>
#include <linux/module.h>
#include <linux/printk.h>
#include "mlx4.h"
@ -690,8 +691,10 @@ static int find_entry(struct mlx4_dev *dev, u8 port,
if (err)
return err;
if (0)
mlx4_dbg(dev, "Hash for %pI6 is %04x\n", gid, hash);
if (0) {
mlx4_dbg(dev, "Hash for "GID_PRINT_FMT" is %04x\n",
GID_PRINT_ARGS(gid), hash);
}
*index = hash;
*prev = -1;
@ -912,10 +915,11 @@ static void mlx4_err_rule(struct mlx4_dev *dev, char *str,
case MLX4_NET_TRANS_RULE_ID_IB:
len += snprintf(buf + len, BUF_SIZE - len,
"dst-gid = %pI6\n", cur->ib.dst_gid);
"dst-gid = "GID_PRINT_FMT"\n",
GID_PRINT_ARGS(cur->ib.dst_gid));
len += snprintf(buf + len, BUF_SIZE - len,
"dst-gid-mask = %pI6\n",
cur->ib.dst_gid_msk);
"dst-gid-mask = "GID_PRINT_FMT"\n",
GID_PRINT_ARGS(cur->ib.dst_gid_msk));
break;
case MLX4_NET_TRANS_RULE_ID_IPV6:
@ -1135,7 +1139,8 @@ int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
goto out;
if (index == -1) {
mlx4_err(dev, "MGID %pI6 not found\n", gid);
mlx4_err(dev, "MGID "GID_PRINT_FMT" not found\n",
GID_PRINT_ARGS(gid));
err = -EINVAL;
goto out;
}

View File

@ -154,7 +154,7 @@ enum {
#define MLX4_EN_NUM_UP 1
#define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
(MLX4_EN_NUM_UP + 1))
MLX4_EN_NUM_UP)
#define MLX4_EN_DEF_TX_RING_SIZE 1024
#define MLX4_EN_DEF_RX_RING_SIZE 1024
@ -358,11 +358,7 @@ struct mlx4_en_rx_ring {
static inline int mlx4_en_can_lro(__be16 status)
{
static __be16 status_all;
static __be16 status_ipv4_ipok_tcp;
static __be16 status_ipv6_ipok_tcp;
status_all = cpu_to_be16(
const __be16 status_all = cpu_to_be16(
MLX4_CQE_STATUS_IPV4 |
MLX4_CQE_STATUS_IPV4F |
MLX4_CQE_STATUS_IPV6 |
@ -370,11 +366,11 @@ static inline int mlx4_en_can_lro(__be16 status)
MLX4_CQE_STATUS_TCP |
MLX4_CQE_STATUS_UDP |
MLX4_CQE_STATUS_IPOK);
status_ipv4_ipok_tcp = cpu_to_be16(
const __be16 status_ipv4_ipok_tcp = cpu_to_be16(
MLX4_CQE_STATUS_IPV4 |
MLX4_CQE_STATUS_IPOK |
MLX4_CQE_STATUS_TCP);
status_ipv6_ipok_tcp = cpu_to_be16(
const __be16 status_ipv6_ipok_tcp = cpu_to_be16(
MLX4_CQE_STATUS_IPV6 |
MLX4_CQE_STATUS_IPOK |
MLX4_CQE_STATUS_TCP);
@ -384,7 +380,6 @@ static inline int mlx4_en_can_lro(__be16 status)
status == status_ipv6_ipok_tcp);
}
struct mlx4_en_cq {
struct mlx4_cq mcq;
struct mlx4_hwq_resources wqres;

View File

@ -186,8 +186,19 @@ enum {
MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 10,
MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 11,
MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 12,
MLX4_DEV_CAP_FLAG2_TS = 1LL << 13,
MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW = 1LL << 14
MLX4_DEV_CAP_FLAG2_TS = 1LL << 13,
MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW = 1LL << 14,
MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 15,
MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 16,
MLX4_DEV_CAP_FLAG2_FS_EN_NCSI = 1LL << 17,
MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
MLX4_DEV_CAP_FLAG2_DMFS_TAG_MODE = 1LL << 19,
MLX4_DEV_CAP_FLAG2_ROCEV2 = 1LL << 20,
MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 21,
MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 22,
MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 23,
MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1LL << 24,
MLX4_DEV_CAP_FLAG2_RX_CSUM_MODE = 1LL << 25,
};
/* bit enums for an 8-bit flags field indicating special use
@ -948,9 +959,9 @@ void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
{
if (BITS_PER_LONG == 64 || buf->nbufs == 1)
return buf->direct.buf + offset;
return (u8 *)buf->direct.buf + offset;
else
return buf->page_list[offset >> PAGE_SHIFT].buf +
return (u8 *)buf->page_list[offset >> PAGE_SHIFT].buf +
(offset & (PAGE_SIZE - 1));
}

View File

@ -253,6 +253,8 @@ enum {
MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE = 14 + 32,
MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX = 15 + 32,
MLX4_UPD_QP_PATH_MASK_FVL_RX = 16 + 32,
MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_UC_LB = 18 + 32,
MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB = 19 + 32,
};
enum { /* param3 */