Regen assembly files for arm.
This commit is contained in:
parent
4b7c498f1f
commit
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/projects/openssl111/; revision=338877
@ -149,22 +149,34 @@ ${s}.S: ${s}.s
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.PATH: ${LCRYPTO_SRC}/crypto \
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.PATH: ${LCRYPTO_SRC}/crypto \
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${LCRYPTO_SRC}/crypto/aes/asm \
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${LCRYPTO_SRC}/crypto/aes/asm \
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${LCRYPTO_SRC}/crypto/bn/asm \
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${LCRYPTO_SRC}/crypto/bn/asm \
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${LCRYPTO_SRC}/crypto/chacha/asm \
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${LCRYPTO_SRC}/crypto/ec/asm \
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${LCRYPTO_SRC}/crypto/modes/asm \
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${LCRYPTO_SRC}/crypto/modes/asm \
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${LCRYPTO_SRC}/crypto/poly1305/asm \
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${LCRYPTO_SRC}/crypto/sha/asm
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${LCRYPTO_SRC}/crypto/sha/asm
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PERLPATH= -I${LCRYPTO_SRC}/crypto/perlasm
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PERLPATH= -I${LCRYPTO_SRC}/crypto/perlasm
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# aes
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# aes
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SRCS= aesv8-armx.pl bsaes-armv7.pl
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SRCS= aes-armv4.pl aesv8-armx.pl bsaes-armv7.pl
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# bn
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# bn
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SRCS+= armv4-mont.pl armv4-gf2m.pl
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SRCS+= armv4-mont.pl armv4-gf2m.pl
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# chacha
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SRCS+= chacha-armv4.pl
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# ec
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SRCS+= ecp_nistz256-armv4.pl
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# modes
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# modes
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SRCS+= ghash-armv4.pl ghashv8-armx.pl
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SRCS+= ghash-armv4.pl ghashv8-armx.pl
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# poly1305
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SRCS+= poly1305-armv4.pl
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# sha
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# sha
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SRCS+= sha1-armv4-large.pl sha256-armv4.pl sha512-armv4.pl
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SRCS+= keccak1600-armv4.pl sha1-armv4-large.pl sha256-armv4.pl sha512-armv4.pl
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ASM= aes-armv4.S ${SRCS:R:S/$/.S/}
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ASM= aes-armv4.S ${SRCS:R:S/$/.S/}
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@ -1,5 +1,12 @@
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/* $FreeBSD$ */
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/* $FreeBSD$ */
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/* Do not modify. This file is auto-generated from aes-armv4.pl. */
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/* Do not modify. This file is auto-generated from aes-armv4.pl. */
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@ Copyright 2007-2018 The OpenSSL Project Authors. All Rights Reserved.
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@
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@ Licensed under the OpenSSL license (the "License"). You may not use
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@ this file except in compliance with the License. You can obtain a copy
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@ in the file LICENSE in the source distribution or at
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@ https://www.openssl.org/source/license.html
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@ ====================================================================
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@ ====================================================================
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@ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
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@ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
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@ -40,15 +47,12 @@
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#endif
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#endif
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.text
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.text
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#if __ARM_ARCH__<7
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#if defined(__thumb2__) && !defined(__APPLE__)
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.code 32
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#else
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.syntax unified
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.syntax unified
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# ifdef __thumb2__
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.thumb
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.thumb
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#else
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#else
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.code 32
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.code 32
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# endif
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#undef __thumb2__
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#endif
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#endif
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.type AES_Te,%object
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.type AES_Te,%object
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@ -159,19 +163,23 @@ AES_Te:
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@ void AES_encrypt(const unsigned char *in, unsigned char *out,
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@ void AES_encrypt(const unsigned char *in, unsigned char *out,
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@ const AES_KEY *key) {
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@ const AES_KEY *key) {
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.global AES_encrypt
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.globl AES_encrypt
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.type AES_encrypt,%function
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.type AES_encrypt,%function
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.align 5
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.align 5
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AES_encrypt:
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AES_encrypt:
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#if __ARM_ARCH__<7
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#ifndef __thumb2__
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sub r3,pc,#8 @ AES_encrypt
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sub r3,pc,#8 @ AES_encrypt
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#else
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#else
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adr r3,.
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adr r3,.
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#endif
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#endif
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stmdb sp!,{r1,r4-r12,lr}
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stmdb sp!,{r1,r4-r12,lr}
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#if defined(__thumb2__) || defined(__APPLE__)
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adr r10,AES_Te
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#else
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sub r10,r3,#AES_encrypt-AES_Te @ Te
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#endif
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mov r12,r0 @ inp
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mov r12,r0 @ inp
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mov r11,r2
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mov r11,r2
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sub r10,r3,#AES_encrypt-AES_Te @ Te
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#if __ARM_ARCH__<7
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#if __ARM_ARCH__<7
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ldrb r0,[r12,#3] @ load input data in endian-neutral
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ldrb r0,[r12,#3] @ load input data in endian-neutral
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ldrb r4,[r12,#2] @ manner...
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ldrb r4,[r12,#2] @ manner...
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@ -258,9 +266,9 @@ AES_encrypt:
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strb r3,[r12,#15]
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strb r3,[r12,#15]
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#endif
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#endif
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#if __ARM_ARCH__>=5
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#if __ARM_ARCH__>=5
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ldmia sp!,{r4-r12,pc}
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ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,pc}
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#else
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#else
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ldmia sp!,{r4-r12,lr}
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ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
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tst lr,#1
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tst lr,#1
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moveq pc,lr @ be binary compatible with V4, yet
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moveq pc,lr @ be binary compatible with V4, yet
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.word 0xe12fff1e @ interoperable with Thumb ISA:-)
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.word 0xe12fff1e @ interoperable with Thumb ISA:-)
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@ -271,7 +279,7 @@ AES_encrypt:
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.align 2
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.align 2
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_armv4_AES_encrypt:
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_armv4_AES_encrypt:
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str lr,[sp,#-4]! @ push lr
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str lr,[sp,#-4]! @ push lr
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ldmia r11!,{r4-r7}
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ldmia r11!,{r4,r5,r6,r7}
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eor r0,r0,r4
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eor r0,r0,r4
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ldr r12,[r11,#240-16]
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ldr r12,[r11,#240-16]
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eor r1,r1,r5
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eor r1,r1,r5
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@ -404,24 +412,24 @@ _armv4_AES_encrypt:
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ldr pc,[sp],#4 @ pop and return
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ldr pc,[sp],#4 @ pop and return
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.size _armv4_AES_encrypt,.-_armv4_AES_encrypt
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.size _armv4_AES_encrypt,.-_armv4_AES_encrypt
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.global private_AES_set_encrypt_key
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.globl AES_set_encrypt_key
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.type private_AES_set_encrypt_key,%function
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.type AES_set_encrypt_key,%function
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.align 5
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.align 5
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private_AES_set_encrypt_key:
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AES_set_encrypt_key:
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_armv4_AES_set_encrypt_key:
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_armv4_AES_set_encrypt_key:
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#if __ARM_ARCH__<7
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#ifndef __thumb2__
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sub r3,pc,#8 @ AES_set_encrypt_key
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sub r3,pc,#8 @ AES_set_encrypt_key
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#else
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#else
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adr r3,.
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adr r3,.
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#endif
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#endif
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teq r0,#0
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teq r0,#0
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#if __ARM_ARCH__>=7
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#ifdef __thumb2__
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itt eq @ Thumb2 thing, sanity check in ARM
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itt eq @ Thumb2 thing, sanity check in ARM
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#endif
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#endif
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moveq r0,#-1
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moveq r0,#-1
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beq .Labrt
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beq .Labrt
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teq r2,#0
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teq r2,#0
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#if __ARM_ARCH__>=7
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#ifdef __thumb2__
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itt eq @ Thumb2 thing, sanity check in ARM
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itt eq @ Thumb2 thing, sanity check in ARM
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#endif
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#endif
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moveq r0,#-1
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moveq r0,#-1
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@ -432,19 +440,23 @@ _armv4_AES_set_encrypt_key:
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teq r1,#192
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teq r1,#192
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beq .Lok
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beq .Lok
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teq r1,#256
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teq r1,#256
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#if __ARM_ARCH__>=7
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#ifdef __thumb2__
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itt ne @ Thumb2 thing, sanity check in ARM
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itt ne @ Thumb2 thing, sanity check in ARM
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#endif
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#endif
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movne r0,#-1
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movne r0,#-1
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bne .Labrt
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bne .Labrt
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.Lok: stmdb sp!,{r4-r12,lr}
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.Lok: stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
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sub r10,r3,#_armv4_AES_set_encrypt_key-AES_Te-1024 @ Te4
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mov r12,r0 @ inp
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mov r12,r0 @ inp
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mov lr,r1 @ bits
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mov lr,r1 @ bits
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mov r11,r2 @ key
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mov r11,r2 @ key
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#if defined(__thumb2__) || defined(__APPLE__)
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adr r10,AES_Te+1024 @ Te4
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#else
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sub r10,r3,#_armv4_AES_set_encrypt_key-AES_Te-1024 @ Te4
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#endif
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#if __ARM_ARCH__<7
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#if __ARM_ARCH__<7
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ldrb r0,[r12,#3] @ load input data in endian-neutral
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ldrb r0,[r12,#3] @ load input data in endian-neutral
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ldrb r4,[r12,#2] @ manner...
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ldrb r4,[r12,#2] @ manner...
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@ -589,7 +601,7 @@ _armv4_AES_set_encrypt_key:
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str r2,[r11,#-16]
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str r2,[r11,#-16]
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subs r12,r12,#1
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subs r12,r12,#1
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str r3,[r11,#-12]
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str r3,[r11,#-12]
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#if __ARM_ARCH__>=7
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#ifdef __thumb2__
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itt eq @ Thumb2 thing, sanity check in ARM
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itt eq @ Thumb2 thing, sanity check in ARM
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#endif
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#endif
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subeq r2,r11,#216
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subeq r2,r11,#216
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@ -661,7 +673,7 @@ _armv4_AES_set_encrypt_key:
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str r2,[r11,#-24]
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str r2,[r11,#-24]
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subs r12,r12,#1
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subs r12,r12,#1
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str r3,[r11,#-20]
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str r3,[r11,#-20]
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#if __ARM_ARCH__>=7
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#ifdef __thumb2__
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itt eq @ Thumb2 thing, sanity check in ARM
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itt eq @ Thumb2 thing, sanity check in ARM
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#endif
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#endif
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subeq r2,r11,#256
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subeq r2,r11,#256
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@ -695,7 +707,7 @@ _armv4_AES_set_encrypt_key:
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.align 2
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.align 2
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.Ldone: mov r0,#0
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.Ldone: mov r0,#0
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ldmia sp!,{r4-r12,lr}
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ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
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.Labrt:
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.Labrt:
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#if __ARM_ARCH__>=5
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#if __ARM_ARCH__>=5
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bx lr @ .word 0xe12fff1e
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bx lr @ .word 0xe12fff1e
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@ -704,12 +716,12 @@ _armv4_AES_set_encrypt_key:
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moveq pc,lr @ be binary compatible with V4, yet
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moveq pc,lr @ be binary compatible with V4, yet
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.word 0xe12fff1e @ interoperable with Thumb ISA:-)
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.word 0xe12fff1e @ interoperable with Thumb ISA:-)
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#endif
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#endif
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.size private_AES_set_encrypt_key,.-private_AES_set_encrypt_key
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.size AES_set_encrypt_key,.-AES_set_encrypt_key
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.global private_AES_set_decrypt_key
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.globl AES_set_decrypt_key
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.type private_AES_set_decrypt_key,%function
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.type AES_set_decrypt_key,%function
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.align 5
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.align 5
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private_AES_set_decrypt_key:
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AES_set_decrypt_key:
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str lr,[sp,#-4]! @ push lr
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str lr,[sp,#-4]! @ push lr
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bl _armv4_AES_set_encrypt_key
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bl _armv4_AES_set_encrypt_key
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teq r0,#0
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teq r0,#0
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@ -719,20 +731,20 @@ private_AES_set_decrypt_key:
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mov r0,r2 @ AES_set_encrypt_key preserves r2,
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mov r0,r2 @ AES_set_encrypt_key preserves r2,
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mov r1,r2 @ which is AES_KEY *key
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mov r1,r2 @ which is AES_KEY *key
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b _armv4_AES_set_enc2dec_key
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b _armv4_AES_set_enc2dec_key
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.size private_AES_set_decrypt_key,.-private_AES_set_decrypt_key
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.size AES_set_decrypt_key,.-AES_set_decrypt_key
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@ void AES_set_enc2dec_key(const AES_KEY *inp,AES_KEY *out)
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@ void AES_set_enc2dec_key(const AES_KEY *inp,AES_KEY *out)
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.global AES_set_enc2dec_key
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.globl AES_set_enc2dec_key
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.type AES_set_enc2dec_key,%function
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.type AES_set_enc2dec_key,%function
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.align 5
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.align 5
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AES_set_enc2dec_key:
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AES_set_enc2dec_key:
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_armv4_AES_set_enc2dec_key:
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_armv4_AES_set_enc2dec_key:
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stmdb sp!,{r4-r12,lr}
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stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
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ldr r12,[r0,#240]
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ldr r12,[r0,#240]
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mov r7,r0 @ input
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mov r7,r0 @ input
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add r8,r0,r12,lsl#4
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add r8,r0,r12,lsl#4
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mov r11,r1 @ ouput
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mov r11,r1 @ output
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add r10,r1,r12,lsl#4
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add r10,r1,r12,lsl#4
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str r12,[r1,#240]
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str r12,[r1,#240]
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@ -809,9 +821,9 @@ _armv4_AES_set_enc2dec_key:
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mov r0,#0
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mov r0,#0
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#if __ARM_ARCH__>=5
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#if __ARM_ARCH__>=5
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ldmia sp!,{r4-r12,pc}
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ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,pc}
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#else
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#else
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ldmia sp!,{r4-r12,lr}
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ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
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tst lr,#1
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tst lr,#1
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moveq pc,lr @ be binary compatible with V4, yet
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moveq pc,lr @ be binary compatible with V4, yet
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.word 0xe12fff1e @ interoperable with Thumb ISA:-)
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.word 0xe12fff1e @ interoperable with Thumb ISA:-)
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@ -922,19 +934,23 @@ AES_Td:
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@ void AES_decrypt(const unsigned char *in, unsigned char *out,
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@ void AES_decrypt(const unsigned char *in, unsigned char *out,
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@ const AES_KEY *key) {
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@ const AES_KEY *key) {
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.global AES_decrypt
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.globl AES_decrypt
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.type AES_decrypt,%function
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.type AES_decrypt,%function
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.align 5
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.align 5
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AES_decrypt:
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AES_decrypt:
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#if __ARM_ARCH__<7
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#ifndef __thumb2__
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sub r3,pc,#8 @ AES_decrypt
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sub r3,pc,#8 @ AES_decrypt
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#else
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#else
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adr r3,.
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adr r3,.
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#endif
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#endif
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stmdb sp!,{r1,r4-r12,lr}
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stmdb sp!,{r1,r4-r12,lr}
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#if defined(__thumb2__) || defined(__APPLE__)
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adr r10,AES_Td
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#else
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sub r10,r3,#AES_decrypt-AES_Td @ Td
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#endif
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mov r12,r0 @ inp
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mov r12,r0 @ inp
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mov r11,r2
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mov r11,r2
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sub r10,r3,#AES_decrypt-AES_Td @ Td
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#if __ARM_ARCH__<7
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#if __ARM_ARCH__<7
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ldrb r0,[r12,#3] @ load input data in endian-neutral
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ldrb r0,[r12,#3] @ load input data in endian-neutral
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ldrb r4,[r12,#2] @ manner...
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ldrb r4,[r12,#2] @ manner...
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@ -1021,9 +1037,9 @@ AES_decrypt:
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strb r3,[r12,#15]
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strb r3,[r12,#15]
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#endif
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#endif
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#if __ARM_ARCH__>=5
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#if __ARM_ARCH__>=5
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ldmia sp!,{r4-r12,pc}
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ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,pc}
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#else
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#else
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ldmia sp!,{r4-r12,lr}
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ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
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tst lr,#1
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tst lr,#1
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moveq pc,lr @ be binary compatible with V4, yet
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moveq pc,lr @ be binary compatible with V4, yet
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.word 0xe12fff1e @ interoperable with Thumb ISA:-)
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.word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
||||||
@ -1034,7 +1050,7 @@ AES_decrypt:
|
|||||||
.align 2
|
.align 2
|
||||||
_armv4_AES_decrypt:
|
_armv4_AES_decrypt:
|
||||||
str lr,[sp,#-4]! @ push lr
|
str lr,[sp,#-4]! @ push lr
|
||||||
ldmia r11!,{r4-r7}
|
ldmia r11!,{r4,r5,r6,r7}
|
||||||
eor r0,r0,r4
|
eor r0,r0,r4
|
||||||
ldr r12,[r11,#240-16]
|
ldr r12,[r11,#240-16]
|
||||||
eor r1,r1,r5
|
eor r1,r1,r5
|
||||||
@ -1175,5 +1191,6 @@ _armv4_AES_decrypt:
|
|||||||
sub r10,r10,#1024
|
sub r10,r10,#1024
|
||||||
ldr pc,[sp],#4 @ pop and return
|
ldr pc,[sp],#4 @ pop and return
|
||||||
.size _armv4_AES_decrypt,.-_armv4_AES_decrypt
|
.size _armv4_AES_decrypt,.-_armv4_AES_decrypt
|
||||||
.asciz "AES for ARMv4, CRYPTOGAMS by <appro@openssl.org>"
|
.byte 65,69,83,32,102,111,114,32,65,82,77,118,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
|
||||||
|
.align 2
|
||||||
.align 2
|
.align 2
|
||||||
|
@ -4,11 +4,12 @@
|
|||||||
|
|
||||||
#if __ARM_MAX_ARCH__>=7
|
#if __ARM_MAX_ARCH__>=7
|
||||||
.text
|
.text
|
||||||
.arch armv7-a
|
.arch armv7-a @ don't confuse not-so-latest binutils with argv8 :-)
|
||||||
.fpu neon
|
.fpu neon
|
||||||
.code 32
|
.code 32
|
||||||
|
#undef __thumb2__
|
||||||
.align 5
|
.align 5
|
||||||
rcon:
|
.Lrcon:
|
||||||
.long 0x01,0x01,0x01,0x01
|
.long 0x01,0x01,0x01,0x01
|
||||||
.long 0x0c0f0e0d,0x0c0f0e0d,0x0c0f0e0d,0x0c0f0e0d @ rotate-n-splat
|
.long 0x0c0f0e0d,0x0c0f0e0d,0x0c0f0e0d,0x0c0f0e0d @ rotate-n-splat
|
||||||
.long 0x1b,0x1b,0x1b,0x1b
|
.long 0x1b,0x1b,0x1b,0x1b
|
||||||
@ -31,7 +32,7 @@ aes_v8_set_encrypt_key:
|
|||||||
tst r1,#0x3f
|
tst r1,#0x3f
|
||||||
bne .Lenc_key_abort
|
bne .Lenc_key_abort
|
||||||
|
|
||||||
adr r3,rcon
|
adr r3,.Lrcon
|
||||||
cmp r1,#192
|
cmp r1,#192
|
||||||
|
|
||||||
veor q0,q0,q0
|
veor q0,q0,q0
|
||||||
@ -283,9 +284,9 @@ aes_v8_decrypt:
|
|||||||
.align 5
|
.align 5
|
||||||
aes_v8_cbc_encrypt:
|
aes_v8_cbc_encrypt:
|
||||||
mov ip,sp
|
mov ip,sp
|
||||||
stmdb sp!,{r4-r8,lr}
|
stmdb sp!,{r4,r5,r6,r7,r8,lr}
|
||||||
vstmdb sp!,{d8-d15} @ ABI specification says so
|
vstmdb sp!,{d8,d9,d10,d11,d12,d13,d14,d15} @ ABI specification says so
|
||||||
ldmia ip,{r4-r5} @ load remaining args
|
ldmia ip,{r4,r5} @ load remaining args
|
||||||
subs r2,r2,#16
|
subs r2,r2,#16
|
||||||
mov r8,#16
|
mov r8,#16
|
||||||
blo .Lcbc_abort
|
blo .Lcbc_abort
|
||||||
@ -297,13 +298,13 @@ aes_v8_cbc_encrypt:
|
|||||||
vld1.8 {q6},[r4]
|
vld1.8 {q6},[r4]
|
||||||
vld1.8 {q0},[r0],r8
|
vld1.8 {q0},[r0],r8
|
||||||
|
|
||||||
vld1.32 {q8-q9},[r3] @ load key schedule...
|
vld1.32 {q8,q9},[r3] @ load key schedule...
|
||||||
sub r5,r5,#6
|
sub r5,r5,#6
|
||||||
add r7,r3,r5,lsl#4 @ pointer to last 7 round keys
|
add r7,r3,r5,lsl#4 @ pointer to last 7 round keys
|
||||||
sub r5,r5,#2
|
sub r5,r5,#2
|
||||||
vld1.32 {q10-q11},[r7]!
|
vld1.32 {q10,q11},[r7]!
|
||||||
vld1.32 {q12-q13},[r7]!
|
vld1.32 {q12,q13},[r7]!
|
||||||
vld1.32 {q14-q15},[r7]!
|
vld1.32 {q14,q15},[r7]!
|
||||||
vld1.32 {q7},[r7]
|
vld1.32 {q7},[r7]
|
||||||
|
|
||||||
add r7,r3,#32
|
add r7,r3,#32
|
||||||
@ -315,7 +316,7 @@ aes_v8_cbc_encrypt:
|
|||||||
veor q5,q8,q7
|
veor q5,q8,q7
|
||||||
beq .Lcbc_enc128
|
beq .Lcbc_enc128
|
||||||
|
|
||||||
vld1.32 {q2-q3},[r7]
|
vld1.32 {q2,q3},[r7]
|
||||||
add r7,r3,#16
|
add r7,r3,#16
|
||||||
add r6,r3,#16*4
|
add r6,r3,#16*4
|
||||||
add r12,r3,#16*5
|
add r12,r3,#16*5
|
||||||
@ -379,7 +380,7 @@ aes_v8_cbc_encrypt:
|
|||||||
|
|
||||||
.align 5
|
.align 5
|
||||||
.Lcbc_enc128:
|
.Lcbc_enc128:
|
||||||
vld1.32 {q2-q3},[r7]
|
vld1.32 {q2,q3},[r7]
|
||||||
.byte 0x20,0x03,0xb0,0xf3 @ aese q0,q8
|
.byte 0x20,0x03,0xb0,0xf3 @ aese q0,q8
|
||||||
.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
|
.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
|
||||||
b .Lenter_cbc_enc128
|
b .Lenter_cbc_enc128
|
||||||
@ -567,30 +568,30 @@ aes_v8_cbc_encrypt:
|
|||||||
.Lcbc_done:
|
.Lcbc_done:
|
||||||
vst1.8 {q6},[r4]
|
vst1.8 {q6},[r4]
|
||||||
.Lcbc_abort:
|
.Lcbc_abort:
|
||||||
vldmia sp!,{d8-d15}
|
vldmia sp!,{d8,d9,d10,d11,d12,d13,d14,d15}
|
||||||
ldmia sp!,{r4-r8,pc}
|
ldmia sp!,{r4,r5,r6,r7,r8,pc}
|
||||||
.size aes_v8_cbc_encrypt,.-aes_v8_cbc_encrypt
|
.size aes_v8_cbc_encrypt,.-aes_v8_cbc_encrypt
|
||||||
.globl aes_v8_ctr32_encrypt_blocks
|
.globl aes_v8_ctr32_encrypt_blocks
|
||||||
.type aes_v8_ctr32_encrypt_blocks,%function
|
.type aes_v8_ctr32_encrypt_blocks,%function
|
||||||
.align 5
|
.align 5
|
||||||
aes_v8_ctr32_encrypt_blocks:
|
aes_v8_ctr32_encrypt_blocks:
|
||||||
mov ip,sp
|
mov ip,sp
|
||||||
stmdb sp!,{r4-r10,lr}
|
stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,lr}
|
||||||
vstmdb sp!,{d8-d15} @ ABI specification says so
|
vstmdb sp!,{d8,d9,d10,d11,d12,d13,d14,d15} @ ABI specification says so
|
||||||
ldr r4, [ip] @ load remaining arg
|
ldr r4, [ip] @ load remaining arg
|
||||||
ldr r5,[r3,#240]
|
ldr r5,[r3,#240]
|
||||||
|
|
||||||
ldr r8, [r4, #12]
|
ldr r8, [r4, #12]
|
||||||
vld1.32 {q0},[r4]
|
vld1.32 {q0},[r4]
|
||||||
|
|
||||||
vld1.32 {q8-q9},[r3] @ load key schedule...
|
vld1.32 {q8,q9},[r3] @ load key schedule...
|
||||||
sub r5,r5,#4
|
sub r5,r5,#4
|
||||||
mov r12,#16
|
mov r12,#16
|
||||||
cmp r2,#2
|
cmp r2,#2
|
||||||
add r7,r3,r5,lsl#4 @ pointer to last 5 round keys
|
add r7,r3,r5,lsl#4 @ pointer to last 5 round keys
|
||||||
sub r5,r5,#2
|
sub r5,r5,#2
|
||||||
vld1.32 {q12-q13},[r7]!
|
vld1.32 {q12,q13},[r7]!
|
||||||
vld1.32 {q14-q15},[r7]!
|
vld1.32 {q14,q15},[r7]!
|
||||||
vld1.32 {q7},[r7]
|
vld1.32 {q7},[r7]
|
||||||
add r7,r3,#32
|
add r7,r3,#32
|
||||||
mov r6,r5
|
mov r6,r5
|
||||||
@ -750,7 +751,7 @@ aes_v8_ctr32_encrypt_blocks:
|
|||||||
vst1.8 {q3},[r1]
|
vst1.8 {q3},[r1]
|
||||||
|
|
||||||
.Lctr32_done:
|
.Lctr32_done:
|
||||||
vldmia sp!,{d8-d15}
|
vldmia sp!,{d8,d9,d10,d11,d12,d13,d14,d15}
|
||||||
ldmia sp!,{r4-r10,pc}
|
ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,pc}
|
||||||
.size aes_v8_ctr32_encrypt_blocks,.-aes_v8_ctr32_encrypt_blocks
|
.size aes_v8_ctr32_encrypt_blocks,.-aes_v8_ctr32_encrypt_blocks
|
||||||
#endif
|
#endif
|
||||||
|
@ -3,7 +3,12 @@
|
|||||||
#include "arm_arch.h"
|
#include "arm_arch.h"
|
||||||
|
|
||||||
.text
|
.text
|
||||||
|
#if defined(__thumb2__)
|
||||||
|
.syntax unified
|
||||||
|
.thumb
|
||||||
|
#else
|
||||||
.code 32
|
.code 32
|
||||||
|
#endif
|
||||||
.type mul_1x1_ialu,%function
|
.type mul_1x1_ialu,%function
|
||||||
.align 5
|
.align 5
|
||||||
mul_1x1_ialu:
|
mul_1x1_ialu:
|
||||||
@ -71,11 +76,17 @@ mul_1x1_ialu:
|
|||||||
eor r4,r4,r6,lsr#8
|
eor r4,r4,r6,lsr#8
|
||||||
ldr r6,[sp,r8] @ tab[b >> 30 ]
|
ldr r6,[sp,r8] @ tab[b >> 30 ]
|
||||||
|
|
||||||
|
#ifdef __thumb2__
|
||||||
|
itt ne
|
||||||
|
#endif
|
||||||
eorne r5,r5,r0,lsl#30
|
eorne r5,r5,r0,lsl#30
|
||||||
eorne r4,r4,r0,lsr#2
|
eorne r4,r4,r0,lsr#2
|
||||||
tst r1,#1<<31
|
tst r1,#1<<31
|
||||||
eor r5,r5,r7,lsl#27
|
eor r5,r5,r7,lsl#27
|
||||||
eor r4,r4,r7,lsr#5
|
eor r4,r4,r7,lsr#5
|
||||||
|
#ifdef __thumb2__
|
||||||
|
itt ne
|
||||||
|
#endif
|
||||||
eorne r5,r5,r0,lsl#31
|
eorne r5,r5,r0,lsl#31
|
||||||
eorne r4,r4,r0,lsr#1
|
eorne r4,r4,r0,lsr#1
|
||||||
eor r5,r5,r6,lsl#30
|
eor r5,r5,r6,lsl#30
|
||||||
@ -83,22 +94,35 @@ mul_1x1_ialu:
|
|||||||
|
|
||||||
mov pc,lr
|
mov pc,lr
|
||||||
.size mul_1x1_ialu,.-mul_1x1_ialu
|
.size mul_1x1_ialu,.-mul_1x1_ialu
|
||||||
.global bn_GF2m_mul_2x2
|
.globl bn_GF2m_mul_2x2
|
||||||
.type bn_GF2m_mul_2x2,%function
|
.type bn_GF2m_mul_2x2,%function
|
||||||
.align 5
|
.align 5
|
||||||
bn_GF2m_mul_2x2:
|
bn_GF2m_mul_2x2:
|
||||||
#if __ARM_MAX_ARCH__>=7
|
#if __ARM_MAX_ARCH__>=7
|
||||||
|
stmdb sp!,{r10,lr}
|
||||||
ldr r12,.LOPENSSL_armcap
|
ldr r12,.LOPENSSL_armcap
|
||||||
.Lpic: ldr r12,[pc,r12]
|
adr r10,.LOPENSSL_armcap
|
||||||
tst r12,#1
|
ldr r12,[r12,r10]
|
||||||
bne .LNEON
|
#ifdef __APPLE__
|
||||||
|
ldr r12,[r12]
|
||||||
|
#endif
|
||||||
|
tst r12,#ARMV7_NEON
|
||||||
|
itt ne
|
||||||
|
ldrne r10,[sp],#8
|
||||||
|
bne .LNEON
|
||||||
|
stmdb sp!,{r4,r5,r6,r7,r8,r9}
|
||||||
|
#else
|
||||||
|
stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,lr}
|
||||||
#endif
|
#endif
|
||||||
stmdb sp!,{r4-r10,lr}
|
|
||||||
mov r10,r0 @ reassign 1st argument
|
mov r10,r0 @ reassign 1st argument
|
||||||
mov r0,r3 @ r0=b1
|
mov r0,r3 @ r0=b1
|
||||||
|
sub r7,sp,#36
|
||||||
|
mov r8,sp
|
||||||
|
and r7,r7,#-32
|
||||||
ldr r3,[sp,#32] @ load b0
|
ldr r3,[sp,#32] @ load b0
|
||||||
mov r12,#7<<2
|
mov r12,#7<<2
|
||||||
sub sp,sp,#32 @ allocate tab[8]
|
mov sp,r7 @ allocate tab[8]
|
||||||
|
str r8,[r7,#32]
|
||||||
|
|
||||||
bl mul_1x1_ialu @ a1·b1
|
bl mul_1x1_ialu @ a1·b1
|
||||||
str r5,[r10,#8]
|
str r5,[r10,#8]
|
||||||
@ -117,8 +141,9 @@ bn_GF2m_mul_2x2:
|
|||||||
eor r1,r1,r2
|
eor r1,r1,r2
|
||||||
eor r0,r0,r3
|
eor r0,r0,r3
|
||||||
bl mul_1x1_ialu @ (a1+a0)·(b1+b0)
|
bl mul_1x1_ialu @ (a1+a0)·(b1+b0)
|
||||||
ldmia r10,{r6-r9}
|
ldmia r10,{r6,r7,r8,r9}
|
||||||
eor r5,r5,r4
|
eor r5,r5,r4
|
||||||
|
ldr sp,[sp,#32] @ destroy tab[8]
|
||||||
eor r4,r4,r7
|
eor r4,r4,r7
|
||||||
eor r5,r5,r6
|
eor r5,r5,r6
|
||||||
eor r4,r4,r8
|
eor r4,r4,r8
|
||||||
@ -126,13 +151,12 @@ bn_GF2m_mul_2x2:
|
|||||||
eor r4,r4,r9
|
eor r4,r4,r9
|
||||||
str r4,[r10,#8]
|
str r4,[r10,#8]
|
||||||
eor r5,r5,r4
|
eor r5,r5,r4
|
||||||
add sp,sp,#32 @ destroy tab[8]
|
|
||||||
str r5,[r10,#4]
|
str r5,[r10,#4]
|
||||||
|
|
||||||
#if __ARM_ARCH__>=5
|
#if __ARM_ARCH__>=5
|
||||||
ldmia sp!,{r4-r10,pc}
|
ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,pc}
|
||||||
#else
|
#else
|
||||||
ldmia sp!,{r4-r10,lr}
|
ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,lr}
|
||||||
tst lr,#1
|
tst lr,#1
|
||||||
moveq pc,lr @ be binary compatible with V4, yet
|
moveq pc,lr @ be binary compatible with V4, yet
|
||||||
.word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
.word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
||||||
@ -195,9 +219,10 @@ bn_GF2m_mul_2x2:
|
|||||||
#if __ARM_MAX_ARCH__>=7
|
#if __ARM_MAX_ARCH__>=7
|
||||||
.align 5
|
.align 5
|
||||||
.LOPENSSL_armcap:
|
.LOPENSSL_armcap:
|
||||||
.word OPENSSL_armcap_P-(.Lpic+8)
|
.word OPENSSL_armcap_P-.
|
||||||
#endif
|
#endif
|
||||||
.asciz "GF(2^m) Multiplication for ARMv4/NEON, CRYPTOGAMS by <appro@openssl.org>"
|
.byte 71,70,40,50,94,109,41,32,77,117,108,116,105,112,108,105,99,97,116,105,111,110,32,102,111,114,32,65,82,77,118,52,47,78,69,79,78,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
|
||||||
|
.align 2
|
||||||
.align 5
|
.align 5
|
||||||
|
|
||||||
#if __ARM_MAX_ARCH__>=7
|
#if __ARM_MAX_ARCH__>=7
|
||||||
|
@ -3,28 +3,37 @@
|
|||||||
#include "arm_arch.h"
|
#include "arm_arch.h"
|
||||||
|
|
||||||
.text
|
.text
|
||||||
|
#if defined(__thumb2__)
|
||||||
|
.syntax unified
|
||||||
|
.thumb
|
||||||
|
#else
|
||||||
.code 32
|
.code 32
|
||||||
|
#endif
|
||||||
|
|
||||||
#if __ARM_MAX_ARCH__>=7
|
#if __ARM_MAX_ARCH__>=7
|
||||||
.align 5
|
.align 5
|
||||||
.LOPENSSL_armcap:
|
.LOPENSSL_armcap:
|
||||||
.word OPENSSL_armcap_P-bn_mul_mont
|
.word OPENSSL_armcap_P-.Lbn_mul_mont
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
.global bn_mul_mont
|
.globl bn_mul_mont
|
||||||
.type bn_mul_mont,%function
|
.type bn_mul_mont,%function
|
||||||
|
|
||||||
.align 5
|
.align 5
|
||||||
bn_mul_mont:
|
bn_mul_mont:
|
||||||
|
.Lbn_mul_mont:
|
||||||
ldr ip,[sp,#4] @ load num
|
ldr ip,[sp,#4] @ load num
|
||||||
stmdb sp!,{r0,r2} @ sp points at argument block
|
stmdb sp!,{r0,r2} @ sp points at argument block
|
||||||
#if __ARM_MAX_ARCH__>=7
|
#if __ARM_MAX_ARCH__>=7
|
||||||
tst ip,#7
|
tst ip,#7
|
||||||
bne .Lialu
|
bne .Lialu
|
||||||
adr r0,bn_mul_mont
|
adr r0,.Lbn_mul_mont
|
||||||
ldr r2,.LOPENSSL_armcap
|
ldr r2,.LOPENSSL_armcap
|
||||||
ldr r0,[r0,r2]
|
ldr r0,[r0,r2]
|
||||||
tst r0,#1 @ NEON available?
|
#ifdef __APPLE__
|
||||||
|
ldr r0,[r0]
|
||||||
|
#endif
|
||||||
|
tst r0,#ARMV7_NEON @ NEON available?
|
||||||
ldmia sp, {r0,r2}
|
ldmia sp, {r0,r2}
|
||||||
beq .Lialu
|
beq .Lialu
|
||||||
add sp,sp,#8
|
add sp,sp,#8
|
||||||
@ -34,11 +43,14 @@ bn_mul_mont:
|
|||||||
#endif
|
#endif
|
||||||
cmp ip,#2
|
cmp ip,#2
|
||||||
mov r0,ip @ load num
|
mov r0,ip @ load num
|
||||||
|
#ifdef __thumb2__
|
||||||
|
ittt lt
|
||||||
|
#endif
|
||||||
movlt r0,#0
|
movlt r0,#0
|
||||||
addlt sp,sp,#2*4
|
addlt sp,sp,#2*4
|
||||||
blt .Labrt
|
blt .Labrt
|
||||||
|
|
||||||
stmdb sp!,{r4-r12,lr} @ save 10 registers
|
stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} @ save 10 registers
|
||||||
|
|
||||||
mov r0,r0,lsl#2 @ rescale r0 for byte count
|
mov r0,r0,lsl#2 @ rescale r0 for byte count
|
||||||
sub sp,sp,r0 @ alloca(4*num)
|
sub sp,sp,r0 @ alloca(4*num)
|
||||||
@ -81,10 +93,11 @@ bn_mul_mont:
|
|||||||
ldr r8,[r0,#14*4] @ restore n0
|
ldr r8,[r0,#14*4] @ restore n0
|
||||||
adc r14,r14,#0
|
adc r14,r14,#0
|
||||||
str r12,[r0] @ tp[num-1]=
|
str r12,[r0] @ tp[num-1]=
|
||||||
|
mov r7,sp
|
||||||
str r14,[r0,#4] @ tp[num]=
|
str r14,[r0,#4] @ tp[num]=
|
||||||
|
|
||||||
.Louter:
|
.Louter:
|
||||||
sub r7,r0,sp @ "original" r0-1 value
|
sub r7,r0,r7 @ "original" r0-1 value
|
||||||
sub r1,r1,r7 @ "rewind" ap to &ap[1]
|
sub r1,r1,r7 @ "rewind" ap to &ap[1]
|
||||||
ldr r2,[r4,#4]! @ *(++bp)
|
ldr r2,[r4,#4]! @ *(++bp)
|
||||||
sub r3,r3,r7 @ "rewind" np to &np[1]
|
sub r3,r3,r7 @ "rewind" np to &np[1]
|
||||||
@ -129,11 +142,16 @@ bn_mul_mont:
|
|||||||
str r14,[r0,#4] @ tp[num]=
|
str r14,[r0,#4] @ tp[num]=
|
||||||
|
|
||||||
cmp r4,r7
|
cmp r4,r7
|
||||||
|
#ifdef __thumb2__
|
||||||
|
itt ne
|
||||||
|
#endif
|
||||||
|
movne r7,sp
|
||||||
bne .Louter
|
bne .Louter
|
||||||
|
|
||||||
ldr r2,[r0,#12*4] @ pull rp
|
ldr r2,[r0,#12*4] @ pull rp
|
||||||
|
mov r5,sp
|
||||||
add r0,r0,#4 @ r0 to point at &tp[num]
|
add r0,r0,#4 @ r0 to point at &tp[num]
|
||||||
sub r5,r0,sp @ "original" num value
|
sub r5,r0,r5 @ "original" num value
|
||||||
mov r4,sp @ "rewind" r4
|
mov r4,sp @ "rewind" r4
|
||||||
mov r1,r4 @ "borrow" r1
|
mov r1,r4 @ "borrow" r1
|
||||||
sub r3,r3,r5 @ "rewind" r3 to &np[0]
|
sub r3,r3,r5 @ "rewind" r3 to &np[0]
|
||||||
@ -160,13 +178,14 @@ bn_mul_mont:
|
|||||||
teq r4,r0 @ preserve carry
|
teq r4,r0 @ preserve carry
|
||||||
bne .Lcopy
|
bne .Lcopy
|
||||||
|
|
||||||
add sp,r0,#4 @ skip over tp[num+1]
|
mov sp,r0
|
||||||
ldmia sp!,{r4-r12,lr} @ restore registers
|
add sp,sp,#4 @ skip over tp[num+1]
|
||||||
|
ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} @ restore registers
|
||||||
add sp,sp,#2*4 @ skip over {r0,r2}
|
add sp,sp,#2*4 @ skip over {r0,r2}
|
||||||
mov r0,#1
|
mov r0,#1
|
||||||
.Labrt:
|
.Labrt:
|
||||||
#if __ARM_ARCH__>=5
|
#if __ARM_ARCH__>=5
|
||||||
bx lr @ .word 0xe12fff1e
|
bx lr @ bx lr
|
||||||
#else
|
#else
|
||||||
tst lr,#1
|
tst lr,#1
|
||||||
moveq pc,lr @ be binary compatible with V4, yet
|
moveq pc,lr @ be binary compatible with V4, yet
|
||||||
@ -181,42 +200,42 @@ bn_mul_mont:
|
|||||||
.align 5
|
.align 5
|
||||||
bn_mul8x_mont_neon:
|
bn_mul8x_mont_neon:
|
||||||
mov ip,sp
|
mov ip,sp
|
||||||
stmdb sp!,{r4-r11}
|
stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11}
|
||||||
vstmdb sp!,{d8-d15} @ ABI specification says so
|
vstmdb sp!,{d8,d9,d10,d11,d12,d13,d14,d15} @ ABI specification says so
|
||||||
ldmia ip,{r4-r5} @ load rest of parameter block
|
ldmia ip,{r4,r5} @ load rest of parameter block
|
||||||
|
mov ip,sp
|
||||||
|
|
||||||
|
cmp r5,#8
|
||||||
|
bhi .LNEON_8n
|
||||||
|
|
||||||
|
@ special case for r5==8, everything is in register bank...
|
||||||
|
|
||||||
sub r7,sp,#16
|
|
||||||
vld1.32 {d28[0]}, [r2,:32]!
|
vld1.32 {d28[0]}, [r2,:32]!
|
||||||
sub r7,r7,r5,lsl#4
|
veor d8,d8,d8
|
||||||
vld1.32 {d0-d3}, [r1]! @ can't specify :32 :-(
|
sub r7,sp,r5,lsl#4
|
||||||
|
vld1.32 {d0,d1,d2,d3}, [r1]! @ can't specify :32 :-(
|
||||||
and r7,r7,#-64
|
and r7,r7,#-64
|
||||||
vld1.32 {d30[0]}, [r4,:32]
|
vld1.32 {d30[0]}, [r4,:32]
|
||||||
mov sp,r7 @ alloca
|
mov sp,r7 @ alloca
|
||||||
veor d8,d8,d8
|
|
||||||
subs r8,r5,#8
|
|
||||||
vzip.16 d28,d8
|
vzip.16 d28,d8
|
||||||
|
|
||||||
vmull.u32 q6,d28,d0[0]
|
vmull.u32 q6,d28,d0[0]
|
||||||
vmull.u32 q7,d28,d0[1]
|
vmull.u32 q7,d28,d0[1]
|
||||||
vmull.u32 q8,d28,d1[0]
|
vmull.u32 q8,d28,d1[0]
|
||||||
vshl.i64 d10,d13,#16
|
vshl.i64 d29,d13,#16
|
||||||
vmull.u32 q9,d28,d1[1]
|
vmull.u32 q9,d28,d1[1]
|
||||||
|
|
||||||
vadd.u64 d10,d10,d12
|
vadd.u64 d29,d29,d12
|
||||||
veor d8,d8,d8
|
veor d8,d8,d8
|
||||||
vmul.u32 d29,d10,d30
|
vmul.u32 d29,d29,d30
|
||||||
|
|
||||||
vmull.u32 q10,d28,d2[0]
|
vmull.u32 q10,d28,d2[0]
|
||||||
vld1.32 {d4-d7}, [r3]!
|
vld1.32 {d4,d5,d6,d7}, [r3]!
|
||||||
vmull.u32 q11,d28,d2[1]
|
vmull.u32 q11,d28,d2[1]
|
||||||
vmull.u32 q12,d28,d3[0]
|
vmull.u32 q12,d28,d3[0]
|
||||||
vzip.16 d29,d8
|
vzip.16 d29,d8
|
||||||
vmull.u32 q13,d28,d3[1]
|
vmull.u32 q13,d28,d3[1]
|
||||||
|
|
||||||
bne .LNEON_1st
|
|
||||||
|
|
||||||
@ special case for num=8, everything is in register bank...
|
|
||||||
|
|
||||||
vmlal.u32 q6,d29,d4[0]
|
vmlal.u32 q6,d29,d4[0]
|
||||||
sub r9,r5,#1
|
sub r9,r5,#1
|
||||||
vmlal.u32 q7,d29,d4[1]
|
vmlal.u32 q7,d29,d4[1]
|
||||||
@ -252,13 +271,13 @@ bn_mul8x_mont_neon:
|
|||||||
vmlal.u32 q6,d28,d0[0]
|
vmlal.u32 q6,d28,d0[0]
|
||||||
vmlal.u32 q7,d28,d0[1]
|
vmlal.u32 q7,d28,d0[1]
|
||||||
vmlal.u32 q8,d28,d1[0]
|
vmlal.u32 q8,d28,d1[0]
|
||||||
vshl.i64 d10,d13,#16
|
vshl.i64 d29,d13,#16
|
||||||
vmlal.u32 q9,d28,d1[1]
|
vmlal.u32 q9,d28,d1[1]
|
||||||
|
|
||||||
vadd.u64 d10,d10,d12
|
vadd.u64 d29,d29,d12
|
||||||
veor d8,d8,d8
|
veor d8,d8,d8
|
||||||
subs r9,r9,#1
|
subs r9,r9,#1
|
||||||
vmul.u32 d29,d10,d30
|
vmul.u32 d29,d29,d30
|
||||||
|
|
||||||
vmlal.u32 q10,d28,d2[0]
|
vmlal.u32 q10,d28,d2[0]
|
||||||
vmlal.u32 q11,d28,d2[1]
|
vmlal.u32 q11,d28,d2[1]
|
||||||
@ -295,231 +314,576 @@ bn_mul8x_mont_neon:
|
|||||||
vshr.u64 d10,d12,#16
|
vshr.u64 d10,d12,#16
|
||||||
mov r8,r5
|
mov r8,r5
|
||||||
vadd.u64 d13,d13,d10
|
vadd.u64 d13,d13,d10
|
||||||
add r6,sp,#16
|
add r6,sp,#96
|
||||||
vshr.u64 d10,d13,#16
|
vshr.u64 d10,d13,#16
|
||||||
vzip.16 d12,d13
|
vzip.16 d12,d13
|
||||||
|
|
||||||
b .LNEON_tail2
|
b .LNEON_tail_entry
|
||||||
|
|
||||||
.align 4
|
.align 4
|
||||||
.LNEON_1st:
|
.LNEON_8n:
|
||||||
vmlal.u32 q6,d29,d4[0]
|
veor q6,q6,q6
|
||||||
vld1.32 {d0-d3}, [r1]!
|
sub r7,sp,#128
|
||||||
vmlal.u32 q7,d29,d4[1]
|
veor q7,q7,q7
|
||||||
subs r8,r8,#8
|
sub r7,r7,r5,lsl#4
|
||||||
vmlal.u32 q8,d29,d5[0]
|
veor q8,q8,q8
|
||||||
vmlal.u32 q9,d29,d5[1]
|
and r7,r7,#-64
|
||||||
|
veor q9,q9,q9
|
||||||
vmlal.u32 q10,d29,d6[0]
|
mov sp,r7 @ alloca
|
||||||
vld1.32 {d4-d5}, [r3]!
|
veor q10,q10,q10
|
||||||
vmlal.u32 q11,d29,d6[1]
|
add r7,r7,#256
|
||||||
vst1.64 {q6-q7}, [r7,:256]!
|
veor q11,q11,q11
|
||||||
vmlal.u32 q12,d29,d7[0]
|
|
||||||
vmlal.u32 q13,d29,d7[1]
|
|
||||||
vst1.64 {q8-q9}, [r7,:256]!
|
|
||||||
|
|
||||||
vmull.u32 q6,d28,d0[0]
|
|
||||||
vld1.32 {d6-d7}, [r3]!
|
|
||||||
vmull.u32 q7,d28,d0[1]
|
|
||||||
vst1.64 {q10-q11}, [r7,:256]!
|
|
||||||
vmull.u32 q8,d28,d1[0]
|
|
||||||
vmull.u32 q9,d28,d1[1]
|
|
||||||
vst1.64 {q12-q13}, [r7,:256]!
|
|
||||||
|
|
||||||
vmull.u32 q10,d28,d2[0]
|
|
||||||
vmull.u32 q11,d28,d2[1]
|
|
||||||
vmull.u32 q12,d28,d3[0]
|
|
||||||
vmull.u32 q13,d28,d3[1]
|
|
||||||
|
|
||||||
bne .LNEON_1st
|
|
||||||
|
|
||||||
vmlal.u32 q6,d29,d4[0]
|
|
||||||
add r6,sp,#16
|
|
||||||
vmlal.u32 q7,d29,d4[1]
|
|
||||||
sub r1,r1,r5,lsl#2 @ rewind r1
|
|
||||||
vmlal.u32 q8,d29,d5[0]
|
|
||||||
vld1.64 {q5}, [sp,:128]
|
|
||||||
vmlal.u32 q9,d29,d5[1]
|
|
||||||
sub r9,r5,#1
|
|
||||||
|
|
||||||
vmlal.u32 q10,d29,d6[0]
|
|
||||||
vst1.64 {q6-q7}, [r7,:256]!
|
|
||||||
vmlal.u32 q11,d29,d6[1]
|
|
||||||
vshr.u64 d10,d10,#16
|
|
||||||
vld1.64 {q6}, [r6, :128]!
|
|
||||||
vmlal.u32 q12,d29,d7[0]
|
|
||||||
vst1.64 {q8-q9}, [r7,:256]!
|
|
||||||
vmlal.u32 q13,d29,d7[1]
|
|
||||||
|
|
||||||
vst1.64 {q10-q11}, [r7,:256]!
|
|
||||||
vadd.u64 d10,d10,d11
|
|
||||||
veor q4,q4,q4
|
|
||||||
vst1.64 {q12-q13}, [r7,:256]!
|
|
||||||
vld1.64 {q7-q8}, [r6, :256]!
|
|
||||||
vst1.64 {q4}, [r7,:128]
|
|
||||||
vshr.u64 d10,d10,#16
|
|
||||||
|
|
||||||
b .LNEON_outer
|
|
||||||
|
|
||||||
.align 4
|
|
||||||
.LNEON_outer:
|
|
||||||
vld1.32 {d28[0]}, [r2,:32]!
|
|
||||||
sub r3,r3,r5,lsl#2 @ rewind r3
|
|
||||||
vld1.32 {d0-d3}, [r1]!
|
|
||||||
veor d8,d8,d8
|
|
||||||
mov r7,sp
|
|
||||||
vzip.16 d28,d8
|
|
||||||
sub r8,r5,#8
|
sub r8,r5,#8
|
||||||
vadd.u64 d12,d12,d10
|
veor q12,q12,q12
|
||||||
|
veor q13,q13,q13
|
||||||
|
|
||||||
|
.LNEON_8n_init:
|
||||||
|
vst1.64 {q6,q7},[r7,:256]!
|
||||||
|
subs r8,r8,#8
|
||||||
|
vst1.64 {q8,q9},[r7,:256]!
|
||||||
|
vst1.64 {q10,q11},[r7,:256]!
|
||||||
|
vst1.64 {q12,q13},[r7,:256]!
|
||||||
|
bne .LNEON_8n_init
|
||||||
|
|
||||||
|
add r6,sp,#256
|
||||||
|
vld1.32 {d0,d1,d2,d3},[r1]!
|
||||||
|
add r10,sp,#8
|
||||||
|
vld1.32 {d30[0]},[r4,:32]
|
||||||
|
mov r9,r5
|
||||||
|
b .LNEON_8n_outer
|
||||||
|
|
||||||
|
.align 4
|
||||||
|
.LNEON_8n_outer:
|
||||||
|
vld1.32 {d28[0]},[r2,:32]! @ *b++
|
||||||
|
veor d8,d8,d8
|
||||||
|
vzip.16 d28,d8
|
||||||
|
add r7,sp,#128
|
||||||
|
vld1.32 {d4,d5,d6,d7},[r3]!
|
||||||
|
|
||||||
vmlal.u32 q6,d28,d0[0]
|
vmlal.u32 q6,d28,d0[0]
|
||||||
vld1.64 {q9-q10},[r6,:256]!
|
|
||||||
vmlal.u32 q7,d28,d0[1]
|
vmlal.u32 q7,d28,d0[1]
|
||||||
vmlal.u32 q8,d28,d1[0]
|
|
||||||
vld1.64 {q11-q12},[r6,:256]!
|
|
||||||
vmlal.u32 q9,d28,d1[1]
|
|
||||||
|
|
||||||
vshl.i64 d10,d13,#16
|
|
||||||
veor d8,d8,d8
|
veor d8,d8,d8
|
||||||
vadd.u64 d10,d10,d12
|
vmlal.u32 q8,d28,d1[0]
|
||||||
vld1.64 {q13},[r6,:128]!
|
vshl.i64 d29,d13,#16
|
||||||
vmul.u32 d29,d10,d30
|
vmlal.u32 q9,d28,d1[1]
|
||||||
|
vadd.u64 d29,d29,d12
|
||||||
vmlal.u32 q10,d28,d2[0]
|
vmlal.u32 q10,d28,d2[0]
|
||||||
vld1.32 {d4-d7}, [r3]!
|
vmul.u32 d29,d29,d30
|
||||||
vmlal.u32 q11,d28,d2[1]
|
vmlal.u32 q11,d28,d2[1]
|
||||||
|
vst1.32 {d28},[sp,:64] @ put aside smashed b[8*i+0]
|
||||||
vmlal.u32 q12,d28,d3[0]
|
vmlal.u32 q12,d28,d3[0]
|
||||||
vzip.16 d29,d8
|
vzip.16 d29,d8
|
||||||
vmlal.u32 q13,d28,d3[1]
|
vmlal.u32 q13,d28,d3[1]
|
||||||
|
vld1.32 {d28[0]},[r2,:32]! @ *b++
|
||||||
.LNEON_inner:
|
|
||||||
vmlal.u32 q6,d29,d4[0]
|
vmlal.u32 q6,d29,d4[0]
|
||||||
vld1.32 {d0-d3}, [r1]!
|
veor d10,d10,d10
|
||||||
vmlal.u32 q7,d29,d4[1]
|
vmlal.u32 q7,d29,d4[1]
|
||||||
subs r8,r8,#8
|
vzip.16 d28,d10
|
||||||
vmlal.u32 q8,d29,d5[0]
|
vmlal.u32 q8,d29,d5[0]
|
||||||
|
vshr.u64 d12,d12,#16
|
||||||
vmlal.u32 q9,d29,d5[1]
|
vmlal.u32 q9,d29,d5[1]
|
||||||
vst1.64 {q6-q7}, [r7,:256]!
|
|
||||||
|
|
||||||
vmlal.u32 q10,d29,d6[0]
|
vmlal.u32 q10,d29,d6[0]
|
||||||
vld1.64 {q6}, [r6, :128]!
|
vadd.u64 d12,d12,d13
|
||||||
vmlal.u32 q11,d29,d6[1]
|
vmlal.u32 q11,d29,d6[1]
|
||||||
vst1.64 {q8-q9}, [r7,:256]!
|
vshr.u64 d12,d12,#16
|
||||||
vmlal.u32 q12,d29,d7[0]
|
vmlal.u32 q12,d29,d7[0]
|
||||||
vld1.64 {q7-q8}, [r6, :256]!
|
|
||||||
vmlal.u32 q13,d29,d7[1]
|
vmlal.u32 q13,d29,d7[1]
|
||||||
vst1.64 {q10-q11}, [r7,:256]!
|
vadd.u64 d14,d14,d12
|
||||||
|
vst1.32 {d29},[r10,:64]! @ put aside smashed m[8*i+0]
|
||||||
|
vmlal.u32 q7,d28,d0[0]
|
||||||
|
vld1.64 {q6},[r6,:128]!
|
||||||
|
vmlal.u32 q8,d28,d0[1]
|
||||||
|
veor d8,d8,d8
|
||||||
|
vmlal.u32 q9,d28,d1[0]
|
||||||
|
vshl.i64 d29,d15,#16
|
||||||
|
vmlal.u32 q10,d28,d1[1]
|
||||||
|
vadd.u64 d29,d29,d14
|
||||||
|
vmlal.u32 q11,d28,d2[0]
|
||||||
|
vmul.u32 d29,d29,d30
|
||||||
|
vmlal.u32 q12,d28,d2[1]
|
||||||
|
vst1.32 {d28},[r10,:64]! @ put aside smashed b[8*i+1]
|
||||||
|
vmlal.u32 q13,d28,d3[0]
|
||||||
|
vzip.16 d29,d8
|
||||||
|
vmlal.u32 q6,d28,d3[1]
|
||||||
|
vld1.32 {d28[0]},[r2,:32]! @ *b++
|
||||||
|
vmlal.u32 q7,d29,d4[0]
|
||||||
|
veor d10,d10,d10
|
||||||
|
vmlal.u32 q8,d29,d4[1]
|
||||||
|
vzip.16 d28,d10
|
||||||
|
vmlal.u32 q9,d29,d5[0]
|
||||||
|
vshr.u64 d14,d14,#16
|
||||||
|
vmlal.u32 q10,d29,d5[1]
|
||||||
|
vmlal.u32 q11,d29,d6[0]
|
||||||
|
vadd.u64 d14,d14,d15
|
||||||
|
vmlal.u32 q12,d29,d6[1]
|
||||||
|
vshr.u64 d14,d14,#16
|
||||||
|
vmlal.u32 q13,d29,d7[0]
|
||||||
|
vmlal.u32 q6,d29,d7[1]
|
||||||
|
vadd.u64 d16,d16,d14
|
||||||
|
vst1.32 {d29},[r10,:64]! @ put aside smashed m[8*i+1]
|
||||||
|
vmlal.u32 q8,d28,d0[0]
|
||||||
|
vld1.64 {q7},[r6,:128]!
|
||||||
|
vmlal.u32 q9,d28,d0[1]
|
||||||
|
veor d8,d8,d8
|
||||||
|
vmlal.u32 q10,d28,d1[0]
|
||||||
|
vshl.i64 d29,d17,#16
|
||||||
|
vmlal.u32 q11,d28,d1[1]
|
||||||
|
vadd.u64 d29,d29,d16
|
||||||
|
vmlal.u32 q12,d28,d2[0]
|
||||||
|
vmul.u32 d29,d29,d30
|
||||||
|
vmlal.u32 q13,d28,d2[1]
|
||||||
|
vst1.32 {d28},[r10,:64]! @ put aside smashed b[8*i+2]
|
||||||
|
vmlal.u32 q6,d28,d3[0]
|
||||||
|
vzip.16 d29,d8
|
||||||
|
vmlal.u32 q7,d28,d3[1]
|
||||||
|
vld1.32 {d28[0]},[r2,:32]! @ *b++
|
||||||
|
vmlal.u32 q8,d29,d4[0]
|
||||||
|
veor d10,d10,d10
|
||||||
|
vmlal.u32 q9,d29,d4[1]
|
||||||
|
vzip.16 d28,d10
|
||||||
|
vmlal.u32 q10,d29,d5[0]
|
||||||
|
vshr.u64 d16,d16,#16
|
||||||
|
vmlal.u32 q11,d29,d5[1]
|
||||||
|
vmlal.u32 q12,d29,d6[0]
|
||||||
|
vadd.u64 d16,d16,d17
|
||||||
|
vmlal.u32 q13,d29,d6[1]
|
||||||
|
vshr.u64 d16,d16,#16
|
||||||
|
vmlal.u32 q6,d29,d7[0]
|
||||||
|
vmlal.u32 q7,d29,d7[1]
|
||||||
|
vadd.u64 d18,d18,d16
|
||||||
|
vst1.32 {d29},[r10,:64]! @ put aside smashed m[8*i+2]
|
||||||
|
vmlal.u32 q9,d28,d0[0]
|
||||||
|
vld1.64 {q8},[r6,:128]!
|
||||||
|
vmlal.u32 q10,d28,d0[1]
|
||||||
|
veor d8,d8,d8
|
||||||
|
vmlal.u32 q11,d28,d1[0]
|
||||||
|
vshl.i64 d29,d19,#16
|
||||||
|
vmlal.u32 q12,d28,d1[1]
|
||||||
|
vadd.u64 d29,d29,d18
|
||||||
|
vmlal.u32 q13,d28,d2[0]
|
||||||
|
vmul.u32 d29,d29,d30
|
||||||
|
vmlal.u32 q6,d28,d2[1]
|
||||||
|
vst1.32 {d28},[r10,:64]! @ put aside smashed b[8*i+3]
|
||||||
|
vmlal.u32 q7,d28,d3[0]
|
||||||
|
vzip.16 d29,d8
|
||||||
|
vmlal.u32 q8,d28,d3[1]
|
||||||
|
vld1.32 {d28[0]},[r2,:32]! @ *b++
|
||||||
|
vmlal.u32 q9,d29,d4[0]
|
||||||
|
veor d10,d10,d10
|
||||||
|
vmlal.u32 q10,d29,d4[1]
|
||||||
|
vzip.16 d28,d10
|
||||||
|
vmlal.u32 q11,d29,d5[0]
|
||||||
|
vshr.u64 d18,d18,#16
|
||||||
|
vmlal.u32 q12,d29,d5[1]
|
||||||
|
vmlal.u32 q13,d29,d6[0]
|
||||||
|
vadd.u64 d18,d18,d19
|
||||||
|
vmlal.u32 q6,d29,d6[1]
|
||||||
|
vshr.u64 d18,d18,#16
|
||||||
|
vmlal.u32 q7,d29,d7[0]
|
||||||
|
vmlal.u32 q8,d29,d7[1]
|
||||||
|
vadd.u64 d20,d20,d18
|
||||||
|
vst1.32 {d29},[r10,:64]! @ put aside smashed m[8*i+3]
|
||||||
|
vmlal.u32 q10,d28,d0[0]
|
||||||
|
vld1.64 {q9},[r6,:128]!
|
||||||
|
vmlal.u32 q11,d28,d0[1]
|
||||||
|
veor d8,d8,d8
|
||||||
|
vmlal.u32 q12,d28,d1[0]
|
||||||
|
vshl.i64 d29,d21,#16
|
||||||
|
vmlal.u32 q13,d28,d1[1]
|
||||||
|
vadd.u64 d29,d29,d20
|
||||||
|
vmlal.u32 q6,d28,d2[0]
|
||||||
|
vmul.u32 d29,d29,d30
|
||||||
|
vmlal.u32 q7,d28,d2[1]
|
||||||
|
vst1.32 {d28},[r10,:64]! @ put aside smashed b[8*i+4]
|
||||||
|
vmlal.u32 q8,d28,d3[0]
|
||||||
|
vzip.16 d29,d8
|
||||||
|
vmlal.u32 q9,d28,d3[1]
|
||||||
|
vld1.32 {d28[0]},[r2,:32]! @ *b++
|
||||||
|
vmlal.u32 q10,d29,d4[0]
|
||||||
|
veor d10,d10,d10
|
||||||
|
vmlal.u32 q11,d29,d4[1]
|
||||||
|
vzip.16 d28,d10
|
||||||
|
vmlal.u32 q12,d29,d5[0]
|
||||||
|
vshr.u64 d20,d20,#16
|
||||||
|
vmlal.u32 q13,d29,d5[1]
|
||||||
|
vmlal.u32 q6,d29,d6[0]
|
||||||
|
vadd.u64 d20,d20,d21
|
||||||
|
vmlal.u32 q7,d29,d6[1]
|
||||||
|
vshr.u64 d20,d20,#16
|
||||||
|
vmlal.u32 q8,d29,d7[0]
|
||||||
|
vmlal.u32 q9,d29,d7[1]
|
||||||
|
vadd.u64 d22,d22,d20
|
||||||
|
vst1.32 {d29},[r10,:64]! @ put aside smashed m[8*i+4]
|
||||||
|
vmlal.u32 q11,d28,d0[0]
|
||||||
|
vld1.64 {q10},[r6,:128]!
|
||||||
|
vmlal.u32 q12,d28,d0[1]
|
||||||
|
veor d8,d8,d8
|
||||||
|
vmlal.u32 q13,d28,d1[0]
|
||||||
|
vshl.i64 d29,d23,#16
|
||||||
|
vmlal.u32 q6,d28,d1[1]
|
||||||
|
vadd.u64 d29,d29,d22
|
||||||
|
vmlal.u32 q7,d28,d2[0]
|
||||||
|
vmul.u32 d29,d29,d30
|
||||||
|
vmlal.u32 q8,d28,d2[1]
|
||||||
|
vst1.32 {d28},[r10,:64]! @ put aside smashed b[8*i+5]
|
||||||
|
vmlal.u32 q9,d28,d3[0]
|
||||||
|
vzip.16 d29,d8
|
||||||
|
vmlal.u32 q10,d28,d3[1]
|
||||||
|
vld1.32 {d28[0]},[r2,:32]! @ *b++
|
||||||
|
vmlal.u32 q11,d29,d4[0]
|
||||||
|
veor d10,d10,d10
|
||||||
|
vmlal.u32 q12,d29,d4[1]
|
||||||
|
vzip.16 d28,d10
|
||||||
|
vmlal.u32 q13,d29,d5[0]
|
||||||
|
vshr.u64 d22,d22,#16
|
||||||
|
vmlal.u32 q6,d29,d5[1]
|
||||||
|
vmlal.u32 q7,d29,d6[0]
|
||||||
|
vadd.u64 d22,d22,d23
|
||||||
|
vmlal.u32 q8,d29,d6[1]
|
||||||
|
vshr.u64 d22,d22,#16
|
||||||
|
vmlal.u32 q9,d29,d7[0]
|
||||||
|
vmlal.u32 q10,d29,d7[1]
|
||||||
|
vadd.u64 d24,d24,d22
|
||||||
|
vst1.32 {d29},[r10,:64]! @ put aside smashed m[8*i+5]
|
||||||
|
vmlal.u32 q12,d28,d0[0]
|
||||||
|
vld1.64 {q11},[r6,:128]!
|
||||||
|
vmlal.u32 q13,d28,d0[1]
|
||||||
|
veor d8,d8,d8
|
||||||
|
vmlal.u32 q6,d28,d1[0]
|
||||||
|
vshl.i64 d29,d25,#16
|
||||||
|
vmlal.u32 q7,d28,d1[1]
|
||||||
|
vadd.u64 d29,d29,d24
|
||||||
|
vmlal.u32 q8,d28,d2[0]
|
||||||
|
vmul.u32 d29,d29,d30
|
||||||
|
vmlal.u32 q9,d28,d2[1]
|
||||||
|
vst1.32 {d28},[r10,:64]! @ put aside smashed b[8*i+6]
|
||||||
|
vmlal.u32 q10,d28,d3[0]
|
||||||
|
vzip.16 d29,d8
|
||||||
|
vmlal.u32 q11,d28,d3[1]
|
||||||
|
vld1.32 {d28[0]},[r2,:32]! @ *b++
|
||||||
|
vmlal.u32 q12,d29,d4[0]
|
||||||
|
veor d10,d10,d10
|
||||||
|
vmlal.u32 q13,d29,d4[1]
|
||||||
|
vzip.16 d28,d10
|
||||||
|
vmlal.u32 q6,d29,d5[0]
|
||||||
|
vshr.u64 d24,d24,#16
|
||||||
|
vmlal.u32 q7,d29,d5[1]
|
||||||
|
vmlal.u32 q8,d29,d6[0]
|
||||||
|
vadd.u64 d24,d24,d25
|
||||||
|
vmlal.u32 q9,d29,d6[1]
|
||||||
|
vshr.u64 d24,d24,#16
|
||||||
|
vmlal.u32 q10,d29,d7[0]
|
||||||
|
vmlal.u32 q11,d29,d7[1]
|
||||||
|
vadd.u64 d26,d26,d24
|
||||||
|
vst1.32 {d29},[r10,:64]! @ put aside smashed m[8*i+6]
|
||||||
|
vmlal.u32 q13,d28,d0[0]
|
||||||
|
vld1.64 {q12},[r6,:128]!
|
||||||
|
vmlal.u32 q6,d28,d0[1]
|
||||||
|
veor d8,d8,d8
|
||||||
|
vmlal.u32 q7,d28,d1[0]
|
||||||
|
vshl.i64 d29,d27,#16
|
||||||
|
vmlal.u32 q8,d28,d1[1]
|
||||||
|
vadd.u64 d29,d29,d26
|
||||||
|
vmlal.u32 q9,d28,d2[0]
|
||||||
|
vmul.u32 d29,d29,d30
|
||||||
|
vmlal.u32 q10,d28,d2[1]
|
||||||
|
vst1.32 {d28},[r10,:64]! @ put aside smashed b[8*i+7]
|
||||||
|
vmlal.u32 q11,d28,d3[0]
|
||||||
|
vzip.16 d29,d8
|
||||||
|
vmlal.u32 q12,d28,d3[1]
|
||||||
|
vld1.32 {d28},[sp,:64] @ pull smashed b[8*i+0]
|
||||||
|
vmlal.u32 q13,d29,d4[0]
|
||||||
|
vld1.32 {d0,d1,d2,d3},[r1]!
|
||||||
|
vmlal.u32 q6,d29,d4[1]
|
||||||
|
vmlal.u32 q7,d29,d5[0]
|
||||||
|
vshr.u64 d26,d26,#16
|
||||||
|
vmlal.u32 q8,d29,d5[1]
|
||||||
|
vmlal.u32 q9,d29,d6[0]
|
||||||
|
vadd.u64 d26,d26,d27
|
||||||
|
vmlal.u32 q10,d29,d6[1]
|
||||||
|
vshr.u64 d26,d26,#16
|
||||||
|
vmlal.u32 q11,d29,d7[0]
|
||||||
|
vmlal.u32 q12,d29,d7[1]
|
||||||
|
vadd.u64 d12,d12,d26
|
||||||
|
vst1.32 {d29},[r10,:64] @ put aside smashed m[8*i+7]
|
||||||
|
add r10,sp,#8 @ rewind
|
||||||
|
sub r8,r5,#8
|
||||||
|
b .LNEON_8n_inner
|
||||||
|
|
||||||
|
.align 4
|
||||||
|
.LNEON_8n_inner:
|
||||||
|
subs r8,r8,#8
|
||||||
vmlal.u32 q6,d28,d0[0]
|
vmlal.u32 q6,d28,d0[0]
|
||||||
vld1.64 {q9-q10}, [r6, :256]!
|
vld1.64 {q13},[r6,:128]
|
||||||
vmlal.u32 q7,d28,d0[1]
|
vmlal.u32 q7,d28,d0[1]
|
||||||
vst1.64 {q12-q13}, [r7,:256]!
|
vld1.32 {d29},[r10,:64]! @ pull smashed m[8*i+0]
|
||||||
vmlal.u32 q8,d28,d1[0]
|
vmlal.u32 q8,d28,d1[0]
|
||||||
vld1.64 {q11-q12}, [r6, :256]!
|
vld1.32 {d4,d5,d6,d7},[r3]!
|
||||||
vmlal.u32 q9,d28,d1[1]
|
vmlal.u32 q9,d28,d1[1]
|
||||||
vld1.32 {d4-d7}, [r3]!
|
it ne
|
||||||
|
addne r6,r6,#16 @ don't advance in last iteration
|
||||||
vmlal.u32 q10,d28,d2[0]
|
vmlal.u32 q10,d28,d2[0]
|
||||||
vld1.64 {q13}, [r6, :128]!
|
|
||||||
vmlal.u32 q11,d28,d2[1]
|
vmlal.u32 q11,d28,d2[1]
|
||||||
vmlal.u32 q12,d28,d3[0]
|
vmlal.u32 q12,d28,d3[0]
|
||||||
vmlal.u32 q13,d28,d3[1]
|
vmlal.u32 q13,d28,d3[1]
|
||||||
|
vld1.32 {d28},[r10,:64]! @ pull smashed b[8*i+1]
|
||||||
bne .LNEON_inner
|
|
||||||
|
|
||||||
vmlal.u32 q6,d29,d4[0]
|
vmlal.u32 q6,d29,d4[0]
|
||||||
add r6,sp,#16
|
|
||||||
vmlal.u32 q7,d29,d4[1]
|
vmlal.u32 q7,d29,d4[1]
|
||||||
sub r1,r1,r5,lsl#2 @ rewind r1
|
|
||||||
vmlal.u32 q8,d29,d5[0]
|
vmlal.u32 q8,d29,d5[0]
|
||||||
vld1.64 {q5}, [sp,:128]
|
|
||||||
vmlal.u32 q9,d29,d5[1]
|
vmlal.u32 q9,d29,d5[1]
|
||||||
subs r9,r9,#1
|
|
||||||
|
|
||||||
vmlal.u32 q10,d29,d6[0]
|
vmlal.u32 q10,d29,d6[0]
|
||||||
vst1.64 {q6-q7}, [r7,:256]!
|
|
||||||
vmlal.u32 q11,d29,d6[1]
|
vmlal.u32 q11,d29,d6[1]
|
||||||
vld1.64 {q6}, [r6, :128]!
|
|
||||||
vshr.u64 d10,d10,#16
|
|
||||||
vst1.64 {q8-q9}, [r7,:256]!
|
|
||||||
vmlal.u32 q12,d29,d7[0]
|
vmlal.u32 q12,d29,d7[0]
|
||||||
vld1.64 {q7-q8}, [r6, :256]!
|
|
||||||
vmlal.u32 q13,d29,d7[1]
|
vmlal.u32 q13,d29,d7[1]
|
||||||
|
vst1.64 {q6},[r7,:128]!
|
||||||
|
vmlal.u32 q7,d28,d0[0]
|
||||||
|
vld1.64 {q6},[r6,:128]
|
||||||
|
vmlal.u32 q8,d28,d0[1]
|
||||||
|
vld1.32 {d29},[r10,:64]! @ pull smashed m[8*i+1]
|
||||||
|
vmlal.u32 q9,d28,d1[0]
|
||||||
|
it ne
|
||||||
|
addne r6,r6,#16 @ don't advance in last iteration
|
||||||
|
vmlal.u32 q10,d28,d1[1]
|
||||||
|
vmlal.u32 q11,d28,d2[0]
|
||||||
|
vmlal.u32 q12,d28,d2[1]
|
||||||
|
vmlal.u32 q13,d28,d3[0]
|
||||||
|
vmlal.u32 q6,d28,d3[1]
|
||||||
|
vld1.32 {d28},[r10,:64]! @ pull smashed b[8*i+2]
|
||||||
|
vmlal.u32 q7,d29,d4[0]
|
||||||
|
vmlal.u32 q8,d29,d4[1]
|
||||||
|
vmlal.u32 q9,d29,d5[0]
|
||||||
|
vmlal.u32 q10,d29,d5[1]
|
||||||
|
vmlal.u32 q11,d29,d6[0]
|
||||||
|
vmlal.u32 q12,d29,d6[1]
|
||||||
|
vmlal.u32 q13,d29,d7[0]
|
||||||
|
vmlal.u32 q6,d29,d7[1]
|
||||||
|
vst1.64 {q7},[r7,:128]!
|
||||||
|
vmlal.u32 q8,d28,d0[0]
|
||||||
|
vld1.64 {q7},[r6,:128]
|
||||||
|
vmlal.u32 q9,d28,d0[1]
|
||||||
|
vld1.32 {d29},[r10,:64]! @ pull smashed m[8*i+2]
|
||||||
|
vmlal.u32 q10,d28,d1[0]
|
||||||
|
it ne
|
||||||
|
addne r6,r6,#16 @ don't advance in last iteration
|
||||||
|
vmlal.u32 q11,d28,d1[1]
|
||||||
|
vmlal.u32 q12,d28,d2[0]
|
||||||
|
vmlal.u32 q13,d28,d2[1]
|
||||||
|
vmlal.u32 q6,d28,d3[0]
|
||||||
|
vmlal.u32 q7,d28,d3[1]
|
||||||
|
vld1.32 {d28},[r10,:64]! @ pull smashed b[8*i+3]
|
||||||
|
vmlal.u32 q8,d29,d4[0]
|
||||||
|
vmlal.u32 q9,d29,d4[1]
|
||||||
|
vmlal.u32 q10,d29,d5[0]
|
||||||
|
vmlal.u32 q11,d29,d5[1]
|
||||||
|
vmlal.u32 q12,d29,d6[0]
|
||||||
|
vmlal.u32 q13,d29,d6[1]
|
||||||
|
vmlal.u32 q6,d29,d7[0]
|
||||||
|
vmlal.u32 q7,d29,d7[1]
|
||||||
|
vst1.64 {q8},[r7,:128]!
|
||||||
|
vmlal.u32 q9,d28,d0[0]
|
||||||
|
vld1.64 {q8},[r6,:128]
|
||||||
|
vmlal.u32 q10,d28,d0[1]
|
||||||
|
vld1.32 {d29},[r10,:64]! @ pull smashed m[8*i+3]
|
||||||
|
vmlal.u32 q11,d28,d1[0]
|
||||||
|
it ne
|
||||||
|
addne r6,r6,#16 @ don't advance in last iteration
|
||||||
|
vmlal.u32 q12,d28,d1[1]
|
||||||
|
vmlal.u32 q13,d28,d2[0]
|
||||||
|
vmlal.u32 q6,d28,d2[1]
|
||||||
|
vmlal.u32 q7,d28,d3[0]
|
||||||
|
vmlal.u32 q8,d28,d3[1]
|
||||||
|
vld1.32 {d28},[r10,:64]! @ pull smashed b[8*i+4]
|
||||||
|
vmlal.u32 q9,d29,d4[0]
|
||||||
|
vmlal.u32 q10,d29,d4[1]
|
||||||
|
vmlal.u32 q11,d29,d5[0]
|
||||||
|
vmlal.u32 q12,d29,d5[1]
|
||||||
|
vmlal.u32 q13,d29,d6[0]
|
||||||
|
vmlal.u32 q6,d29,d6[1]
|
||||||
|
vmlal.u32 q7,d29,d7[0]
|
||||||
|
vmlal.u32 q8,d29,d7[1]
|
||||||
|
vst1.64 {q9},[r7,:128]!
|
||||||
|
vmlal.u32 q10,d28,d0[0]
|
||||||
|
vld1.64 {q9},[r6,:128]
|
||||||
|
vmlal.u32 q11,d28,d0[1]
|
||||||
|
vld1.32 {d29},[r10,:64]! @ pull smashed m[8*i+4]
|
||||||
|
vmlal.u32 q12,d28,d1[0]
|
||||||
|
it ne
|
||||||
|
addne r6,r6,#16 @ don't advance in last iteration
|
||||||
|
vmlal.u32 q13,d28,d1[1]
|
||||||
|
vmlal.u32 q6,d28,d2[0]
|
||||||
|
vmlal.u32 q7,d28,d2[1]
|
||||||
|
vmlal.u32 q8,d28,d3[0]
|
||||||
|
vmlal.u32 q9,d28,d3[1]
|
||||||
|
vld1.32 {d28},[r10,:64]! @ pull smashed b[8*i+5]
|
||||||
|
vmlal.u32 q10,d29,d4[0]
|
||||||
|
vmlal.u32 q11,d29,d4[1]
|
||||||
|
vmlal.u32 q12,d29,d5[0]
|
||||||
|
vmlal.u32 q13,d29,d5[1]
|
||||||
|
vmlal.u32 q6,d29,d6[0]
|
||||||
|
vmlal.u32 q7,d29,d6[1]
|
||||||
|
vmlal.u32 q8,d29,d7[0]
|
||||||
|
vmlal.u32 q9,d29,d7[1]
|
||||||
|
vst1.64 {q10},[r7,:128]!
|
||||||
|
vmlal.u32 q11,d28,d0[0]
|
||||||
|
vld1.64 {q10},[r6,:128]
|
||||||
|
vmlal.u32 q12,d28,d0[1]
|
||||||
|
vld1.32 {d29},[r10,:64]! @ pull smashed m[8*i+5]
|
||||||
|
vmlal.u32 q13,d28,d1[0]
|
||||||
|
it ne
|
||||||
|
addne r6,r6,#16 @ don't advance in last iteration
|
||||||
|
vmlal.u32 q6,d28,d1[1]
|
||||||
|
vmlal.u32 q7,d28,d2[0]
|
||||||
|
vmlal.u32 q8,d28,d2[1]
|
||||||
|
vmlal.u32 q9,d28,d3[0]
|
||||||
|
vmlal.u32 q10,d28,d3[1]
|
||||||
|
vld1.32 {d28},[r10,:64]! @ pull smashed b[8*i+6]
|
||||||
|
vmlal.u32 q11,d29,d4[0]
|
||||||
|
vmlal.u32 q12,d29,d4[1]
|
||||||
|
vmlal.u32 q13,d29,d5[0]
|
||||||
|
vmlal.u32 q6,d29,d5[1]
|
||||||
|
vmlal.u32 q7,d29,d6[0]
|
||||||
|
vmlal.u32 q8,d29,d6[1]
|
||||||
|
vmlal.u32 q9,d29,d7[0]
|
||||||
|
vmlal.u32 q10,d29,d7[1]
|
||||||
|
vst1.64 {q11},[r7,:128]!
|
||||||
|
vmlal.u32 q12,d28,d0[0]
|
||||||
|
vld1.64 {q11},[r6,:128]
|
||||||
|
vmlal.u32 q13,d28,d0[1]
|
||||||
|
vld1.32 {d29},[r10,:64]! @ pull smashed m[8*i+6]
|
||||||
|
vmlal.u32 q6,d28,d1[0]
|
||||||
|
it ne
|
||||||
|
addne r6,r6,#16 @ don't advance in last iteration
|
||||||
|
vmlal.u32 q7,d28,d1[1]
|
||||||
|
vmlal.u32 q8,d28,d2[0]
|
||||||
|
vmlal.u32 q9,d28,d2[1]
|
||||||
|
vmlal.u32 q10,d28,d3[0]
|
||||||
|
vmlal.u32 q11,d28,d3[1]
|
||||||
|
vld1.32 {d28},[r10,:64]! @ pull smashed b[8*i+7]
|
||||||
|
vmlal.u32 q12,d29,d4[0]
|
||||||
|
vmlal.u32 q13,d29,d4[1]
|
||||||
|
vmlal.u32 q6,d29,d5[0]
|
||||||
|
vmlal.u32 q7,d29,d5[1]
|
||||||
|
vmlal.u32 q8,d29,d6[0]
|
||||||
|
vmlal.u32 q9,d29,d6[1]
|
||||||
|
vmlal.u32 q10,d29,d7[0]
|
||||||
|
vmlal.u32 q11,d29,d7[1]
|
||||||
|
vst1.64 {q12},[r7,:128]!
|
||||||
|
vmlal.u32 q13,d28,d0[0]
|
||||||
|
vld1.64 {q12},[r6,:128]
|
||||||
|
vmlal.u32 q6,d28,d0[1]
|
||||||
|
vld1.32 {d29},[r10,:64]! @ pull smashed m[8*i+7]
|
||||||
|
vmlal.u32 q7,d28,d1[0]
|
||||||
|
it ne
|
||||||
|
addne r6,r6,#16 @ don't advance in last iteration
|
||||||
|
vmlal.u32 q8,d28,d1[1]
|
||||||
|
vmlal.u32 q9,d28,d2[0]
|
||||||
|
vmlal.u32 q10,d28,d2[1]
|
||||||
|
vmlal.u32 q11,d28,d3[0]
|
||||||
|
vmlal.u32 q12,d28,d3[1]
|
||||||
|
it eq
|
||||||
|
subeq r1,r1,r5,lsl#2 @ rewind
|
||||||
|
vmlal.u32 q13,d29,d4[0]
|
||||||
|
vld1.32 {d28},[sp,:64] @ pull smashed b[8*i+0]
|
||||||
|
vmlal.u32 q6,d29,d4[1]
|
||||||
|
vld1.32 {d0,d1,d2,d3},[r1]!
|
||||||
|
vmlal.u32 q7,d29,d5[0]
|
||||||
|
add r10,sp,#8 @ rewind
|
||||||
|
vmlal.u32 q8,d29,d5[1]
|
||||||
|
vmlal.u32 q9,d29,d6[0]
|
||||||
|
vmlal.u32 q10,d29,d6[1]
|
||||||
|
vmlal.u32 q11,d29,d7[0]
|
||||||
|
vst1.64 {q13},[r7,:128]!
|
||||||
|
vmlal.u32 q12,d29,d7[1]
|
||||||
|
|
||||||
vst1.64 {q10-q11}, [r7,:256]!
|
bne .LNEON_8n_inner
|
||||||
vadd.u64 d10,d10,d11
|
add r6,sp,#128
|
||||||
vst1.64 {q12-q13}, [r7,:256]!
|
vst1.64 {q6,q7},[r7,:256]!
|
||||||
vshr.u64 d10,d10,#16
|
veor q2,q2,q2 @ d4-d5
|
||||||
|
vst1.64 {q8,q9},[r7,:256]!
|
||||||
|
veor q3,q3,q3 @ d6-d7
|
||||||
|
vst1.64 {q10,q11},[r7,:256]!
|
||||||
|
vst1.64 {q12},[r7,:128]
|
||||||
|
|
||||||
bne .LNEON_outer
|
subs r9,r9,#8
|
||||||
|
vld1.64 {q6,q7},[r6,:256]!
|
||||||
|
vld1.64 {q8,q9},[r6,:256]!
|
||||||
|
vld1.64 {q10,q11},[r6,:256]!
|
||||||
|
vld1.64 {q12,q13},[r6,:256]!
|
||||||
|
|
||||||
mov r7,sp
|
itt ne
|
||||||
mov r8,r5
|
subne r3,r3,r5,lsl#2 @ rewind
|
||||||
|
bne .LNEON_8n_outer
|
||||||
|
|
||||||
.LNEON_tail:
|
add r7,sp,#128
|
||||||
vadd.u64 d12,d12,d10
|
vst1.64 {q2,q3}, [sp,:256]! @ start wiping stack frame
|
||||||
vld1.64 {q9-q10}, [r6, :256]!
|
|
||||||
vshr.u64 d10,d12,#16
|
vshr.u64 d10,d12,#16
|
||||||
|
vst1.64 {q2,q3},[sp,:256]!
|
||||||
vadd.u64 d13,d13,d10
|
vadd.u64 d13,d13,d10
|
||||||
vld1.64 {q11-q12}, [r6, :256]!
|
vst1.64 {q2,q3}, [sp,:256]!
|
||||||
vshr.u64 d10,d13,#16
|
vshr.u64 d10,d13,#16
|
||||||
vld1.64 {q13}, [r6, :128]!
|
vst1.64 {q2,q3}, [sp,:256]!
|
||||||
vzip.16 d12,d13
|
vzip.16 d12,d13
|
||||||
|
|
||||||
.LNEON_tail2:
|
mov r8,r5
|
||||||
|
b .LNEON_tail_entry
|
||||||
|
|
||||||
|
.align 4
|
||||||
|
.LNEON_tail:
|
||||||
|
vadd.u64 d12,d12,d10
|
||||||
|
vshr.u64 d10,d12,#16
|
||||||
|
vld1.64 {q8,q9}, [r6, :256]!
|
||||||
|
vadd.u64 d13,d13,d10
|
||||||
|
vld1.64 {q10,q11}, [r6, :256]!
|
||||||
|
vshr.u64 d10,d13,#16
|
||||||
|
vld1.64 {q12,q13}, [r6, :256]!
|
||||||
|
vzip.16 d12,d13
|
||||||
|
|
||||||
|
.LNEON_tail_entry:
|
||||||
vadd.u64 d14,d14,d10
|
vadd.u64 d14,d14,d10
|
||||||
vst1.32 {d12[0]}, [r7, :32]!
|
vst1.32 {d12[0]}, [r7, :32]!
|
||||||
vshr.u64 d10,d14,#16
|
vshr.u64 d10,d14,#16
|
||||||
vadd.u64 d15,d15,d10
|
vadd.u64 d15,d15,d10
|
||||||
vshr.u64 d10,d15,#16
|
vshr.u64 d10,d15,#16
|
||||||
vzip.16 d14,d15
|
vzip.16 d14,d15
|
||||||
|
|
||||||
vadd.u64 d16,d16,d10
|
vadd.u64 d16,d16,d10
|
||||||
vst1.32 {d14[0]}, [r7, :32]!
|
vst1.32 {d14[0]}, [r7, :32]!
|
||||||
vshr.u64 d10,d16,#16
|
vshr.u64 d10,d16,#16
|
||||||
vadd.u64 d17,d17,d10
|
vadd.u64 d17,d17,d10
|
||||||
vshr.u64 d10,d17,#16
|
vshr.u64 d10,d17,#16
|
||||||
vzip.16 d16,d17
|
vzip.16 d16,d17
|
||||||
|
|
||||||
vadd.u64 d18,d18,d10
|
vadd.u64 d18,d18,d10
|
||||||
vst1.32 {d16[0]}, [r7, :32]!
|
vst1.32 {d16[0]}, [r7, :32]!
|
||||||
vshr.u64 d10,d18,#16
|
vshr.u64 d10,d18,#16
|
||||||
vadd.u64 d19,d19,d10
|
vadd.u64 d19,d19,d10
|
||||||
vshr.u64 d10,d19,#16
|
vshr.u64 d10,d19,#16
|
||||||
vzip.16 d18,d19
|
vzip.16 d18,d19
|
||||||
|
|
||||||
vadd.u64 d20,d20,d10
|
vadd.u64 d20,d20,d10
|
||||||
vst1.32 {d18[0]}, [r7, :32]!
|
vst1.32 {d18[0]}, [r7, :32]!
|
||||||
vshr.u64 d10,d20,#16
|
vshr.u64 d10,d20,#16
|
||||||
vadd.u64 d21,d21,d10
|
vadd.u64 d21,d21,d10
|
||||||
vshr.u64 d10,d21,#16
|
vshr.u64 d10,d21,#16
|
||||||
vzip.16 d20,d21
|
vzip.16 d20,d21
|
||||||
|
|
||||||
vadd.u64 d22,d22,d10
|
vadd.u64 d22,d22,d10
|
||||||
vst1.32 {d20[0]}, [r7, :32]!
|
vst1.32 {d20[0]}, [r7, :32]!
|
||||||
vshr.u64 d10,d22,#16
|
vshr.u64 d10,d22,#16
|
||||||
vadd.u64 d23,d23,d10
|
vadd.u64 d23,d23,d10
|
||||||
vshr.u64 d10,d23,#16
|
vshr.u64 d10,d23,#16
|
||||||
vzip.16 d22,d23
|
vzip.16 d22,d23
|
||||||
|
|
||||||
vadd.u64 d24,d24,d10
|
vadd.u64 d24,d24,d10
|
||||||
vst1.32 {d22[0]}, [r7, :32]!
|
vst1.32 {d22[0]}, [r7, :32]!
|
||||||
vshr.u64 d10,d24,#16
|
vshr.u64 d10,d24,#16
|
||||||
vadd.u64 d25,d25,d10
|
vadd.u64 d25,d25,d10
|
||||||
vld1.64 {q6}, [r6, :128]!
|
|
||||||
vshr.u64 d10,d25,#16
|
vshr.u64 d10,d25,#16
|
||||||
vzip.16 d24,d25
|
vzip.16 d24,d25
|
||||||
|
|
||||||
vadd.u64 d26,d26,d10
|
vadd.u64 d26,d26,d10
|
||||||
vst1.32 {d24[0]}, [r7, :32]!
|
vst1.32 {d24[0]}, [r7, :32]!
|
||||||
vshr.u64 d10,d26,#16
|
vshr.u64 d10,d26,#16
|
||||||
vadd.u64 d27,d27,d10
|
vadd.u64 d27,d27,d10
|
||||||
vld1.64 {q7-q8}, [r6, :256]!
|
|
||||||
vshr.u64 d10,d27,#16
|
vshr.u64 d10,d27,#16
|
||||||
vzip.16 d26,d27
|
vzip.16 d26,d27
|
||||||
|
vld1.64 {q6,q7}, [r6, :256]!
|
||||||
subs r8,r8,#8
|
subs r8,r8,#8
|
||||||
vst1.32 {d26[0]}, [r7, :32]!
|
vst1.32 {d26[0]}, [r7, :32]!
|
||||||
|
|
||||||
bne .LNEON_tail
|
bne .LNEON_tail
|
||||||
|
|
||||||
vst1.32 {d10[0]}, [r7, :32] @ top-most bit
|
vst1.32 {d10[0]}, [r7, :32] @ top-most bit
|
||||||
@ -528,19 +892,20 @@ bn_mul8x_mont_neon:
|
|||||||
add r2,sp,r5,lsl#2
|
add r2,sp,r5,lsl#2
|
||||||
|
|
||||||
.LNEON_sub:
|
.LNEON_sub:
|
||||||
ldmia r1!, {r4-r7}
|
ldmia r1!, {r4,r5,r6,r7}
|
||||||
ldmia r3!, {r8-r11}
|
ldmia r3!, {r8,r9,r10,r11}
|
||||||
sbcs r8, r4,r8
|
sbcs r8, r4,r8
|
||||||
sbcs r9, r5,r9
|
sbcs r9, r5,r9
|
||||||
sbcs r10,r6,r10
|
sbcs r10,r6,r10
|
||||||
sbcs r11,r7,r11
|
sbcs r11,r7,r11
|
||||||
teq r1,r2 @ preserves carry
|
teq r1,r2 @ preserves carry
|
||||||
stmia r0!, {r8-r11}
|
stmia r0!, {r8,r9,r10,r11}
|
||||||
bne .LNEON_sub
|
bne .LNEON_sub
|
||||||
|
|
||||||
ldr r10, [r1] @ load top-most bit
|
ldr r10, [r1] @ load top-most bit
|
||||||
|
mov r11,sp
|
||||||
veor q0,q0,q0
|
veor q0,q0,q0
|
||||||
sub r11,r2,sp @ this is num*4
|
sub r11,r2,r11 @ this is num*4
|
||||||
veor q1,q1,q1
|
veor q1,q1,q1
|
||||||
mov r1,sp
|
mov r1,sp
|
||||||
sub r0,r0,r11 @ rewind r0
|
sub r0,r0,r11 @ rewind r0
|
||||||
@ -548,35 +913,42 @@ bn_mul8x_mont_neon:
|
|||||||
sbcs r10,r10,#0 @ result is carry flag
|
sbcs r10,r10,#0 @ result is carry flag
|
||||||
|
|
||||||
.LNEON_copy_n_zap:
|
.LNEON_copy_n_zap:
|
||||||
ldmia r1!, {r4-r7}
|
ldmia r1!, {r4,r5,r6,r7}
|
||||||
ldmia r0, {r8-r11}
|
ldmia r0, {r8,r9,r10,r11}
|
||||||
|
it cc
|
||||||
movcc r8, r4
|
movcc r8, r4
|
||||||
vst1.64 {q0-q1}, [r3,:256]! @ wipe
|
vst1.64 {q0,q1}, [r3,:256]! @ wipe
|
||||||
|
itt cc
|
||||||
movcc r9, r5
|
movcc r9, r5
|
||||||
movcc r10,r6
|
movcc r10,r6
|
||||||
vst1.64 {q0-q1}, [r3,:256]! @ wipe
|
vst1.64 {q0,q1}, [r3,:256]! @ wipe
|
||||||
|
it cc
|
||||||
movcc r11,r7
|
movcc r11,r7
|
||||||
ldmia r1, {r4-r7}
|
ldmia r1, {r4,r5,r6,r7}
|
||||||
stmia r0!, {r8-r11}
|
stmia r0!, {r8,r9,r10,r11}
|
||||||
sub r1,r1,#16
|
sub r1,r1,#16
|
||||||
ldmia r0, {r8-r11}
|
ldmia r0, {r8,r9,r10,r11}
|
||||||
|
it cc
|
||||||
movcc r8, r4
|
movcc r8, r4
|
||||||
vst1.64 {q0-q1}, [r1,:256]! @ wipe
|
vst1.64 {q0,q1}, [r1,:256]! @ wipe
|
||||||
|
itt cc
|
||||||
movcc r9, r5
|
movcc r9, r5
|
||||||
movcc r10,r6
|
movcc r10,r6
|
||||||
vst1.64 {q0-q1}, [r3,:256]! @ wipe
|
vst1.64 {q0,q1}, [r3,:256]! @ wipe
|
||||||
|
it cc
|
||||||
movcc r11,r7
|
movcc r11,r7
|
||||||
teq r1,r2 @ preserves carry
|
teq r1,r2 @ preserves carry
|
||||||
stmia r0!, {r8-r11}
|
stmia r0!, {r8,r9,r10,r11}
|
||||||
bne .LNEON_copy_n_zap
|
bne .LNEON_copy_n_zap
|
||||||
|
|
||||||
sub sp,ip,#96
|
mov sp,ip
|
||||||
vldmia sp!,{d8-d15}
|
vldmia sp!,{d8,d9,d10,d11,d12,d13,d14,d15}
|
||||||
ldmia sp!,{r4-r11}
|
ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11}
|
||||||
bx lr @ .word 0xe12fff1e
|
bx lr @ bx lr
|
||||||
.size bn_mul8x_mont_neon,.-bn_mul8x_mont_neon
|
.size bn_mul8x_mont_neon,.-bn_mul8x_mont_neon
|
||||||
#endif
|
#endif
|
||||||
.asciz "Montgomery multiplication for ARMv4/NEON, CRYPTOGAMS by <appro@openssl.org>"
|
.byte 77,111,110,116,103,111,109,101,114,121,32,109,117,108,116,105,112,108,105,99,97,116,105,111,110,32,102,111,114,32,65,82,77,118,52,47,78,69,79,78,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
|
||||||
|
.align 2
|
||||||
.align 2
|
.align 2
|
||||||
#if __ARM_MAX_ARCH__>=7
|
#if __ARM_MAX_ARCH__>=7
|
||||||
.comm OPENSSL_armcap_P,4,4
|
.comm OPENSSL_armcap_P,4,4
|
||||||
|
@ -1,5 +1,12 @@
|
|||||||
/* $FreeBSD$ */
|
/* $FreeBSD$ */
|
||||||
/* Do not modify. This file is auto-generated from bsaes-armv7.pl. */
|
/* Do not modify. This file is auto-generated from bsaes-armv7.pl. */
|
||||||
|
@ Copyright 2012-2018 The OpenSSL Project Authors. All Rights Reserved.
|
||||||
|
@
|
||||||
|
@ Licensed under the OpenSSL license (the "License"). You may not use
|
||||||
|
@ this file except in compliance with the License. You can obtain a copy
|
||||||
|
@ in the file LICENSE in the source distribution or at
|
||||||
|
@ https://www.openssl.org/source/license.html
|
||||||
|
|
||||||
|
|
||||||
@ ====================================================================
|
@ ====================================================================
|
||||||
@ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
|
@ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
|
||||||
@ -8,8 +15,7 @@
|
|||||||
@ details see http://www.openssl.org/~appro/cryptogams/.
|
@ details see http://www.openssl.org/~appro/cryptogams/.
|
||||||
@
|
@
|
||||||
@ Specific modes and adaptation for Linux kernel by Ard Biesheuvel
|
@ Specific modes and adaptation for Linux kernel by Ard Biesheuvel
|
||||||
@ <ard.biesheuvel@linaro.org>. Permission to use under GPL terms is
|
@ of Linaro. Permission to use under GPL terms is granted.
|
||||||
@ granted.
|
|
||||||
@ ====================================================================
|
@ ====================================================================
|
||||||
|
|
||||||
@ Bit-sliced AES for ARM NEON
|
@ Bit-sliced AES for ARM NEON
|
||||||
@ -43,10 +49,7 @@
|
|||||||
@ <appro@openssl.org>
|
@ <appro@openssl.org>
|
||||||
|
|
||||||
@ April-August 2013
|
@ April-August 2013
|
||||||
@
|
@ Add CBC, CTR and XTS subroutines and adapt for kernel use; courtesy of Ard.
|
||||||
@ Add CBC, CTR and XTS subroutines, adapt for kernel use.
|
|
||||||
@
|
|
||||||
@ <ard.biesheuvel@linaro.org>
|
|
||||||
|
|
||||||
#ifndef __KERNEL__
|
#ifndef __KERNEL__
|
||||||
# include "arm_arch.h"
|
# include "arm_arch.h"
|
||||||
@ -61,7 +64,7 @@
|
|||||||
# define BSAES_ASM_EXTENDED_KEY
|
# define BSAES_ASM_EXTENDED_KEY
|
||||||
# define XTS_CHAIN_TWEAK
|
# define XTS_CHAIN_TWEAK
|
||||||
# define __ARM_ARCH__ __LINUX_ARM_ARCH__
|
# define __ARM_ARCH__ __LINUX_ARM_ARCH__
|
||||||
# define __ARM_MAX_ARCH__ __LINUX_ARM_ARCH__
|
# define __ARM_MAX_ARCH__ 7
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef __thumb__
|
#ifdef __thumb__
|
||||||
@ -74,10 +77,11 @@
|
|||||||
|
|
||||||
.text
|
.text
|
||||||
.syntax unified @ ARMv7-capable assembler is expected to handle this
|
.syntax unified @ ARMv7-capable assembler is expected to handle this
|
||||||
#ifdef __thumb2__
|
#if defined(__thumb2__) && !defined(__APPLE__)
|
||||||
.thumb
|
.thumb
|
||||||
#else
|
#else
|
||||||
.code 32
|
.code 32
|
||||||
|
# undef __thumb2__
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
.type _bsaes_decrypt8,%function
|
.type _bsaes_decrypt8,%function
|
||||||
@ -85,7 +89,11 @@
|
|||||||
_bsaes_decrypt8:
|
_bsaes_decrypt8:
|
||||||
adr r6,.
|
adr r6,.
|
||||||
vldmia r4!, {q9} @ round 0 key
|
vldmia r4!, {q9} @ round 0 key
|
||||||
|
#if defined(__thumb2__) || defined(__APPLE__)
|
||||||
|
adr r6,.LM0ISR
|
||||||
|
#else
|
||||||
add r6,r6,#.LM0ISR-_bsaes_decrypt8
|
add r6,r6,#.LM0ISR-_bsaes_decrypt8
|
||||||
|
#endif
|
||||||
|
|
||||||
vldmia r6!, {q8} @ .LM0ISR
|
vldmia r6!, {q8} @ .LM0ISR
|
||||||
veor q10, q0, q9 @ xor with round0 key
|
veor q10, q0, q9 @ xor with round0 key
|
||||||
@ -191,7 +199,7 @@ _bsaes_decrypt8:
|
|||||||
b .Ldec_sbox
|
b .Ldec_sbox
|
||||||
.align 4
|
.align 4
|
||||||
.Ldec_loop:
|
.Ldec_loop:
|
||||||
vldmia r4!, {q8-q11}
|
vldmia r4!, {q8,q9,q10,q11}
|
||||||
veor q8, q8, q0
|
veor q8, q8, q0
|
||||||
veor q9, q9, q1
|
veor q9, q9, q1
|
||||||
vtbl.8 d0, {q8}, d24
|
vtbl.8 d0, {q8}, d24
|
||||||
@ -562,7 +570,8 @@ _bsaes_const:
|
|||||||
.quad 0x02060a0e03070b0f, 0x0004080c0105090d
|
.quad 0x02060a0e03070b0f, 0x0004080c0105090d
|
||||||
.LREVM0SR:
|
.LREVM0SR:
|
||||||
.quad 0x090d01050c000408, 0x03070b0f060a0e02
|
.quad 0x090d01050c000408, 0x03070b0f060a0e02
|
||||||
.asciz "Bit-sliced AES for NEON, CRYPTOGAMS by <appro@openssl.org>"
|
.byte 66,105,116,45,115,108,105,99,101,100,32,65,69,83,32,102,111,114,32,78,69,79,78,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
|
||||||
|
.align 2
|
||||||
.align 6
|
.align 6
|
||||||
.size _bsaes_const,.-_bsaes_const
|
.size _bsaes_const,.-_bsaes_const
|
||||||
|
|
||||||
@ -571,7 +580,11 @@ _bsaes_const:
|
|||||||
_bsaes_encrypt8:
|
_bsaes_encrypt8:
|
||||||
adr r6,.
|
adr r6,.
|
||||||
vldmia r4!, {q9} @ round 0 key
|
vldmia r4!, {q9} @ round 0 key
|
||||||
|
#if defined(__thumb2__) || defined(__APPLE__)
|
||||||
|
adr r6,.LM0SR
|
||||||
|
#else
|
||||||
sub r6,r6,#_bsaes_encrypt8-.LM0SR
|
sub r6,r6,#_bsaes_encrypt8-.LM0SR
|
||||||
|
#endif
|
||||||
|
|
||||||
vldmia r6!, {q8} @ .LM0SR
|
vldmia r6!, {q8} @ .LM0SR
|
||||||
_bsaes_encrypt8_alt:
|
_bsaes_encrypt8_alt:
|
||||||
@ -679,7 +692,7 @@ _bsaes_encrypt8_bitslice:
|
|||||||
b .Lenc_sbox
|
b .Lenc_sbox
|
||||||
.align 4
|
.align 4
|
||||||
.Lenc_loop:
|
.Lenc_loop:
|
||||||
vldmia r4!, {q8-q11}
|
vldmia r4!, {q8,q9,q10,q11}
|
||||||
veor q8, q8, q0
|
veor q8, q8, q0
|
||||||
veor q9, q9, q1
|
veor q9, q9, q1
|
||||||
vtbl.8 d0, {q8}, d24
|
vtbl.8 d0, {q8}, d24
|
||||||
@ -1002,7 +1015,11 @@ _bsaes_encrypt8_bitslice:
|
|||||||
_bsaes_key_convert:
|
_bsaes_key_convert:
|
||||||
adr r6,.
|
adr r6,.
|
||||||
vld1.8 {q7}, [r4]! @ load round 0 key
|
vld1.8 {q7}, [r4]! @ load round 0 key
|
||||||
|
#if defined(__thumb2__) || defined(__APPLE__)
|
||||||
|
adr r6,.LM0
|
||||||
|
#else
|
||||||
sub r6,r6,#_bsaes_key_convert-.LM0
|
sub r6,r6,#_bsaes_key_convert-.LM0
|
||||||
|
#endif
|
||||||
vld1.8 {q15}, [r4]! @ load round 1 key
|
vld1.8 {q15}, [r4]! @ load round 1 key
|
||||||
|
|
||||||
vmov.i8 q8, #0x01 @ bit masks
|
vmov.i8 q8, #0x01 @ bit masks
|
||||||
@ -1045,17 +1062,17 @@ _bsaes_key_convert:
|
|||||||
vrev32.8 q15, q15
|
vrev32.8 q15, q15
|
||||||
#endif
|
#endif
|
||||||
subs r5,r5,#1
|
subs r5,r5,#1
|
||||||
vstmia r12!,{q0-q7} @ write bit-sliced round key
|
vstmia r12!,{q0,q1,q2,q3,q4,q5,q6,q7} @ write bit-sliced round key
|
||||||
bne .Lkey_loop
|
bne .Lkey_loop
|
||||||
|
|
||||||
vmov.i8 q7,#0x63 @ compose .L63
|
vmov.i8 q7,#0x63 @ compose .L63
|
||||||
@ don't save last round key
|
@ don't save last round key
|
||||||
bx lr
|
bx lr
|
||||||
.size _bsaes_key_convert,.-_bsaes_key_convert
|
.size _bsaes_key_convert,.-_bsaes_key_convert
|
||||||
.extern AES_cbc_encrypt
|
|
||||||
.extern AES_decrypt
|
|
||||||
|
|
||||||
.global bsaes_cbc_encrypt
|
|
||||||
|
|
||||||
|
.globl bsaes_cbc_encrypt
|
||||||
.type bsaes_cbc_encrypt,%function
|
.type bsaes_cbc_encrypt,%function
|
||||||
.align 5
|
.align 5
|
||||||
bsaes_cbc_encrypt:
|
bsaes_cbc_encrypt:
|
||||||
@ -1073,7 +1090,7 @@ bsaes_cbc_encrypt:
|
|||||||
@ it is up to the caller to make sure we are called with enc == 0
|
@ it is up to the caller to make sure we are called with enc == 0
|
||||||
|
|
||||||
mov ip, sp
|
mov ip, sp
|
||||||
stmdb sp!, {r4-r10, lr}
|
stmdb sp!, {r4,r5,r6,r7,r8,r9,r10, lr}
|
||||||
VFP_ABI_PUSH
|
VFP_ABI_PUSH
|
||||||
ldr r8, [ip] @ IV is 1st arg on the stack
|
ldr r8, [ip] @ IV is 1st arg on the stack
|
||||||
mov r2, r2, lsr#4 @ len in 16 byte blocks
|
mov r2, r2, lsr#4 @ len in 16 byte blocks
|
||||||
@ -1113,7 +1130,7 @@ bsaes_cbc_encrypt:
|
|||||||
vstmia r4, {q7}
|
vstmia r4, {q7}
|
||||||
|
|
||||||
.align 2
|
.align 2
|
||||||
0:
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
vld1.8 {q15}, [r8] @ load IV
|
vld1.8 {q15}, [r8] @ load IV
|
||||||
@ -1124,33 +1141,33 @@ bsaes_cbc_encrypt:
|
|||||||
subs r2, r2, #0x8
|
subs r2, r2, #0x8
|
||||||
bmi .Lcbc_dec_loop_finish
|
bmi .Lcbc_dec_loop_finish
|
||||||
|
|
||||||
vld1.8 {q0-q1}, [r0]! @ load input
|
vld1.8 {q0,q1}, [r0]! @ load input
|
||||||
vld1.8 {q2-q3}, [r0]!
|
vld1.8 {q2,q3}, [r0]!
|
||||||
#ifndef BSAES_ASM_EXTENDED_KEY
|
#ifndef BSAES_ASM_EXTENDED_KEY
|
||||||
mov r4, sp @ pass the key
|
mov r4, sp @ pass the key
|
||||||
#else
|
#else
|
||||||
add r4, r3, #248
|
add r4, r3, #248
|
||||||
#endif
|
#endif
|
||||||
vld1.8 {q4-q5}, [r0]!
|
vld1.8 {q4,q5}, [r0]!
|
||||||
mov r5, r10
|
mov r5, r10
|
||||||
vld1.8 {q6-q7}, [r0]
|
vld1.8 {q6,q7}, [r0]
|
||||||
sub r0, r0, #0x60
|
sub r0, r0, #0x60
|
||||||
vstmia r9, {q15} @ put aside IV
|
vstmia r9, {q15} @ put aside IV
|
||||||
|
|
||||||
bl _bsaes_decrypt8
|
bl _bsaes_decrypt8
|
||||||
|
|
||||||
vldmia r9, {q14} @ reload IV
|
vldmia r9, {q14} @ reload IV
|
||||||
vld1.8 {q8-q9}, [r0]! @ reload input
|
vld1.8 {q8,q9}, [r0]! @ reload input
|
||||||
veor q0, q0, q14 @ ^= IV
|
veor q0, q0, q14 @ ^= IV
|
||||||
vld1.8 {q10-q11}, [r0]!
|
vld1.8 {q10,q11}, [r0]!
|
||||||
veor q1, q1, q8
|
veor q1, q1, q8
|
||||||
veor q6, q6, q9
|
veor q6, q6, q9
|
||||||
vld1.8 {q12-q13}, [r0]!
|
vld1.8 {q12,q13}, [r0]!
|
||||||
veor q4, q4, q10
|
veor q4, q4, q10
|
||||||
veor q2, q2, q11
|
veor q2, q2, q11
|
||||||
vld1.8 {q14-q15}, [r0]!
|
vld1.8 {q14,q15}, [r0]!
|
||||||
veor q7, q7, q12
|
veor q7, q7, q12
|
||||||
vst1.8 {q0-q1}, [r1]! @ write output
|
vst1.8 {q0,q1}, [r1]! @ write output
|
||||||
veor q3, q3, q13
|
veor q3, q3, q13
|
||||||
vst1.8 {q6}, [r1]!
|
vst1.8 {q6}, [r1]!
|
||||||
veor q5, q5, q14
|
veor q5, q5, q14
|
||||||
@ -1194,17 +1211,17 @@ bsaes_cbc_encrypt:
|
|||||||
bl _bsaes_decrypt8
|
bl _bsaes_decrypt8
|
||||||
|
|
||||||
vldmia r9, {q14} @ reload IV
|
vldmia r9, {q14} @ reload IV
|
||||||
vld1.8 {q8-q9}, [r0]! @ reload input
|
vld1.8 {q8,q9}, [r0]! @ reload input
|
||||||
veor q0, q0, q14 @ ^= IV
|
veor q0, q0, q14 @ ^= IV
|
||||||
vld1.8 {q10-q11}, [r0]!
|
vld1.8 {q10,q11}, [r0]!
|
||||||
veor q1, q1, q8
|
veor q1, q1, q8
|
||||||
veor q6, q6, q9
|
veor q6, q6, q9
|
||||||
vld1.8 {q12-q13}, [r0]!
|
vld1.8 {q12,q13}, [r0]!
|
||||||
veor q4, q4, q10
|
veor q4, q4, q10
|
||||||
veor q2, q2, q11
|
veor q2, q2, q11
|
||||||
vld1.8 {q15}, [r0]!
|
vld1.8 {q15}, [r0]!
|
||||||
veor q7, q7, q12
|
veor q7, q7, q12
|
||||||
vst1.8 {q0-q1}, [r1]! @ write output
|
vst1.8 {q0,q1}, [r1]! @ write output
|
||||||
veor q3, q3, q13
|
veor q3, q3, q13
|
||||||
vst1.8 {q6}, [r1]!
|
vst1.8 {q6}, [r1]!
|
||||||
vst1.8 {q4}, [r1]!
|
vst1.8 {q4}, [r1]!
|
||||||
@ -1217,9 +1234,9 @@ bsaes_cbc_encrypt:
|
|||||||
sub r0, r0, #0x60
|
sub r0, r0, #0x60
|
||||||
bl _bsaes_decrypt8
|
bl _bsaes_decrypt8
|
||||||
vldmia r9,{q14} @ reload IV
|
vldmia r9,{q14} @ reload IV
|
||||||
vld1.8 {q8-q9}, [r0]! @ reload input
|
vld1.8 {q8,q9}, [r0]! @ reload input
|
||||||
veor q0, q0, q14 @ ^= IV
|
veor q0, q0, q14 @ ^= IV
|
||||||
vld1.8 {q10-q11}, [r0]!
|
vld1.8 {q10,q11}, [r0]!
|
||||||
veor q1, q1, q8
|
veor q1, q1, q8
|
||||||
veor q6, q6, q9
|
veor q6, q6, q9
|
||||||
vld1.8 {q12}, [r0]!
|
vld1.8 {q12}, [r0]!
|
||||||
@ -1227,7 +1244,7 @@ bsaes_cbc_encrypt:
|
|||||||
veor q2, q2, q11
|
veor q2, q2, q11
|
||||||
vld1.8 {q15}, [r0]!
|
vld1.8 {q15}, [r0]!
|
||||||
veor q7, q7, q12
|
veor q7, q7, q12
|
||||||
vst1.8 {q0-q1}, [r1]! @ write output
|
vst1.8 {q0,q1}, [r1]! @ write output
|
||||||
vst1.8 {q6}, [r1]!
|
vst1.8 {q6}, [r1]!
|
||||||
vst1.8 {q4}, [r1]!
|
vst1.8 {q4}, [r1]!
|
||||||
vst1.8 {q2}, [r1]!
|
vst1.8 {q2}, [r1]!
|
||||||
@ -1238,14 +1255,14 @@ bsaes_cbc_encrypt:
|
|||||||
sub r0, r0, #0x50
|
sub r0, r0, #0x50
|
||||||
bl _bsaes_decrypt8
|
bl _bsaes_decrypt8
|
||||||
vldmia r9, {q14} @ reload IV
|
vldmia r9, {q14} @ reload IV
|
||||||
vld1.8 {q8-q9}, [r0]! @ reload input
|
vld1.8 {q8,q9}, [r0]! @ reload input
|
||||||
veor q0, q0, q14 @ ^= IV
|
veor q0, q0, q14 @ ^= IV
|
||||||
vld1.8 {q10-q11}, [r0]!
|
vld1.8 {q10,q11}, [r0]!
|
||||||
veor q1, q1, q8
|
veor q1, q1, q8
|
||||||
veor q6, q6, q9
|
veor q6, q6, q9
|
||||||
vld1.8 {q15}, [r0]!
|
vld1.8 {q15}, [r0]!
|
||||||
veor q4, q4, q10
|
veor q4, q4, q10
|
||||||
vst1.8 {q0-q1}, [r1]! @ write output
|
vst1.8 {q0,q1}, [r1]! @ write output
|
||||||
veor q2, q2, q11
|
veor q2, q2, q11
|
||||||
vst1.8 {q6}, [r1]!
|
vst1.8 {q6}, [r1]!
|
||||||
vst1.8 {q4}, [r1]!
|
vst1.8 {q4}, [r1]!
|
||||||
@ -1256,14 +1273,14 @@ bsaes_cbc_encrypt:
|
|||||||
sub r0, r0, #0x40
|
sub r0, r0, #0x40
|
||||||
bl _bsaes_decrypt8
|
bl _bsaes_decrypt8
|
||||||
vldmia r9, {q14} @ reload IV
|
vldmia r9, {q14} @ reload IV
|
||||||
vld1.8 {q8-q9}, [r0]! @ reload input
|
vld1.8 {q8,q9}, [r0]! @ reload input
|
||||||
veor q0, q0, q14 @ ^= IV
|
veor q0, q0, q14 @ ^= IV
|
||||||
vld1.8 {q10}, [r0]!
|
vld1.8 {q10}, [r0]!
|
||||||
veor q1, q1, q8
|
veor q1, q1, q8
|
||||||
veor q6, q6, q9
|
veor q6, q6, q9
|
||||||
vld1.8 {q15}, [r0]!
|
vld1.8 {q15}, [r0]!
|
||||||
veor q4, q4, q10
|
veor q4, q4, q10
|
||||||
vst1.8 {q0-q1}, [r1]! @ write output
|
vst1.8 {q0,q1}, [r1]! @ write output
|
||||||
vst1.8 {q6}, [r1]!
|
vst1.8 {q6}, [r1]!
|
||||||
vst1.8 {q4}, [r1]!
|
vst1.8 {q4}, [r1]!
|
||||||
b .Lcbc_dec_done
|
b .Lcbc_dec_done
|
||||||
@ -1272,12 +1289,12 @@ bsaes_cbc_encrypt:
|
|||||||
sub r0, r0, #0x30
|
sub r0, r0, #0x30
|
||||||
bl _bsaes_decrypt8
|
bl _bsaes_decrypt8
|
||||||
vldmia r9, {q14} @ reload IV
|
vldmia r9, {q14} @ reload IV
|
||||||
vld1.8 {q8-q9}, [r0]! @ reload input
|
vld1.8 {q8,q9}, [r0]! @ reload input
|
||||||
veor q0, q0, q14 @ ^= IV
|
veor q0, q0, q14 @ ^= IV
|
||||||
vld1.8 {q15}, [r0]!
|
vld1.8 {q15}, [r0]!
|
||||||
veor q1, q1, q8
|
veor q1, q1, q8
|
||||||
veor q6, q6, q9
|
veor q6, q6, q9
|
||||||
vst1.8 {q0-q1}, [r1]! @ write output
|
vst1.8 {q0,q1}, [r1]! @ write output
|
||||||
vst1.8 {q6}, [r1]!
|
vst1.8 {q6}, [r1]!
|
||||||
b .Lcbc_dec_done
|
b .Lcbc_dec_done
|
||||||
.align 4
|
.align 4
|
||||||
@ -1289,7 +1306,7 @@ bsaes_cbc_encrypt:
|
|||||||
veor q0, q0, q14 @ ^= IV
|
veor q0, q0, q14 @ ^= IV
|
||||||
vld1.8 {q15}, [r0]! @ reload input
|
vld1.8 {q15}, [r0]! @ reload input
|
||||||
veor q1, q1, q8
|
veor q1, q1, q8
|
||||||
vst1.8 {q0-q1}, [r1]! @ write output
|
vst1.8 {q0,q1}, [r1]! @ write output
|
||||||
b .Lcbc_dec_done
|
b .Lcbc_dec_done
|
||||||
.align 4
|
.align 4
|
||||||
.Lcbc_dec_one:
|
.Lcbc_dec_one:
|
||||||
@ -1310,7 +1327,7 @@ bsaes_cbc_encrypt:
|
|||||||
vmov.i32 q0, #0
|
vmov.i32 q0, #0
|
||||||
vmov.i32 q1, #0
|
vmov.i32 q1, #0
|
||||||
.Lcbc_dec_bzero:@ wipe key schedule [if any]
|
.Lcbc_dec_bzero:@ wipe key schedule [if any]
|
||||||
vstmia sp!, {q0-q1}
|
vstmia sp!, {q0,q1}
|
||||||
cmp sp, r9
|
cmp sp, r9
|
||||||
bne .Lcbc_dec_bzero
|
bne .Lcbc_dec_bzero
|
||||||
#endif
|
#endif
|
||||||
@ -1319,10 +1336,10 @@ bsaes_cbc_encrypt:
|
|||||||
add sp, #0x10 @ add sp,r9,#0x10 is no good for thumb
|
add sp, #0x10 @ add sp,r9,#0x10 is no good for thumb
|
||||||
vst1.8 {q15}, [r8] @ return IV
|
vst1.8 {q15}, [r8] @ return IV
|
||||||
VFP_ABI_POP
|
VFP_ABI_POP
|
||||||
ldmia sp!, {r4-r10, pc}
|
ldmia sp!, {r4,r5,r6,r7,r8,r9,r10, pc}
|
||||||
.size bsaes_cbc_encrypt,.-bsaes_cbc_encrypt
|
.size bsaes_cbc_encrypt,.-bsaes_cbc_encrypt
|
||||||
.extern AES_encrypt
|
|
||||||
.global bsaes_ctr32_encrypt_blocks
|
.globl bsaes_ctr32_encrypt_blocks
|
||||||
.type bsaes_ctr32_encrypt_blocks,%function
|
.type bsaes_ctr32_encrypt_blocks,%function
|
||||||
.align 5
|
.align 5
|
||||||
bsaes_ctr32_encrypt_blocks:
|
bsaes_ctr32_encrypt_blocks:
|
||||||
@ -1330,7 +1347,7 @@ bsaes_ctr32_encrypt_blocks:
|
|||||||
blo .Lctr_enc_short @ small sizes
|
blo .Lctr_enc_short @ small sizes
|
||||||
|
|
||||||
mov ip, sp
|
mov ip, sp
|
||||||
stmdb sp!, {r4-r10, lr}
|
stmdb sp!, {r4,r5,r6,r7,r8,r9,r10, lr}
|
||||||
VFP_ABI_PUSH
|
VFP_ABI_PUSH
|
||||||
ldr r8, [ip] @ ctr is 1st arg on the stack
|
ldr r8, [ip] @ ctr is 1st arg on the stack
|
||||||
sub sp, sp, #0x10 @ scratch space to carry over the ctr
|
sub sp, sp, #0x10 @ scratch space to carry over the ctr
|
||||||
@ -1351,7 +1368,12 @@ bsaes_ctr32_encrypt_blocks:
|
|||||||
vstmia r12, {q7} @ save last round key
|
vstmia r12, {q7} @ save last round key
|
||||||
|
|
||||||
vld1.8 {q0}, [r8] @ load counter
|
vld1.8 {q0}, [r8] @ load counter
|
||||||
|
#ifdef __APPLE__
|
||||||
|
mov r8, #:lower16:(.LREVM0SR-.LM0)
|
||||||
|
add r8, r6, r8
|
||||||
|
#else
|
||||||
add r8, r6, #.LREVM0SR-.LM0 @ borrow r8
|
add r8, r6, #.LREVM0SR-.LM0 @ borrow r8
|
||||||
|
#endif
|
||||||
vldmia sp, {q4} @ load round0 key
|
vldmia sp, {q4} @ load round0 key
|
||||||
#else
|
#else
|
||||||
ldr r12, [r3, #244]
|
ldr r12, [r3, #244]
|
||||||
@ -1368,7 +1390,7 @@ bsaes_ctr32_encrypt_blocks:
|
|||||||
vstmia r12, {q7} @ save last round key
|
vstmia r12, {q7} @ save last round key
|
||||||
|
|
||||||
.align 2
|
.align 2
|
||||||
0: add r12, r3, #248
|
add r12, r3, #248
|
||||||
vld1.8 {q0}, [r8] @ load counter
|
vld1.8 {q0}, [r8] @ load counter
|
||||||
adrl r8, .LREVM0SR @ borrow r8
|
adrl r8, .LREVM0SR @ borrow r8
|
||||||
vldmia r12, {q4} @ load round0 key
|
vldmia r12, {q4} @ load round0 key
|
||||||
@ -1408,23 +1430,28 @@ bsaes_ctr32_encrypt_blocks:
|
|||||||
vldmia r8, {q8} @ .LREVM0SR
|
vldmia r8, {q8} @ .LREVM0SR
|
||||||
mov r5, r10 @ pass rounds
|
mov r5, r10 @ pass rounds
|
||||||
vstmia r9, {q10} @ save next counter
|
vstmia r9, {q10} @ save next counter
|
||||||
|
#ifdef __APPLE__
|
||||||
|
mov r6, #:lower16:(.LREVM0SR-.LSR)
|
||||||
|
sub r6, r8, r6
|
||||||
|
#else
|
||||||
sub r6, r8, #.LREVM0SR-.LSR @ pass constants
|
sub r6, r8, #.LREVM0SR-.LSR @ pass constants
|
||||||
|
#endif
|
||||||
|
|
||||||
bl _bsaes_encrypt8_alt
|
bl _bsaes_encrypt8_alt
|
||||||
|
|
||||||
subs r2, r2, #8
|
subs r2, r2, #8
|
||||||
blo .Lctr_enc_loop_done
|
blo .Lctr_enc_loop_done
|
||||||
|
|
||||||
vld1.8 {q8-q9}, [r0]! @ load input
|
vld1.8 {q8,q9}, [r0]! @ load input
|
||||||
vld1.8 {q10-q11}, [r0]!
|
vld1.8 {q10,q11}, [r0]!
|
||||||
veor q0, q8
|
veor q0, q8
|
||||||
veor q1, q9
|
veor q1, q9
|
||||||
vld1.8 {q12-q13}, [r0]!
|
vld1.8 {q12,q13}, [r0]!
|
||||||
veor q4, q10
|
veor q4, q10
|
||||||
veor q6, q11
|
veor q6, q11
|
||||||
vld1.8 {q14-q15}, [r0]!
|
vld1.8 {q14,q15}, [r0]!
|
||||||
veor q3, q12
|
veor q3, q12
|
||||||
vst1.8 {q0-q1}, [r1]! @ write output
|
vst1.8 {q0,q1}, [r1]! @ write output
|
||||||
veor q7, q13
|
veor q7, q13
|
||||||
veor q2, q14
|
veor q2, q14
|
||||||
vst1.8 {q4}, [r1]!
|
vst1.8 {q4}, [r1]!
|
||||||
@ -1482,34 +1509,34 @@ bsaes_ctr32_encrypt_blocks:
|
|||||||
vmov.i32 q1, #0
|
vmov.i32 q1, #0
|
||||||
#ifndef BSAES_ASM_EXTENDED_KEY
|
#ifndef BSAES_ASM_EXTENDED_KEY
|
||||||
.Lctr_enc_bzero:@ wipe key schedule [if any]
|
.Lctr_enc_bzero:@ wipe key schedule [if any]
|
||||||
vstmia sp!, {q0-q1}
|
vstmia sp!, {q0,q1}
|
||||||
cmp sp, r9
|
cmp sp, r9
|
||||||
bne .Lctr_enc_bzero
|
bne .Lctr_enc_bzero
|
||||||
#else
|
#else
|
||||||
vstmia sp, {q0-q1}
|
vstmia sp, {q0,q1}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
mov sp, r9
|
mov sp, r9
|
||||||
add sp, #0x10 @ add sp,r9,#0x10 is no good for thumb
|
add sp, #0x10 @ add sp,r9,#0x10 is no good for thumb
|
||||||
VFP_ABI_POP
|
VFP_ABI_POP
|
||||||
ldmia sp!, {r4-r10, pc} @ return
|
ldmia sp!, {r4,r5,r6,r7,r8,r9,r10, pc} @ return
|
||||||
|
|
||||||
.align 4
|
.align 4
|
||||||
.Lctr_enc_short:
|
.Lctr_enc_short:
|
||||||
ldr ip, [sp] @ ctr pointer is passed on stack
|
ldr ip, [sp] @ ctr pointer is passed on stack
|
||||||
stmdb sp!, {r4-r8, lr}
|
stmdb sp!, {r4,r5,r6,r7,r8, lr}
|
||||||
|
|
||||||
mov r4, r0 @ copy arguments
|
mov r4, r0 @ copy arguments
|
||||||
mov r5, r1
|
mov r5, r1
|
||||||
mov r6, r2
|
mov r6, r2
|
||||||
mov r7, r3
|
mov r7, r3
|
||||||
ldr r8, [ip, #12] @ load counter LSW
|
ldr r8, [ip, #12] @ load counter .LSW
|
||||||
vld1.8 {q1}, [ip] @ load whole counter value
|
vld1.8 {q1}, [ip] @ load whole counter value
|
||||||
#ifdef __ARMEL__
|
#ifdef __ARMEL__
|
||||||
rev r8, r8
|
rev r8, r8
|
||||||
#endif
|
#endif
|
||||||
sub sp, sp, #0x10
|
sub sp, sp, #0x10
|
||||||
vst1.8 {q1}, [sp,:64] @ copy counter value
|
vst1.8 {q1}, [sp] @ copy counter value
|
||||||
sub sp, sp, #0x10
|
sub sp, sp, #0x10
|
||||||
|
|
||||||
.Lctr_enc_short_loop:
|
.Lctr_enc_short_loop:
|
||||||
@ -1520,7 +1547,7 @@ bsaes_ctr32_encrypt_blocks:
|
|||||||
bl AES_encrypt
|
bl AES_encrypt
|
||||||
|
|
||||||
vld1.8 {q0}, [r4]! @ load input
|
vld1.8 {q0}, [r4]! @ load input
|
||||||
vld1.8 {q1}, [sp,:64] @ load encrypted counter
|
vld1.8 {q1}, [sp] @ load encrypted counter
|
||||||
add r8, r8, #1
|
add r8, r8, #1
|
||||||
#ifdef __ARMEL__
|
#ifdef __ARMEL__
|
||||||
rev r0, r8
|
rev r0, r8
|
||||||
@ -1535,16 +1562,16 @@ bsaes_ctr32_encrypt_blocks:
|
|||||||
|
|
||||||
vmov.i32 q0, #0
|
vmov.i32 q0, #0
|
||||||
vmov.i32 q1, #0
|
vmov.i32 q1, #0
|
||||||
vstmia sp!, {q0-q1}
|
vstmia sp!, {q0,q1}
|
||||||
|
|
||||||
ldmia sp!, {r4-r8, pc}
|
ldmia sp!, {r4,r5,r6,r7,r8, pc}
|
||||||
.size bsaes_ctr32_encrypt_blocks,.-bsaes_ctr32_encrypt_blocks
|
.size bsaes_ctr32_encrypt_blocks,.-bsaes_ctr32_encrypt_blocks
|
||||||
.globl bsaes_xts_encrypt
|
.globl bsaes_xts_encrypt
|
||||||
.type bsaes_xts_encrypt,%function
|
.type bsaes_xts_encrypt,%function
|
||||||
.align 4
|
.align 4
|
||||||
bsaes_xts_encrypt:
|
bsaes_xts_encrypt:
|
||||||
mov ip, sp
|
mov ip, sp
|
||||||
stmdb sp!, {r4-r10, lr} @ 0x20
|
stmdb sp!, {r4,r5,r6,r7,r8,r9,r10, lr} @ 0x20
|
||||||
VFP_ABI_PUSH
|
VFP_ABI_PUSH
|
||||||
mov r6, sp @ future r3
|
mov r6, sp @ future r3
|
||||||
|
|
||||||
@ -1598,7 +1625,7 @@ bsaes_xts_encrypt:
|
|||||||
vstmia r12, {q7}
|
vstmia r12, {q7}
|
||||||
|
|
||||||
.align 2
|
.align 2
|
||||||
0: sub sp, #0x90 @ place for tweak[9]
|
sub sp, #0x90 @ place for tweak[9]
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
vld1.8 {q8}, [r0] @ initial tweak
|
vld1.8 {q8}, [r0] @ initial tweak
|
||||||
@ -1673,7 +1700,7 @@ bsaes_xts_encrypt:
|
|||||||
veor q8, q8, q7
|
veor q8, q8, q7
|
||||||
vst1.64 {q8}, [r0,:128] @ next round tweak
|
vst1.64 {q8}, [r0,:128] @ next round tweak
|
||||||
|
|
||||||
vld1.8 {q6-q7}, [r7]!
|
vld1.8 {q6,q7}, [r7]!
|
||||||
veor q5, q5, q13
|
veor q5, q5, q13
|
||||||
#ifndef BSAES_ASM_EXTENDED_KEY
|
#ifndef BSAES_ASM_EXTENDED_KEY
|
||||||
add r4, sp, #0x90 @ pass key schedule
|
add r4, sp, #0x90 @ pass key schedule
|
||||||
@ -1687,22 +1714,22 @@ bsaes_xts_encrypt:
|
|||||||
|
|
||||||
bl _bsaes_encrypt8
|
bl _bsaes_encrypt8
|
||||||
|
|
||||||
vld1.64 {q8-q9}, [r0,:128]!
|
vld1.64 {q8,q9}, [r0,:128]!
|
||||||
vld1.64 {q10-q11}, [r0,:128]!
|
vld1.64 {q10,q11}, [r0,:128]!
|
||||||
veor q0, q0, q8
|
veor q0, q0, q8
|
||||||
vld1.64 {q12-q13}, [r0,:128]!
|
vld1.64 {q12,q13}, [r0,:128]!
|
||||||
veor q1, q1, q9
|
veor q1, q1, q9
|
||||||
veor q8, q4, q10
|
veor q8, q4, q10
|
||||||
vst1.8 {q0-q1}, [r8]!
|
vst1.8 {q0,q1}, [r8]!
|
||||||
veor q9, q6, q11
|
veor q9, q6, q11
|
||||||
vld1.64 {q14-q15}, [r0,:128]!
|
vld1.64 {q14,q15}, [r0,:128]!
|
||||||
veor q10, q3, q12
|
veor q10, q3, q12
|
||||||
vst1.8 {q8-q9}, [r8]!
|
vst1.8 {q8,q9}, [r8]!
|
||||||
veor q11, q7, q13
|
veor q11, q7, q13
|
||||||
veor q12, q2, q14
|
veor q12, q2, q14
|
||||||
vst1.8 {q10-q11}, [r8]!
|
vst1.8 {q10,q11}, [r8]!
|
||||||
veor q13, q5, q15
|
veor q13, q5, q15
|
||||||
vst1.8 {q12-q13}, [r8]!
|
vst1.8 {q12,q13}, [r8]!
|
||||||
|
|
||||||
vld1.64 {q8}, [r0,:128] @ next round tweak
|
vld1.64 {q8}, [r0,:128] @ next round tweak
|
||||||
|
|
||||||
@ -1798,20 +1825,20 @@ bsaes_xts_encrypt:
|
|||||||
|
|
||||||
bl _bsaes_encrypt8
|
bl _bsaes_encrypt8
|
||||||
|
|
||||||
vld1.64 {q8-q9}, [r0,:128]!
|
vld1.64 {q8,q9}, [r0,:128]!
|
||||||
vld1.64 {q10-q11}, [r0,:128]!
|
vld1.64 {q10,q11}, [r0,:128]!
|
||||||
veor q0, q0, q8
|
veor q0, q0, q8
|
||||||
vld1.64 {q12-q13}, [r0,:128]!
|
vld1.64 {q12,q13}, [r0,:128]!
|
||||||
veor q1, q1, q9
|
veor q1, q1, q9
|
||||||
veor q8, q4, q10
|
veor q8, q4, q10
|
||||||
vst1.8 {q0-q1}, [r8]!
|
vst1.8 {q0,q1}, [r8]!
|
||||||
veor q9, q6, q11
|
veor q9, q6, q11
|
||||||
vld1.64 {q14}, [r0,:128]!
|
vld1.64 {q14}, [r0,:128]!
|
||||||
veor q10, q3, q12
|
veor q10, q3, q12
|
||||||
vst1.8 {q8-q9}, [r8]!
|
vst1.8 {q8,q9}, [r8]!
|
||||||
veor q11, q7, q13
|
veor q11, q7, q13
|
||||||
veor q12, q2, q14
|
veor q12, q2, q14
|
||||||
vst1.8 {q10-q11}, [r8]!
|
vst1.8 {q10,q11}, [r8]!
|
||||||
vst1.8 {q12}, [r8]!
|
vst1.8 {q12}, [r8]!
|
||||||
|
|
||||||
vld1.64 {q8}, [r0,:128] @ next round tweak
|
vld1.64 {q8}, [r0,:128] @ next round tweak
|
||||||
@ -1830,18 +1857,18 @@ bsaes_xts_encrypt:
|
|||||||
|
|
||||||
bl _bsaes_encrypt8
|
bl _bsaes_encrypt8
|
||||||
|
|
||||||
vld1.64 {q8-q9}, [r0,:128]!
|
vld1.64 {q8,q9}, [r0,:128]!
|
||||||
vld1.64 {q10-q11}, [r0,:128]!
|
vld1.64 {q10,q11}, [r0,:128]!
|
||||||
veor q0, q0, q8
|
veor q0, q0, q8
|
||||||
vld1.64 {q12-q13}, [r0,:128]!
|
vld1.64 {q12,q13}, [r0,:128]!
|
||||||
veor q1, q1, q9
|
veor q1, q1, q9
|
||||||
veor q8, q4, q10
|
veor q8, q4, q10
|
||||||
vst1.8 {q0-q1}, [r8]!
|
vst1.8 {q0,q1}, [r8]!
|
||||||
veor q9, q6, q11
|
veor q9, q6, q11
|
||||||
veor q10, q3, q12
|
veor q10, q3, q12
|
||||||
vst1.8 {q8-q9}, [r8]!
|
vst1.8 {q8,q9}, [r8]!
|
||||||
veor q11, q7, q13
|
veor q11, q7, q13
|
||||||
vst1.8 {q10-q11}, [r8]!
|
vst1.8 {q10,q11}, [r8]!
|
||||||
|
|
||||||
vld1.64 {q8}, [r0,:128] @ next round tweak
|
vld1.64 {q8}, [r0,:128] @ next round tweak
|
||||||
b .Lxts_enc_done
|
b .Lxts_enc_done
|
||||||
@ -1865,16 +1892,16 @@ bsaes_xts_encrypt:
|
|||||||
|
|
||||||
bl _bsaes_encrypt8
|
bl _bsaes_encrypt8
|
||||||
|
|
||||||
vld1.64 {q8-q9}, [r0,:128]!
|
vld1.64 {q8,q9}, [r0,:128]!
|
||||||
vld1.64 {q10-q11}, [r0,:128]!
|
vld1.64 {q10,q11}, [r0,:128]!
|
||||||
veor q0, q0, q8
|
veor q0, q0, q8
|
||||||
vld1.64 {q12}, [r0,:128]!
|
vld1.64 {q12}, [r0,:128]!
|
||||||
veor q1, q1, q9
|
veor q1, q1, q9
|
||||||
veor q8, q4, q10
|
veor q8, q4, q10
|
||||||
vst1.8 {q0-q1}, [r8]!
|
vst1.8 {q0,q1}, [r8]!
|
||||||
veor q9, q6, q11
|
veor q9, q6, q11
|
||||||
veor q10, q3, q12
|
veor q10, q3, q12
|
||||||
vst1.8 {q8-q9}, [r8]!
|
vst1.8 {q8,q9}, [r8]!
|
||||||
vst1.8 {q10}, [r8]!
|
vst1.8 {q10}, [r8]!
|
||||||
|
|
||||||
vld1.64 {q8}, [r0,:128] @ next round tweak
|
vld1.64 {q8}, [r0,:128] @ next round tweak
|
||||||
@ -1893,14 +1920,14 @@ bsaes_xts_encrypt:
|
|||||||
|
|
||||||
bl _bsaes_encrypt8
|
bl _bsaes_encrypt8
|
||||||
|
|
||||||
vld1.64 {q8-q9}, [r0,:128]!
|
vld1.64 {q8,q9}, [r0,:128]!
|
||||||
vld1.64 {q10-q11}, [r0,:128]!
|
vld1.64 {q10,q11}, [r0,:128]!
|
||||||
veor q0, q0, q8
|
veor q0, q0, q8
|
||||||
veor q1, q1, q9
|
veor q1, q1, q9
|
||||||
veor q8, q4, q10
|
veor q8, q4, q10
|
||||||
vst1.8 {q0-q1}, [r8]!
|
vst1.8 {q0,q1}, [r8]!
|
||||||
veor q9, q6, q11
|
veor q9, q6, q11
|
||||||
vst1.8 {q8-q9}, [r8]!
|
vst1.8 {q8,q9}, [r8]!
|
||||||
|
|
||||||
vld1.64 {q8}, [r0,:128] @ next round tweak
|
vld1.64 {q8}, [r0,:128] @ next round tweak
|
||||||
b .Lxts_enc_done
|
b .Lxts_enc_done
|
||||||
@ -1918,12 +1945,12 @@ bsaes_xts_encrypt:
|
|||||||
|
|
||||||
bl _bsaes_encrypt8
|
bl _bsaes_encrypt8
|
||||||
|
|
||||||
vld1.64 {q8-q9}, [r0,:128]!
|
vld1.64 {q8,q9}, [r0,:128]!
|
||||||
vld1.64 {q10}, [r0,:128]!
|
vld1.64 {q10}, [r0,:128]!
|
||||||
veor q0, q0, q8
|
veor q0, q0, q8
|
||||||
veor q1, q1, q9
|
veor q1, q1, q9
|
||||||
veor q8, q4, q10
|
veor q8, q4, q10
|
||||||
vst1.8 {q0-q1}, [r8]!
|
vst1.8 {q0,q1}, [r8]!
|
||||||
vst1.8 {q8}, [r8]!
|
vst1.8 {q8}, [r8]!
|
||||||
|
|
||||||
vld1.64 {q8}, [r0,:128] @ next round tweak
|
vld1.64 {q8}, [r0,:128] @ next round tweak
|
||||||
@ -1942,10 +1969,10 @@ bsaes_xts_encrypt:
|
|||||||
|
|
||||||
bl _bsaes_encrypt8
|
bl _bsaes_encrypt8
|
||||||
|
|
||||||
vld1.64 {q8-q9}, [r0,:128]!
|
vld1.64 {q8,q9}, [r0,:128]!
|
||||||
veor q0, q0, q8
|
veor q0, q0, q8
|
||||||
veor q1, q1, q9
|
veor q1, q1, q9
|
||||||
vst1.8 {q0-q1}, [r8]!
|
vst1.8 {q0,q1}, [r8]!
|
||||||
|
|
||||||
vld1.64 {q8}, [r0,:128] @ next round tweak
|
vld1.64 {q8}, [r0,:128] @ next round tweak
|
||||||
b .Lxts_enc_done
|
b .Lxts_enc_done
|
||||||
@ -2006,7 +2033,7 @@ bsaes_xts_encrypt:
|
|||||||
ldr r1, [r3, #0x20+VFP_ABI_FRAME] @ chain tweak
|
ldr r1, [r3, #0x20+VFP_ABI_FRAME] @ chain tweak
|
||||||
#endif
|
#endif
|
||||||
.Lxts_enc_bzero:@ wipe key schedule [if any]
|
.Lxts_enc_bzero:@ wipe key schedule [if any]
|
||||||
vstmia sp!, {q0-q1}
|
vstmia sp!, {q0,q1}
|
||||||
cmp sp, r0
|
cmp sp, r0
|
||||||
bne .Lxts_enc_bzero
|
bne .Lxts_enc_bzero
|
||||||
|
|
||||||
@ -2015,7 +2042,7 @@ bsaes_xts_encrypt:
|
|||||||
vst1.8 {q8}, [r1]
|
vst1.8 {q8}, [r1]
|
||||||
#endif
|
#endif
|
||||||
VFP_ABI_POP
|
VFP_ABI_POP
|
||||||
ldmia sp!, {r4-r10, pc} @ return
|
ldmia sp!, {r4,r5,r6,r7,r8,r9,r10, pc} @ return
|
||||||
|
|
||||||
.size bsaes_xts_encrypt,.-bsaes_xts_encrypt
|
.size bsaes_xts_encrypt,.-bsaes_xts_encrypt
|
||||||
|
|
||||||
@ -2024,7 +2051,7 @@ bsaes_xts_encrypt:
|
|||||||
.align 4
|
.align 4
|
||||||
bsaes_xts_decrypt:
|
bsaes_xts_decrypt:
|
||||||
mov ip, sp
|
mov ip, sp
|
||||||
stmdb sp!, {r4-r10, lr} @ 0x20
|
stmdb sp!, {r4,r5,r6,r7,r8,r9,r10, lr} @ 0x20
|
||||||
VFP_ABI_PUSH
|
VFP_ABI_PUSH
|
||||||
mov r6, sp @ future r3
|
mov r6, sp @ future r3
|
||||||
|
|
||||||
@ -2084,14 +2111,16 @@ bsaes_xts_decrypt:
|
|||||||
vstmia r4, {q7}
|
vstmia r4, {q7}
|
||||||
|
|
||||||
.align 2
|
.align 2
|
||||||
0: sub sp, #0x90 @ place for tweak[9]
|
sub sp, #0x90 @ place for tweak[9]
|
||||||
#endif
|
#endif
|
||||||
vld1.8 {q8}, [r0] @ initial tweak
|
vld1.8 {q8}, [r0] @ initial tweak
|
||||||
adr r2, .Lxts_magic
|
adr r2, .Lxts_magic
|
||||||
|
|
||||||
|
#ifndef XTS_CHAIN_TWEAK
|
||||||
tst r9, #0xf @ if not multiple of 16
|
tst r9, #0xf @ if not multiple of 16
|
||||||
it ne @ Thumb2 thing, sanity check in ARM
|
it ne @ Thumb2 thing, sanity check in ARM
|
||||||
subne r9, #0x10 @ subtract another 16 bytes
|
subne r9, #0x10 @ subtract another 16 bytes
|
||||||
|
#endif
|
||||||
subs r9, #0x80
|
subs r9, #0x80
|
||||||
|
|
||||||
blo .Lxts_dec_short
|
blo .Lxts_dec_short
|
||||||
@ -2162,7 +2191,7 @@ bsaes_xts_decrypt:
|
|||||||
veor q8, q8, q7
|
veor q8, q8, q7
|
||||||
vst1.64 {q8}, [r0,:128] @ next round tweak
|
vst1.64 {q8}, [r0,:128] @ next round tweak
|
||||||
|
|
||||||
vld1.8 {q6-q7}, [r7]!
|
vld1.8 {q6,q7}, [r7]!
|
||||||
veor q5, q5, q13
|
veor q5, q5, q13
|
||||||
#ifndef BSAES_ASM_EXTENDED_KEY
|
#ifndef BSAES_ASM_EXTENDED_KEY
|
||||||
add r4, sp, #0x90 @ pass key schedule
|
add r4, sp, #0x90 @ pass key schedule
|
||||||
@ -2176,22 +2205,22 @@ bsaes_xts_decrypt:
|
|||||||
|
|
||||||
bl _bsaes_decrypt8
|
bl _bsaes_decrypt8
|
||||||
|
|
||||||
vld1.64 {q8-q9}, [r0,:128]!
|
vld1.64 {q8,q9}, [r0,:128]!
|
||||||
vld1.64 {q10-q11}, [r0,:128]!
|
vld1.64 {q10,q11}, [r0,:128]!
|
||||||
veor q0, q0, q8
|
veor q0, q0, q8
|
||||||
vld1.64 {q12-q13}, [r0,:128]!
|
vld1.64 {q12,q13}, [r0,:128]!
|
||||||
veor q1, q1, q9
|
veor q1, q1, q9
|
||||||
veor q8, q6, q10
|
veor q8, q6, q10
|
||||||
vst1.8 {q0-q1}, [r8]!
|
vst1.8 {q0,q1}, [r8]!
|
||||||
veor q9, q4, q11
|
veor q9, q4, q11
|
||||||
vld1.64 {q14-q15}, [r0,:128]!
|
vld1.64 {q14,q15}, [r0,:128]!
|
||||||
veor q10, q2, q12
|
veor q10, q2, q12
|
||||||
vst1.8 {q8-q9}, [r8]!
|
vst1.8 {q8,q9}, [r8]!
|
||||||
veor q11, q7, q13
|
veor q11, q7, q13
|
||||||
veor q12, q3, q14
|
veor q12, q3, q14
|
||||||
vst1.8 {q10-q11}, [r8]!
|
vst1.8 {q10,q11}, [r8]!
|
||||||
veor q13, q5, q15
|
veor q13, q5, q15
|
||||||
vst1.8 {q12-q13}, [r8]!
|
vst1.8 {q12,q13}, [r8]!
|
||||||
|
|
||||||
vld1.64 {q8}, [r0,:128] @ next round tweak
|
vld1.64 {q8}, [r0,:128] @ next round tweak
|
||||||
|
|
||||||
@ -2287,20 +2316,20 @@ bsaes_xts_decrypt:
|
|||||||
|
|
||||||
bl _bsaes_decrypt8
|
bl _bsaes_decrypt8
|
||||||
|
|
||||||
vld1.64 {q8-q9}, [r0,:128]!
|
vld1.64 {q8,q9}, [r0,:128]!
|
||||||
vld1.64 {q10-q11}, [r0,:128]!
|
vld1.64 {q10,q11}, [r0,:128]!
|
||||||
veor q0, q0, q8
|
veor q0, q0, q8
|
||||||
vld1.64 {q12-q13}, [r0,:128]!
|
vld1.64 {q12,q13}, [r0,:128]!
|
||||||
veor q1, q1, q9
|
veor q1, q1, q9
|
||||||
veor q8, q6, q10
|
veor q8, q6, q10
|
||||||
vst1.8 {q0-q1}, [r8]!
|
vst1.8 {q0,q1}, [r8]!
|
||||||
veor q9, q4, q11
|
veor q9, q4, q11
|
||||||
vld1.64 {q14}, [r0,:128]!
|
vld1.64 {q14}, [r0,:128]!
|
||||||
veor q10, q2, q12
|
veor q10, q2, q12
|
||||||
vst1.8 {q8-q9}, [r8]!
|
vst1.8 {q8,q9}, [r8]!
|
||||||
veor q11, q7, q13
|
veor q11, q7, q13
|
||||||
veor q12, q3, q14
|
veor q12, q3, q14
|
||||||
vst1.8 {q10-q11}, [r8]!
|
vst1.8 {q10,q11}, [r8]!
|
||||||
vst1.8 {q12}, [r8]!
|
vst1.8 {q12}, [r8]!
|
||||||
|
|
||||||
vld1.64 {q8}, [r0,:128] @ next round tweak
|
vld1.64 {q8}, [r0,:128] @ next round tweak
|
||||||
@ -2321,18 +2350,18 @@ bsaes_xts_decrypt:
|
|||||||
|
|
||||||
bl _bsaes_decrypt8
|
bl _bsaes_decrypt8
|
||||||
|
|
||||||
vld1.64 {q8-q9}, [r0,:128]!
|
vld1.64 {q8,q9}, [r0,:128]!
|
||||||
vld1.64 {q10-q11}, [r0,:128]!
|
vld1.64 {q10,q11}, [r0,:128]!
|
||||||
veor q0, q0, q8
|
veor q0, q0, q8
|
||||||
vld1.64 {q12-q13}, [r0,:128]!
|
vld1.64 {q12,q13}, [r0,:128]!
|
||||||
veor q1, q1, q9
|
veor q1, q1, q9
|
||||||
veor q8, q6, q10
|
veor q8, q6, q10
|
||||||
vst1.8 {q0-q1}, [r8]!
|
vst1.8 {q0,q1}, [r8]!
|
||||||
veor q9, q4, q11
|
veor q9, q4, q11
|
||||||
veor q10, q2, q12
|
veor q10, q2, q12
|
||||||
vst1.8 {q8-q9}, [r8]!
|
vst1.8 {q8,q9}, [r8]!
|
||||||
veor q11, q7, q13
|
veor q11, q7, q13
|
||||||
vst1.8 {q10-q11}, [r8]!
|
vst1.8 {q10,q11}, [r8]!
|
||||||
|
|
||||||
vld1.64 {q8}, [r0,:128] @ next round tweak
|
vld1.64 {q8}, [r0,:128] @ next round tweak
|
||||||
b .Lxts_dec_done
|
b .Lxts_dec_done
|
||||||
@ -2350,16 +2379,16 @@ bsaes_xts_decrypt:
|
|||||||
|
|
||||||
bl _bsaes_decrypt8
|
bl _bsaes_decrypt8
|
||||||
|
|
||||||
vld1.64 {q8-q9}, [r0,:128]!
|
vld1.64 {q8,q9}, [r0,:128]!
|
||||||
vld1.64 {q10-q11}, [r0,:128]!
|
vld1.64 {q10,q11}, [r0,:128]!
|
||||||
veor q0, q0, q8
|
veor q0, q0, q8
|
||||||
vld1.64 {q12}, [r0,:128]!
|
vld1.64 {q12}, [r0,:128]!
|
||||||
veor q1, q1, q9
|
veor q1, q1, q9
|
||||||
veor q8, q6, q10
|
veor q8, q6, q10
|
||||||
vst1.8 {q0-q1}, [r8]!
|
vst1.8 {q0,q1}, [r8]!
|
||||||
veor q9, q4, q11
|
veor q9, q4, q11
|
||||||
veor q10, q2, q12
|
veor q10, q2, q12
|
||||||
vst1.8 {q8-q9}, [r8]!
|
vst1.8 {q8,q9}, [r8]!
|
||||||
vst1.8 {q10}, [r8]!
|
vst1.8 {q10}, [r8]!
|
||||||
|
|
||||||
vld1.64 {q8}, [r0,:128] @ next round tweak
|
vld1.64 {q8}, [r0,:128] @ next round tweak
|
||||||
@ -2378,14 +2407,14 @@ bsaes_xts_decrypt:
|
|||||||
|
|
||||||
bl _bsaes_decrypt8
|
bl _bsaes_decrypt8
|
||||||
|
|
||||||
vld1.64 {q8-q9}, [r0,:128]!
|
vld1.64 {q8,q9}, [r0,:128]!
|
||||||
vld1.64 {q10-q11}, [r0,:128]!
|
vld1.64 {q10,q11}, [r0,:128]!
|
||||||
veor q0, q0, q8
|
veor q0, q0, q8
|
||||||
veor q1, q1, q9
|
veor q1, q1, q9
|
||||||
veor q8, q6, q10
|
veor q8, q6, q10
|
||||||
vst1.8 {q0-q1}, [r8]!
|
vst1.8 {q0,q1}, [r8]!
|
||||||
veor q9, q4, q11
|
veor q9, q4, q11
|
||||||
vst1.8 {q8-q9}, [r8]!
|
vst1.8 {q8,q9}, [r8]!
|
||||||
|
|
||||||
vld1.64 {q8}, [r0,:128] @ next round tweak
|
vld1.64 {q8}, [r0,:128] @ next round tweak
|
||||||
b .Lxts_dec_done
|
b .Lxts_dec_done
|
||||||
@ -2403,12 +2432,12 @@ bsaes_xts_decrypt:
|
|||||||
|
|
||||||
bl _bsaes_decrypt8
|
bl _bsaes_decrypt8
|
||||||
|
|
||||||
vld1.64 {q8-q9}, [r0,:128]!
|
vld1.64 {q8,q9}, [r0,:128]!
|
||||||
vld1.64 {q10}, [r0,:128]!
|
vld1.64 {q10}, [r0,:128]!
|
||||||
veor q0, q0, q8
|
veor q0, q0, q8
|
||||||
veor q1, q1, q9
|
veor q1, q1, q9
|
||||||
veor q8, q6, q10
|
veor q8, q6, q10
|
||||||
vst1.8 {q0-q1}, [r8]!
|
vst1.8 {q0,q1}, [r8]!
|
||||||
vst1.8 {q8}, [r8]!
|
vst1.8 {q8}, [r8]!
|
||||||
|
|
||||||
vld1.64 {q8}, [r0,:128] @ next round tweak
|
vld1.64 {q8}, [r0,:128] @ next round tweak
|
||||||
@ -2427,10 +2456,10 @@ bsaes_xts_decrypt:
|
|||||||
|
|
||||||
bl _bsaes_decrypt8
|
bl _bsaes_decrypt8
|
||||||
|
|
||||||
vld1.64 {q8-q9}, [r0,:128]!
|
vld1.64 {q8,q9}, [r0,:128]!
|
||||||
veor q0, q0, q8
|
veor q0, q0, q8
|
||||||
veor q1, q1, q9
|
veor q1, q1, q9
|
||||||
vst1.8 {q0-q1}, [r8]!
|
vst1.8 {q0,q1}, [r8]!
|
||||||
|
|
||||||
vld1.64 {q8}, [r0,:128] @ next round tweak
|
vld1.64 {q8}, [r0,:128] @ next round tweak
|
||||||
b .Lxts_dec_done
|
b .Lxts_dec_done
|
||||||
@ -2515,7 +2544,7 @@ bsaes_xts_decrypt:
|
|||||||
ldr r1, [r3, #0x20+VFP_ABI_FRAME] @ chain tweak
|
ldr r1, [r3, #0x20+VFP_ABI_FRAME] @ chain tweak
|
||||||
#endif
|
#endif
|
||||||
.Lxts_dec_bzero:@ wipe key schedule [if any]
|
.Lxts_dec_bzero:@ wipe key schedule [if any]
|
||||||
vstmia sp!, {q0-q1}
|
vstmia sp!, {q0,q1}
|
||||||
cmp sp, r0
|
cmp sp, r0
|
||||||
bne .Lxts_dec_bzero
|
bne .Lxts_dec_bzero
|
||||||
|
|
||||||
@ -2524,7 +2553,7 @@ bsaes_xts_decrypt:
|
|||||||
vst1.8 {q8}, [r1]
|
vst1.8 {q8}, [r1]
|
||||||
#endif
|
#endif
|
||||||
VFP_ABI_POP
|
VFP_ABI_POP
|
||||||
ldmia sp!, {r4-r10, pc} @ return
|
ldmia sp!, {r4,r5,r6,r7,r8,r9,r10, pc} @ return
|
||||||
|
|
||||||
.size bsaes_xts_decrypt,.-bsaes_xts_decrypt
|
.size bsaes_xts_decrypt,.-bsaes_xts_decrypt
|
||||||
#endif
|
#endif
|
||||||
|
1472
secure/lib/libcrypto/arm/chacha-armv4.S
Normal file
1472
secure/lib/libcrypto/arm/chacha-armv4.S
Normal file
File diff suppressed because it is too large
Load Diff
4442
secure/lib/libcrypto/arm/ecp_nistz256-armv4.S
Normal file
4442
secure/lib/libcrypto/arm/ecp_nistz256-armv4.S
Normal file
File diff suppressed because it is too large
Load Diff
@ -3,12 +3,16 @@
|
|||||||
#include "arm_arch.h"
|
#include "arm_arch.h"
|
||||||
|
|
||||||
.text
|
.text
|
||||||
.code 32
|
#if defined(__thumb2__) || defined(__clang__)
|
||||||
|
.syntax unified
|
||||||
#ifdef __clang__
|
|
||||||
#define ldrplb ldrbpl
|
#define ldrplb ldrbpl
|
||||||
#define ldrneb ldrbne
|
#define ldrneb ldrbne
|
||||||
#endif
|
#endif
|
||||||
|
#if defined(__thumb2__)
|
||||||
|
.thumb
|
||||||
|
#else
|
||||||
|
.code 32
|
||||||
|
#endif
|
||||||
|
|
||||||
.type rem_4bit,%object
|
.type rem_4bit,%object
|
||||||
.align 5
|
.align 5
|
||||||
@ -21,22 +25,30 @@ rem_4bit:
|
|||||||
|
|
||||||
.type rem_4bit_get,%function
|
.type rem_4bit_get,%function
|
||||||
rem_4bit_get:
|
rem_4bit_get:
|
||||||
sub r2,pc,#8
|
#if defined(__thumb2__)
|
||||||
sub r2,r2,#32 @ &rem_4bit
|
adr r2,rem_4bit
|
||||||
|
#else
|
||||||
|
sub r2,pc,#8+32 @ &rem_4bit
|
||||||
|
#endif
|
||||||
b .Lrem_4bit_got
|
b .Lrem_4bit_got
|
||||||
nop
|
nop
|
||||||
|
nop
|
||||||
.size rem_4bit_get,.-rem_4bit_get
|
.size rem_4bit_get,.-rem_4bit_get
|
||||||
|
|
||||||
.global gcm_ghash_4bit
|
.globl gcm_ghash_4bit
|
||||||
.type gcm_ghash_4bit,%function
|
.type gcm_ghash_4bit,%function
|
||||||
|
.align 4
|
||||||
gcm_ghash_4bit:
|
gcm_ghash_4bit:
|
||||||
sub r12,pc,#8
|
#if defined(__thumb2__)
|
||||||
|
adr r12,rem_4bit
|
||||||
|
#else
|
||||||
|
sub r12,pc,#8+48 @ &rem_4bit
|
||||||
|
#endif
|
||||||
add r3,r2,r3 @ r3 to point at the end
|
add r3,r2,r3 @ r3 to point at the end
|
||||||
stmdb sp!,{r3-r11,lr} @ save r3/end too
|
stmdb sp!,{r3,r4,r5,r6,r7,r8,r9,r10,r11,lr} @ save r3/end too
|
||||||
sub r12,r12,#48 @ &rem_4bit
|
|
||||||
|
|
||||||
ldmia r12,{r4-r11} @ copy rem_4bit ...
|
ldmia r12,{r4,r5,r6,r7,r8,r9,r10,r11} @ copy rem_4bit ...
|
||||||
stmdb sp!,{r4-r11} @ ... to stack
|
stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11} @ ... to stack
|
||||||
|
|
||||||
ldrb r12,[r2,#15]
|
ldrb r12,[r2,#15]
|
||||||
ldrb r14,[r0,#15]
|
ldrb r14,[r0,#15]
|
||||||
@ -47,12 +59,12 @@ gcm_ghash_4bit:
|
|||||||
mov r3,#14
|
mov r3,#14
|
||||||
|
|
||||||
add r7,r1,r12,lsl#4
|
add r7,r1,r12,lsl#4
|
||||||
ldmia r7,{r4-r7} @ load Htbl[nlo]
|
ldmia r7,{r4,r5,r6,r7} @ load Htbl[nlo]
|
||||||
add r11,r1,r14
|
add r11,r1,r14
|
||||||
ldrb r12,[r2,#14]
|
ldrb r12,[r2,#14]
|
||||||
|
|
||||||
and r14,r4,#0xf @ rem
|
and r14,r4,#0xf @ rem
|
||||||
ldmia r11,{r8-r11} @ load Htbl[nhi]
|
ldmia r11,{r8,r9,r10,r11} @ load Htbl[nhi]
|
||||||
add r14,r14,r14
|
add r14,r14,r14
|
||||||
eor r4,r8,r4,lsr#4
|
eor r4,r8,r4,lsr#4
|
||||||
ldrh r8,[sp,r14] @ rem_4bit[rem]
|
ldrh r8,[sp,r14] @ rem_4bit[rem]
|
||||||
@ -73,13 +85,16 @@ gcm_ghash_4bit:
|
|||||||
and r12,r4,#0xf @ rem
|
and r12,r4,#0xf @ rem
|
||||||
subs r3,r3,#1
|
subs r3,r3,#1
|
||||||
add r12,r12,r12
|
add r12,r12,r12
|
||||||
ldmia r11,{r8-r11} @ load Htbl[nlo]
|
ldmia r11,{r8,r9,r10,r11} @ load Htbl[nlo]
|
||||||
eor r4,r8,r4,lsr#4
|
eor r4,r8,r4,lsr#4
|
||||||
eor r4,r4,r5,lsl#28
|
eor r4,r4,r5,lsl#28
|
||||||
eor r5,r9,r5,lsr#4
|
eor r5,r9,r5,lsr#4
|
||||||
eor r5,r5,r6,lsl#28
|
eor r5,r5,r6,lsl#28
|
||||||
ldrh r8,[sp,r12] @ rem_4bit[rem]
|
ldrh r8,[sp,r12] @ rem_4bit[rem]
|
||||||
eor r6,r10,r6,lsr#4
|
eor r6,r10,r6,lsr#4
|
||||||
|
#ifdef __thumb2__
|
||||||
|
it pl
|
||||||
|
#endif
|
||||||
ldrplb r12,[r2,r3]
|
ldrplb r12,[r2,r3]
|
||||||
eor r6,r6,r7,lsl#28
|
eor r6,r6,r7,lsl#28
|
||||||
eor r7,r11,r7,lsr#4
|
eor r7,r11,r7,lsr#4
|
||||||
@ -88,8 +103,11 @@ gcm_ghash_4bit:
|
|||||||
and r14,r4,#0xf @ rem
|
and r14,r4,#0xf @ rem
|
||||||
eor r7,r7,r8,lsl#16 @ ^= rem_4bit[rem]
|
eor r7,r7,r8,lsl#16 @ ^= rem_4bit[rem]
|
||||||
add r14,r14,r14
|
add r14,r14,r14
|
||||||
ldmia r11,{r8-r11} @ load Htbl[nhi]
|
ldmia r11,{r8,r9,r10,r11} @ load Htbl[nhi]
|
||||||
eor r4,r8,r4,lsr#4
|
eor r4,r8,r4,lsr#4
|
||||||
|
#ifdef __thumb2__
|
||||||
|
it pl
|
||||||
|
#endif
|
||||||
ldrplb r8,[r0,r3]
|
ldrplb r8,[r0,r3]
|
||||||
eor r4,r4,r5,lsl#28
|
eor r4,r4,r5,lsl#28
|
||||||
eor r5,r9,r5,lsr#4
|
eor r5,r9,r5,lsr#4
|
||||||
@ -97,8 +115,14 @@ gcm_ghash_4bit:
|
|||||||
eor r5,r5,r6,lsl#28
|
eor r5,r5,r6,lsl#28
|
||||||
eor r6,r10,r6,lsr#4
|
eor r6,r10,r6,lsr#4
|
||||||
eor r6,r6,r7,lsl#28
|
eor r6,r6,r7,lsl#28
|
||||||
|
#ifdef __thumb2__
|
||||||
|
it pl
|
||||||
|
#endif
|
||||||
eorpl r12,r12,r8
|
eorpl r12,r12,r8
|
||||||
eor r7,r11,r7,lsr#4
|
eor r7,r11,r7,lsr#4
|
||||||
|
#ifdef __thumb2__
|
||||||
|
itt pl
|
||||||
|
#endif
|
||||||
andpl r14,r12,#0xf0
|
andpl r14,r12,#0xf0
|
||||||
andpl r12,r12,#0x0f
|
andpl r12,r12,#0x0f
|
||||||
eor r7,r7,r9,lsl#16 @ ^= rem_4bit[rem]
|
eor r7,r7,r9,lsl#16 @ ^= rem_4bit[rem]
|
||||||
@ -136,6 +160,10 @@ gcm_ghash_4bit:
|
|||||||
strb r10,[r0,#8+1]
|
strb r10,[r0,#8+1]
|
||||||
strb r11,[r0,#8]
|
strb r11,[r0,#8]
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifdef __thumb2__
|
||||||
|
it ne
|
||||||
|
#endif
|
||||||
ldrneb r12,[r2,#15]
|
ldrneb r12,[r2,#15]
|
||||||
#if __ARM_ARCH__>=7 && defined(__ARMEL__)
|
#if __ARM_ARCH__>=7 && defined(__ARMEL__)
|
||||||
rev r6,r6
|
rev r6,r6
|
||||||
@ -171,19 +199,19 @@ gcm_ghash_4bit:
|
|||||||
|
|
||||||
add sp,sp,#36
|
add sp,sp,#36
|
||||||
#if __ARM_ARCH__>=5
|
#if __ARM_ARCH__>=5
|
||||||
ldmia sp!,{r4-r11,pc}
|
ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,pc}
|
||||||
#else
|
#else
|
||||||
ldmia sp!,{r4-r11,lr}
|
ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,lr}
|
||||||
tst lr,#1
|
tst lr,#1
|
||||||
moveq pc,lr @ be binary compatible with V4, yet
|
moveq pc,lr @ be binary compatible with V4, yet
|
||||||
.word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
.word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
||||||
#endif
|
#endif
|
||||||
.size gcm_ghash_4bit,.-gcm_ghash_4bit
|
.size gcm_ghash_4bit,.-gcm_ghash_4bit
|
||||||
|
|
||||||
.global gcm_gmult_4bit
|
.globl gcm_gmult_4bit
|
||||||
.type gcm_gmult_4bit,%function
|
.type gcm_gmult_4bit,%function
|
||||||
gcm_gmult_4bit:
|
gcm_gmult_4bit:
|
||||||
stmdb sp!,{r4-r11,lr}
|
stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,lr}
|
||||||
ldrb r12,[r0,#15]
|
ldrb r12,[r0,#15]
|
||||||
b rem_4bit_get
|
b rem_4bit_get
|
||||||
.Lrem_4bit_got:
|
.Lrem_4bit_got:
|
||||||
@ -192,12 +220,12 @@ gcm_gmult_4bit:
|
|||||||
mov r3,#14
|
mov r3,#14
|
||||||
|
|
||||||
add r7,r1,r12,lsl#4
|
add r7,r1,r12,lsl#4
|
||||||
ldmia r7,{r4-r7} @ load Htbl[nlo]
|
ldmia r7,{r4,r5,r6,r7} @ load Htbl[nlo]
|
||||||
ldrb r12,[r0,#14]
|
ldrb r12,[r0,#14]
|
||||||
|
|
||||||
add r11,r1,r14
|
add r11,r1,r14
|
||||||
and r14,r4,#0xf @ rem
|
and r14,r4,#0xf @ rem
|
||||||
ldmia r11,{r8-r11} @ load Htbl[nhi]
|
ldmia r11,{r8,r9,r10,r11} @ load Htbl[nhi]
|
||||||
add r14,r14,r14
|
add r14,r14,r14
|
||||||
eor r4,r8,r4,lsr#4
|
eor r4,r8,r4,lsr#4
|
||||||
ldrh r8,[r2,r14] @ rem_4bit[rem]
|
ldrh r8,[r2,r14] @ rem_4bit[rem]
|
||||||
@ -216,13 +244,16 @@ gcm_gmult_4bit:
|
|||||||
and r12,r4,#0xf @ rem
|
and r12,r4,#0xf @ rem
|
||||||
subs r3,r3,#1
|
subs r3,r3,#1
|
||||||
add r12,r12,r12
|
add r12,r12,r12
|
||||||
ldmia r11,{r8-r11} @ load Htbl[nlo]
|
ldmia r11,{r8,r9,r10,r11} @ load Htbl[nlo]
|
||||||
eor r4,r8,r4,lsr#4
|
eor r4,r8,r4,lsr#4
|
||||||
eor r4,r4,r5,lsl#28
|
eor r4,r4,r5,lsl#28
|
||||||
eor r5,r9,r5,lsr#4
|
eor r5,r9,r5,lsr#4
|
||||||
eor r5,r5,r6,lsl#28
|
eor r5,r5,r6,lsl#28
|
||||||
ldrh r8,[r2,r12] @ rem_4bit[rem]
|
ldrh r8,[r2,r12] @ rem_4bit[rem]
|
||||||
eor r6,r10,r6,lsr#4
|
eor r6,r10,r6,lsr#4
|
||||||
|
#ifdef __thumb2__
|
||||||
|
it pl
|
||||||
|
#endif
|
||||||
ldrplb r12,[r0,r3]
|
ldrplb r12,[r0,r3]
|
||||||
eor r6,r6,r7,lsl#28
|
eor r6,r6,r7,lsl#28
|
||||||
eor r7,r11,r7,lsr#4
|
eor r7,r11,r7,lsr#4
|
||||||
@ -231,7 +262,7 @@ gcm_gmult_4bit:
|
|||||||
and r14,r4,#0xf @ rem
|
and r14,r4,#0xf @ rem
|
||||||
eor r7,r7,r8,lsl#16 @ ^= rem_4bit[rem]
|
eor r7,r7,r8,lsl#16 @ ^= rem_4bit[rem]
|
||||||
add r14,r14,r14
|
add r14,r14,r14
|
||||||
ldmia r11,{r8-r11} @ load Htbl[nhi]
|
ldmia r11,{r8,r9,r10,r11} @ load Htbl[nhi]
|
||||||
eor r4,r8,r4,lsr#4
|
eor r4,r8,r4,lsr#4
|
||||||
eor r4,r4,r5,lsl#28
|
eor r4,r4,r5,lsl#28
|
||||||
eor r5,r9,r5,lsr#4
|
eor r5,r9,r5,lsr#4
|
||||||
@ -240,6 +271,9 @@ gcm_gmult_4bit:
|
|||||||
eor r6,r10,r6,lsr#4
|
eor r6,r10,r6,lsr#4
|
||||||
eor r6,r6,r7,lsl#28
|
eor r6,r6,r7,lsl#28
|
||||||
eor r7,r11,r7,lsr#4
|
eor r7,r11,r7,lsr#4
|
||||||
|
#ifdef __thumb2__
|
||||||
|
itt pl
|
||||||
|
#endif
|
||||||
andpl r14,r12,#0xf0
|
andpl r14,r12,#0xf0
|
||||||
andpl r12,r12,#0x0f
|
andpl r12,r12,#0x0f
|
||||||
eor r7,r7,r8,lsl#16 @ ^= rem_4bit[rem]
|
eor r7,r7,r8,lsl#16 @ ^= rem_4bit[rem]
|
||||||
@ -305,9 +339,9 @@ gcm_gmult_4bit:
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if __ARM_ARCH__>=5
|
#if __ARM_ARCH__>=5
|
||||||
ldmia sp!,{r4-r11,pc}
|
ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,pc}
|
||||||
#else
|
#else
|
||||||
ldmia sp!,{r4-r11,lr}
|
ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,lr}
|
||||||
tst lr,#1
|
tst lr,#1
|
||||||
moveq pc,lr @ be binary compatible with V4, yet
|
moveq pc,lr @ be binary compatible with V4, yet
|
||||||
.word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
.word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
||||||
@ -317,13 +351,13 @@ gcm_gmult_4bit:
|
|||||||
.arch armv7-a
|
.arch armv7-a
|
||||||
.fpu neon
|
.fpu neon
|
||||||
|
|
||||||
.global gcm_init_neon
|
.globl gcm_init_neon
|
||||||
.type gcm_init_neon,%function
|
.type gcm_init_neon,%function
|
||||||
.align 4
|
.align 4
|
||||||
gcm_init_neon:
|
gcm_init_neon:
|
||||||
vld1.64 d7,[r1,:64]! @ load H
|
vld1.64 d7,[r1]! @ load H
|
||||||
vmov.i8 q8,#0xe1
|
vmov.i8 q8,#0xe1
|
||||||
vld1.64 d6,[r1,:64]
|
vld1.64 d6,[r1]
|
||||||
vshl.i64 d17,#57
|
vshl.i64 d17,#57
|
||||||
vshr.u64 d16,#63 @ t0=0xc2....01
|
vshr.u64 d16,#63 @ t0=0xc2....01
|
||||||
vdup.8 q9,d7[7]
|
vdup.8 q9,d7[7]
|
||||||
@ -338,14 +372,14 @@ gcm_init_neon:
|
|||||||
bx lr @ bx lr
|
bx lr @ bx lr
|
||||||
.size gcm_init_neon,.-gcm_init_neon
|
.size gcm_init_neon,.-gcm_init_neon
|
||||||
|
|
||||||
.global gcm_gmult_neon
|
.globl gcm_gmult_neon
|
||||||
.type gcm_gmult_neon,%function
|
.type gcm_gmult_neon,%function
|
||||||
.align 4
|
.align 4
|
||||||
gcm_gmult_neon:
|
gcm_gmult_neon:
|
||||||
vld1.64 d7,[r0,:64]! @ load Xi
|
vld1.64 d7,[r0]! @ load Xi
|
||||||
vld1.64 d6,[r0,:64]!
|
vld1.64 d6,[r0]!
|
||||||
vmov.i64 d29,#0x0000ffffffffffff
|
vmov.i64 d29,#0x0000ffffffffffff
|
||||||
vldmia r1,{d26-d27} @ load twisted H
|
vldmia r1,{d26,d27} @ load twisted H
|
||||||
vmov.i64 d30,#0x00000000ffffffff
|
vmov.i64 d30,#0x00000000ffffffff
|
||||||
#ifdef __ARMEL__
|
#ifdef __ARMEL__
|
||||||
vrev64.8 q3,q3
|
vrev64.8 q3,q3
|
||||||
@ -356,14 +390,14 @@ gcm_gmult_neon:
|
|||||||
b .Lgmult_neon
|
b .Lgmult_neon
|
||||||
.size gcm_gmult_neon,.-gcm_gmult_neon
|
.size gcm_gmult_neon,.-gcm_gmult_neon
|
||||||
|
|
||||||
.global gcm_ghash_neon
|
.globl gcm_ghash_neon
|
||||||
.type gcm_ghash_neon,%function
|
.type gcm_ghash_neon,%function
|
||||||
.align 4
|
.align 4
|
||||||
gcm_ghash_neon:
|
gcm_ghash_neon:
|
||||||
vld1.64 d1,[r0,:64]! @ load Xi
|
vld1.64 d1,[r0]! @ load Xi
|
||||||
vld1.64 d0,[r0,:64]!
|
vld1.64 d0,[r0]!
|
||||||
vmov.i64 d29,#0x0000ffffffffffff
|
vmov.i64 d29,#0x0000ffffffffffff
|
||||||
vldmia r1,{d26-d27} @ load twisted H
|
vldmia r1,{d26,d27} @ load twisted H
|
||||||
vmov.i64 d30,#0x00000000ffffffff
|
vmov.i64 d30,#0x00000000ffffffff
|
||||||
#ifdef __ARMEL__
|
#ifdef __ARMEL__
|
||||||
vrev64.8 q0,q0
|
vrev64.8 q0,q0
|
||||||
@ -520,11 +554,12 @@ gcm_ghash_neon:
|
|||||||
vrev64.8 q0,q0
|
vrev64.8 q0,q0
|
||||||
#endif
|
#endif
|
||||||
sub r0,#16
|
sub r0,#16
|
||||||
vst1.64 d1,[r0,:64]! @ write out Xi
|
vst1.64 d1,[r0]! @ write out Xi
|
||||||
vst1.64 d0,[r0,:64]
|
vst1.64 d0,[r0]
|
||||||
|
|
||||||
bx lr @ bx lr
|
bx lr @ bx lr
|
||||||
.size gcm_ghash_neon,.-gcm_ghash_neon
|
.size gcm_ghash_neon,.-gcm_ghash_neon
|
||||||
#endif
|
#endif
|
||||||
.asciz "GHASH for ARMv4/NEON, CRYPTOGAMS by <appro@openssl.org>"
|
.byte 71,72,65,83,72,32,102,111,114,32,65,82,77,118,52,47,78,69,79,78,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
|
||||||
|
.align 2
|
||||||
.align 2
|
.align 2
|
||||||
|
@ -2,10 +2,12 @@
|
|||||||
/* Do not modify. This file is auto-generated from ghashv8-armx.pl. */
|
/* Do not modify. This file is auto-generated from ghashv8-armx.pl. */
|
||||||
#include "arm_arch.h"
|
#include "arm_arch.h"
|
||||||
|
|
||||||
|
#if __ARM_MAX_ARCH__>=7
|
||||||
.text
|
.text
|
||||||
.fpu neon
|
.fpu neon
|
||||||
.code 32
|
.code 32
|
||||||
.global gcm_init_v8
|
#undef __thumb2__
|
||||||
|
.globl gcm_init_v8
|
||||||
.type gcm_init_v8,%function
|
.type gcm_init_v8,%function
|
||||||
.align 4
|
.align 4
|
||||||
gcm_init_v8:
|
gcm_init_v8:
|
||||||
@ -51,17 +53,16 @@ gcm_init_v8:
|
|||||||
vext.8 q9,q14,q14,#8 @ Karatsuba pre-processing
|
vext.8 q9,q14,q14,#8 @ Karatsuba pre-processing
|
||||||
veor q9,q9,q14
|
veor q9,q9,q14
|
||||||
vext.8 q13,q8,q9,#8 @ pack Karatsuba pre-processed
|
vext.8 q13,q8,q9,#8 @ pack Karatsuba pre-processed
|
||||||
vst1.64 {q13-q14},[r0] @ store Htable[1..2]
|
vst1.64 {q13,q14},[r0]! @ store Htable[1..2]
|
||||||
|
|
||||||
bx lr
|
bx lr
|
||||||
.size gcm_init_v8,.-gcm_init_v8
|
.size gcm_init_v8,.-gcm_init_v8
|
||||||
.global gcm_gmult_v8
|
.globl gcm_gmult_v8
|
||||||
.type gcm_gmult_v8,%function
|
.type gcm_gmult_v8,%function
|
||||||
.align 4
|
.align 4
|
||||||
gcm_gmult_v8:
|
gcm_gmult_v8:
|
||||||
vld1.64 {q9},[r0] @ load Xi
|
vld1.64 {q9},[r0] @ load Xi
|
||||||
vmov.i8 q11,#0xe1
|
vmov.i8 q11,#0xe1
|
||||||
vld1.64 {q12-q13},[r1] @ load twisted H, ...
|
vld1.64 {q12,q13},[r1] @ load twisted H, ...
|
||||||
vshl.u64 q11,q11,#57
|
vshl.u64 q11,q11,#57
|
||||||
#ifndef __ARMEB__
|
#ifndef __ARMEB__
|
||||||
vrev64.8 q9,q9
|
vrev64.8 q9,q9
|
||||||
@ -96,28 +97,28 @@ gcm_gmult_v8:
|
|||||||
|
|
||||||
bx lr
|
bx lr
|
||||||
.size gcm_gmult_v8,.-gcm_gmult_v8
|
.size gcm_gmult_v8,.-gcm_gmult_v8
|
||||||
.global gcm_ghash_v8
|
.globl gcm_ghash_v8
|
||||||
.type gcm_ghash_v8,%function
|
.type gcm_ghash_v8,%function
|
||||||
.align 4
|
.align 4
|
||||||
gcm_ghash_v8:
|
gcm_ghash_v8:
|
||||||
vstmdb sp!,{d8-d15} @ 32-bit ABI says so
|
vstmdb sp!,{d8,d9,d10,d11,d12,d13,d14,d15} @ 32-bit ABI says so
|
||||||
vld1.64 {q0},[r0] @ load [rotated] Xi
|
vld1.64 {q0},[r0] @ load [rotated] Xi
|
||||||
@ "[rotated]" means that
|
@ "[rotated]" means that
|
||||||
@ loaded value would have
|
@ loaded value would have
|
||||||
@ to be rotated in order to
|
@ to be rotated in order to
|
||||||
@ make it appear as in
|
@ make it appear as in
|
||||||
@ alorithm specification
|
@ algorithm specification
|
||||||
subs r3,r3,#32 @ see if r3 is 32 or larger
|
subs r3,r3,#32 @ see if r3 is 32 or larger
|
||||||
mov r12,#16 @ r12 is used as post-
|
mov r12,#16 @ r12 is used as post-
|
||||||
@ increment for input pointer;
|
@ increment for input pointer;
|
||||||
@ as loop is modulo-scheduled
|
@ as loop is modulo-scheduled
|
||||||
@ r12 is zeroed just in time
|
@ r12 is zeroed just in time
|
||||||
@ to preclude oversteping
|
@ to preclude overstepping
|
||||||
@ inp[len], which means that
|
@ inp[len], which means that
|
||||||
@ last block[s] are actually
|
@ last block[s] are actually
|
||||||
@ loaded twice, but last
|
@ loaded twice, but last
|
||||||
@ copy is not processed
|
@ copy is not processed
|
||||||
vld1.64 {q12-q13},[r1]! @ load twisted H, ..., H^2
|
vld1.64 {q12,q13},[r1]! @ load twisted H, ..., H^2
|
||||||
vmov.i8 q11,#0xe1
|
vmov.i8 q11,#0xe1
|
||||||
vld1.64 {q14},[r1]
|
vld1.64 {q14},[r1]
|
||||||
moveq r12,#0 @ is it time to zero r12?
|
moveq r12,#0 @ is it time to zero r12?
|
||||||
@ -225,8 +226,10 @@ gcm_ghash_v8:
|
|||||||
vext.8 q0,q0,q0,#8
|
vext.8 q0,q0,q0,#8
|
||||||
vst1.64 {q0},[r0] @ write out Xi
|
vst1.64 {q0},[r0] @ write out Xi
|
||||||
|
|
||||||
vldmia sp!,{d8-d15} @ 32-bit ABI says so
|
vldmia sp!,{d8,d9,d10,d11,d12,d13,d14,d15} @ 32-bit ABI says so
|
||||||
bx lr
|
bx lr
|
||||||
.size gcm_ghash_v8,.-gcm_ghash_v8
|
.size gcm_ghash_v8,.-gcm_ghash_v8
|
||||||
.asciz "GHASH for ARMv8, CRYPTOGAMS by <appro@openssl.org>"
|
.byte 71,72,65,83,72,32,102,111,114,32,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
|
||||||
.align 2
|
.align 2
|
||||||
|
.align 2
|
||||||
|
#endif
|
||||||
|
2667
secure/lib/libcrypto/arm/keccak1600-armv4.S
Normal file
2667
secure/lib/libcrypto/arm/keccak1600-armv4.S
Normal file
File diff suppressed because it is too large
Load Diff
1170
secure/lib/libcrypto/arm/poly1305-armv4.S
Normal file
1170
secure/lib/libcrypto/arm/poly1305-armv4.S
Normal file
File diff suppressed because it is too large
Load Diff
@ -3,23 +3,32 @@
|
|||||||
#include "arm_arch.h"
|
#include "arm_arch.h"
|
||||||
|
|
||||||
.text
|
.text
|
||||||
|
#if defined(__thumb2__)
|
||||||
|
.syntax unified
|
||||||
|
.thumb
|
||||||
|
#else
|
||||||
.code 32
|
.code 32
|
||||||
|
#endif
|
||||||
|
|
||||||
.global sha1_block_data_order
|
.globl sha1_block_data_order
|
||||||
.type sha1_block_data_order,%function
|
.type sha1_block_data_order,%function
|
||||||
|
|
||||||
.align 5
|
.align 5
|
||||||
sha1_block_data_order:
|
sha1_block_data_order:
|
||||||
#if __ARM_MAX_ARCH__>=7
|
#if __ARM_MAX_ARCH__>=7
|
||||||
sub r3,pc,#8 @ sha1_block_data_order
|
.Lsha1_block:
|
||||||
|
adr r3,.Lsha1_block
|
||||||
ldr r12,.LOPENSSL_armcap
|
ldr r12,.LOPENSSL_armcap
|
||||||
ldr r12,[r3,r12] @ OPENSSL_armcap_P
|
ldr r12,[r3,r12] @ OPENSSL_armcap_P
|
||||||
|
#ifdef __APPLE__
|
||||||
|
ldr r12,[r12]
|
||||||
|
#endif
|
||||||
tst r12,#ARMV8_SHA1
|
tst r12,#ARMV8_SHA1
|
||||||
bne .LARMv8
|
bne .LARMv8
|
||||||
tst r12,#ARMV7_NEON
|
tst r12,#ARMV7_NEON
|
||||||
bne .LNEON
|
bne .LNEON
|
||||||
#endif
|
#endif
|
||||||
stmdb sp!,{r4-r12,lr}
|
stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
|
||||||
add r2,r1,r2,lsl#6 @ r2 to point at the end of r1
|
add r2,r1,r2,lsl#6 @ r2 to point at the end of r1
|
||||||
ldmia r0,{r3,r4,r5,r6,r7}
|
ldmia r0,{r3,r4,r5,r6,r7}
|
||||||
.Lloop:
|
.Lloop:
|
||||||
@ -155,7 +164,12 @@ sha1_block_data_order:
|
|||||||
eor r10,r10,r7,ror#2 @ F_00_19(B,C,D)
|
eor r10,r10,r7,ror#2 @ F_00_19(B,C,D)
|
||||||
str r9,[r14,#-4]!
|
str r9,[r14,#-4]!
|
||||||
add r3,r3,r10 @ E+=F_00_19(B,C,D)
|
add r3,r3,r10 @ E+=F_00_19(B,C,D)
|
||||||
|
#if defined(__thumb2__)
|
||||||
|
mov r12,sp
|
||||||
|
teq r14,r12
|
||||||
|
#else
|
||||||
teq r14,sp
|
teq r14,sp
|
||||||
|
#endif
|
||||||
bne .L_00_15 @ [((11+4)*5+2)*3]
|
bne .L_00_15 @ [((11+4)*5+2)*3]
|
||||||
sub sp,sp,#25*4
|
sub sp,sp,#25*4
|
||||||
#if __ARM_ARCH__<7
|
#if __ARM_ARCH__<7
|
||||||
@ -335,7 +349,12 @@ sha1_block_data_order:
|
|||||||
@ F_xx_xx
|
@ F_xx_xx
|
||||||
add r3,r3,r9 @ E+=X[i]
|
add r3,r3,r9 @ E+=X[i]
|
||||||
add r3,r3,r10 @ E+=F_20_39(B,C,D)
|
add r3,r3,r10 @ E+=F_20_39(B,C,D)
|
||||||
|
#if defined(__thumb2__)
|
||||||
|
mov r12,sp
|
||||||
|
teq r14,r12
|
||||||
|
#else
|
||||||
teq r14,sp @ preserve carry
|
teq r14,sp @ preserve carry
|
||||||
|
#endif
|
||||||
bne .L_20_39_or_60_79 @ [+((12+3)*5+2)*4]
|
bne .L_20_39_or_60_79 @ [+((12+3)*5+2)*4]
|
||||||
bcs .L_done @ [+((12+3)*5+2)*4], spare 300 bytes
|
bcs .L_done @ [+((12+3)*5+2)*4], spare 300 bytes
|
||||||
|
|
||||||
@ -427,7 +446,12 @@ sha1_block_data_order:
|
|||||||
add r3,r3,r9 @ E+=X[i]
|
add r3,r3,r9 @ E+=X[i]
|
||||||
add r3,r3,r10 @ E+=F_40_59(B,C,D)
|
add r3,r3,r10 @ E+=F_40_59(B,C,D)
|
||||||
add r3,r3,r11,ror#2
|
add r3,r3,r11,ror#2
|
||||||
|
#if defined(__thumb2__)
|
||||||
|
mov r12,sp
|
||||||
|
teq r14,r12
|
||||||
|
#else
|
||||||
teq r14,sp
|
teq r14,sp
|
||||||
|
#endif
|
||||||
bne .L_40_59 @ [+((12+5)*5+2)*4]
|
bne .L_40_59 @ [+((12+5)*5+2)*4]
|
||||||
|
|
||||||
ldr r8,.LK_60_79
|
ldr r8,.LK_60_79
|
||||||
@ -447,9 +471,9 @@ sha1_block_data_order:
|
|||||||
bne .Lloop @ [+18], total 1307
|
bne .Lloop @ [+18], total 1307
|
||||||
|
|
||||||
#if __ARM_ARCH__>=5
|
#if __ARM_ARCH__>=5
|
||||||
ldmia sp!,{r4-r12,pc}
|
ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,pc}
|
||||||
#else
|
#else
|
||||||
ldmia sp!,{r4-r12,lr}
|
ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
|
||||||
tst lr,#1
|
tst lr,#1
|
||||||
moveq pc,lr @ be binary compatible with V4, yet
|
moveq pc,lr @ be binary compatible with V4, yet
|
||||||
.word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
.word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
||||||
@ -463,9 +487,10 @@ sha1_block_data_order:
|
|||||||
.LK_60_79:.word 0xca62c1d6
|
.LK_60_79:.word 0xca62c1d6
|
||||||
#if __ARM_MAX_ARCH__>=7
|
#if __ARM_MAX_ARCH__>=7
|
||||||
.LOPENSSL_armcap:
|
.LOPENSSL_armcap:
|
||||||
.word OPENSSL_armcap_P-sha1_block_data_order
|
.word OPENSSL_armcap_P-.Lsha1_block
|
||||||
#endif
|
#endif
|
||||||
.asciz "SHA1 block transform for ARMv4/NEON/ARMv8, CRYPTOGAMS by <appro@openssl.org>"
|
.byte 83,72,65,49,32,98,108,111,99,107,32,116,114,97,110,115,102,111,114,109,32,102,111,114,32,65,82,77,118,52,47,78,69,79,78,47,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
|
||||||
|
.align 2
|
||||||
.align 5
|
.align 5
|
||||||
#if __ARM_MAX_ARCH__>=7
|
#if __ARM_MAX_ARCH__>=7
|
||||||
.arch armv7-a
|
.arch armv7-a
|
||||||
@ -475,21 +500,21 @@ sha1_block_data_order:
|
|||||||
.align 4
|
.align 4
|
||||||
sha1_block_data_order_neon:
|
sha1_block_data_order_neon:
|
||||||
.LNEON:
|
.LNEON:
|
||||||
stmdb sp!,{r4-r12,lr}
|
stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
|
||||||
add r2,r1,r2,lsl#6 @ r2 to point at the end of r1
|
add r2,r1,r2,lsl#6 @ r2 to point at the end of r1
|
||||||
@ dmb @ errata #451034 on early Cortex A8
|
@ dmb @ errata #451034 on early Cortex A8
|
||||||
@ vstmdb sp!,{d8-d15} @ ABI specification says so
|
@ vstmdb sp!,{d8-d15} @ ABI specification says so
|
||||||
mov r14,sp
|
mov r14,sp
|
||||||
sub sp,sp,#64 @ alloca
|
sub r12,sp,#64
|
||||||
adr r8,.LK_00_19
|
adr r8,.LK_00_19
|
||||||
bic sp,sp,#15 @ align for 128-bit stores
|
bic r12,r12,#15 @ align for 128-bit stores
|
||||||
|
|
||||||
ldmia r0,{r3,r4,r5,r6,r7} @ load context
|
ldmia r0,{r3,r4,r5,r6,r7} @ load context
|
||||||
mov r12,sp
|
mov sp,r12 @ alloca
|
||||||
|
|
||||||
vld1.8 {q0-q1},[r1]! @ handles unaligned
|
vld1.8 {q0,q1},[r1]! @ handles unaligned
|
||||||
veor q15,q15,q15
|
veor q15,q15,q15
|
||||||
vld1.8 {q2-q3},[r1]!
|
vld1.8 {q2,q3},[r1]!
|
||||||
vld1.32 {d28[],d29[]},[r8,:32]! @ load K_00_19
|
vld1.32 {d28[],d29[]},[r8,:32]! @ load K_00_19
|
||||||
vrev32.8 q0,q0 @ yes, even on
|
vrev32.8 q0,q0 @ yes, even on
|
||||||
vrev32.8 q1,q1 @ big-endian...
|
vrev32.8 q1,q1 @ big-endian...
|
||||||
@ -1178,11 +1203,12 @@ sha1_block_data_order_neon:
|
|||||||
sub r12,r12,#64
|
sub r12,r12,#64
|
||||||
teq r1,r2
|
teq r1,r2
|
||||||
sub r8,r8,#16
|
sub r8,r8,#16
|
||||||
|
it eq
|
||||||
subeq r1,r1,#64
|
subeq r1,r1,#64
|
||||||
vld1.8 {q0-q1},[r1]!
|
vld1.8 {q0,q1},[r1]!
|
||||||
ldr r9,[sp,#4]
|
ldr r9,[sp,#4]
|
||||||
eor r11,r10,r6
|
eor r11,r10,r6
|
||||||
vld1.8 {q2-q3},[r1]!
|
vld1.8 {q2,q3},[r1]!
|
||||||
add r3,r3,r4,ror#27
|
add r3,r3,r4,ror#27
|
||||||
mov r5,r5,ror#2
|
mov r5,r5,ror#2
|
||||||
vld1.32 {d28[],d29[]},[r8,:32]!
|
vld1.32 {d28[],d29[]},[r8,:32]!
|
||||||
@ -1307,23 +1333,33 @@ sha1_block_data_order_neon:
|
|||||||
add r4,r4,r10
|
add r4,r4,r10
|
||||||
add r5,r5,r11
|
add r5,r5,r11
|
||||||
add r6,r6,r12
|
add r6,r6,r12
|
||||||
|
it eq
|
||||||
moveq sp,r14
|
moveq sp,r14
|
||||||
add r7,r7,r9
|
add r7,r7,r9
|
||||||
|
it ne
|
||||||
ldrne r9,[sp]
|
ldrne r9,[sp]
|
||||||
stmia r0,{r3,r4,r5,r6,r7}
|
stmia r0,{r3,r4,r5,r6,r7}
|
||||||
|
itt ne
|
||||||
addne r12,sp,#3*16
|
addne r12,sp,#3*16
|
||||||
bne .Loop_neon
|
bne .Loop_neon
|
||||||
|
|
||||||
@ vldmia sp!,{d8-d15}
|
@ vldmia sp!,{d8-d15}
|
||||||
ldmia sp!,{r4-r12,pc}
|
ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,pc}
|
||||||
.size sha1_block_data_order_neon,.-sha1_block_data_order_neon
|
.size sha1_block_data_order_neon,.-sha1_block_data_order_neon
|
||||||
#endif
|
#endif
|
||||||
#if __ARM_MAX_ARCH__>=7
|
#if __ARM_MAX_ARCH__>=7
|
||||||
|
|
||||||
|
# if defined(__thumb2__)
|
||||||
|
# define INST(a,b,c,d) .byte c,d|0xf,a,b
|
||||||
|
# else
|
||||||
|
# define INST(a,b,c,d) .byte a,b,c,d|0x10
|
||||||
|
# endif
|
||||||
|
|
||||||
.type sha1_block_data_order_armv8,%function
|
.type sha1_block_data_order_armv8,%function
|
||||||
.align 5
|
.align 5
|
||||||
sha1_block_data_order_armv8:
|
sha1_block_data_order_armv8:
|
||||||
.LARMv8:
|
.LARMv8:
|
||||||
vstmdb sp!,{d8-d15} @ ABI specification says so
|
vstmdb sp!,{d8,d9,d10,d11,d12,d13,d14,d15} @ ABI specification says so
|
||||||
|
|
||||||
veor q1,q1,q1
|
veor q1,q1,q1
|
||||||
adr r3,.LK_00_19
|
adr r3,.LK_00_19
|
||||||
@ -1336,8 +1372,8 @@ sha1_block_data_order_armv8:
|
|||||||
vld1.32 {d22[],d23[]},[r3,:32]
|
vld1.32 {d22[],d23[]},[r3,:32]
|
||||||
|
|
||||||
.Loop_v8:
|
.Loop_v8:
|
||||||
vld1.8 {q4-q5},[r1]!
|
vld1.8 {q4,q5},[r1]!
|
||||||
vld1.8 {q6-q7},[r1]!
|
vld1.8 {q6,q7},[r1]!
|
||||||
vrev32.8 q4,q4
|
vrev32.8 q4,q4
|
||||||
vrev32.8 q5,q5
|
vrev32.8 q5,q5
|
||||||
|
|
||||||
@ -1348,98 +1384,98 @@ sha1_block_data_order_armv8:
|
|||||||
|
|
||||||
vadd.i32 q13,q8,q5
|
vadd.i32 q13,q8,q5
|
||||||
vrev32.8 q7,q7
|
vrev32.8 q7,q7
|
||||||
.byte 0xc0,0x62,0xb9,0xf3 @ sha1h q3,q0 @ 0
|
INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 0
|
||||||
.byte 0x68,0x0c,0x02,0xf2 @ sha1c q0,q1,q12
|
INST(0x68,0x0c,0x02,0xe2) @ sha1c q0,q1,q12
|
||||||
vadd.i32 q12,q8,q6
|
vadd.i32 q12,q8,q6
|
||||||
.byte 0x4c,0x8c,0x3a,0xf2 @ sha1su0 q4,q5,q6
|
INST(0x4c,0x8c,0x3a,0xe2) @ sha1su0 q4,q5,q6
|
||||||
.byte 0xc0,0x42,0xb9,0xf3 @ sha1h q2,q0 @ 1
|
INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 1
|
||||||
.byte 0x6a,0x0c,0x06,0xf2 @ sha1c q0,q3,q13
|
INST(0x6a,0x0c,0x06,0xe2) @ sha1c q0,q3,q13
|
||||||
vadd.i32 q13,q8,q7
|
vadd.i32 q13,q8,q7
|
||||||
.byte 0x8e,0x83,0xba,0xf3 @ sha1su1 q4,q7
|
INST(0x8e,0x83,0xba,0xf3) @ sha1su1 q4,q7
|
||||||
.byte 0x4e,0xac,0x3c,0xf2 @ sha1su0 q5,q6,q7
|
INST(0x4e,0xac,0x3c,0xe2) @ sha1su0 q5,q6,q7
|
||||||
.byte 0xc0,0x62,0xb9,0xf3 @ sha1h q3,q0 @ 2
|
INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 2
|
||||||
.byte 0x68,0x0c,0x04,0xf2 @ sha1c q0,q2,q12
|
INST(0x68,0x0c,0x04,0xe2) @ sha1c q0,q2,q12
|
||||||
vadd.i32 q12,q8,q4
|
vadd.i32 q12,q8,q4
|
||||||
.byte 0x88,0xa3,0xba,0xf3 @ sha1su1 q5,q4
|
INST(0x88,0xa3,0xba,0xf3) @ sha1su1 q5,q4
|
||||||
.byte 0x48,0xcc,0x3e,0xf2 @ sha1su0 q6,q7,q4
|
INST(0x48,0xcc,0x3e,0xe2) @ sha1su0 q6,q7,q4
|
||||||
.byte 0xc0,0x42,0xb9,0xf3 @ sha1h q2,q0 @ 3
|
INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 3
|
||||||
.byte 0x6a,0x0c,0x06,0xf2 @ sha1c q0,q3,q13
|
INST(0x6a,0x0c,0x06,0xe2) @ sha1c q0,q3,q13
|
||||||
vadd.i32 q13,q9,q5
|
vadd.i32 q13,q9,q5
|
||||||
.byte 0x8a,0xc3,0xba,0xf3 @ sha1su1 q6,q5
|
INST(0x8a,0xc3,0xba,0xf3) @ sha1su1 q6,q5
|
||||||
.byte 0x4a,0xec,0x38,0xf2 @ sha1su0 q7,q4,q5
|
INST(0x4a,0xec,0x38,0xe2) @ sha1su0 q7,q4,q5
|
||||||
.byte 0xc0,0x62,0xb9,0xf3 @ sha1h q3,q0 @ 4
|
INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 4
|
||||||
.byte 0x68,0x0c,0x04,0xf2 @ sha1c q0,q2,q12
|
INST(0x68,0x0c,0x04,0xe2) @ sha1c q0,q2,q12
|
||||||
vadd.i32 q12,q9,q6
|
vadd.i32 q12,q9,q6
|
||||||
.byte 0x8c,0xe3,0xba,0xf3 @ sha1su1 q7,q6
|
INST(0x8c,0xe3,0xba,0xf3) @ sha1su1 q7,q6
|
||||||
.byte 0x4c,0x8c,0x3a,0xf2 @ sha1su0 q4,q5,q6
|
INST(0x4c,0x8c,0x3a,0xe2) @ sha1su0 q4,q5,q6
|
||||||
.byte 0xc0,0x42,0xb9,0xf3 @ sha1h q2,q0 @ 5
|
INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 5
|
||||||
.byte 0x6a,0x0c,0x16,0xf2 @ sha1p q0,q3,q13
|
INST(0x6a,0x0c,0x16,0xe2) @ sha1p q0,q3,q13
|
||||||
vadd.i32 q13,q9,q7
|
vadd.i32 q13,q9,q7
|
||||||
.byte 0x8e,0x83,0xba,0xf3 @ sha1su1 q4,q7
|
INST(0x8e,0x83,0xba,0xf3) @ sha1su1 q4,q7
|
||||||
.byte 0x4e,0xac,0x3c,0xf2 @ sha1su0 q5,q6,q7
|
INST(0x4e,0xac,0x3c,0xe2) @ sha1su0 q5,q6,q7
|
||||||
.byte 0xc0,0x62,0xb9,0xf3 @ sha1h q3,q0 @ 6
|
INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 6
|
||||||
.byte 0x68,0x0c,0x14,0xf2 @ sha1p q0,q2,q12
|
INST(0x68,0x0c,0x14,0xe2) @ sha1p q0,q2,q12
|
||||||
vadd.i32 q12,q9,q4
|
vadd.i32 q12,q9,q4
|
||||||
.byte 0x88,0xa3,0xba,0xf3 @ sha1su1 q5,q4
|
INST(0x88,0xa3,0xba,0xf3) @ sha1su1 q5,q4
|
||||||
.byte 0x48,0xcc,0x3e,0xf2 @ sha1su0 q6,q7,q4
|
INST(0x48,0xcc,0x3e,0xe2) @ sha1su0 q6,q7,q4
|
||||||
.byte 0xc0,0x42,0xb9,0xf3 @ sha1h q2,q0 @ 7
|
INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 7
|
||||||
.byte 0x6a,0x0c,0x16,0xf2 @ sha1p q0,q3,q13
|
INST(0x6a,0x0c,0x16,0xe2) @ sha1p q0,q3,q13
|
||||||
vadd.i32 q13,q9,q5
|
vadd.i32 q13,q9,q5
|
||||||
.byte 0x8a,0xc3,0xba,0xf3 @ sha1su1 q6,q5
|
INST(0x8a,0xc3,0xba,0xf3) @ sha1su1 q6,q5
|
||||||
.byte 0x4a,0xec,0x38,0xf2 @ sha1su0 q7,q4,q5
|
INST(0x4a,0xec,0x38,0xe2) @ sha1su0 q7,q4,q5
|
||||||
.byte 0xc0,0x62,0xb9,0xf3 @ sha1h q3,q0 @ 8
|
INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 8
|
||||||
.byte 0x68,0x0c,0x14,0xf2 @ sha1p q0,q2,q12
|
INST(0x68,0x0c,0x14,0xe2) @ sha1p q0,q2,q12
|
||||||
vadd.i32 q12,q10,q6
|
vadd.i32 q12,q10,q6
|
||||||
.byte 0x8c,0xe3,0xba,0xf3 @ sha1su1 q7,q6
|
INST(0x8c,0xe3,0xba,0xf3) @ sha1su1 q7,q6
|
||||||
.byte 0x4c,0x8c,0x3a,0xf2 @ sha1su0 q4,q5,q6
|
INST(0x4c,0x8c,0x3a,0xe2) @ sha1su0 q4,q5,q6
|
||||||
.byte 0xc0,0x42,0xb9,0xf3 @ sha1h q2,q0 @ 9
|
INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 9
|
||||||
.byte 0x6a,0x0c,0x16,0xf2 @ sha1p q0,q3,q13
|
INST(0x6a,0x0c,0x16,0xe2) @ sha1p q0,q3,q13
|
||||||
vadd.i32 q13,q10,q7
|
vadd.i32 q13,q10,q7
|
||||||
.byte 0x8e,0x83,0xba,0xf3 @ sha1su1 q4,q7
|
INST(0x8e,0x83,0xba,0xf3) @ sha1su1 q4,q7
|
||||||
.byte 0x4e,0xac,0x3c,0xf2 @ sha1su0 q5,q6,q7
|
INST(0x4e,0xac,0x3c,0xe2) @ sha1su0 q5,q6,q7
|
||||||
.byte 0xc0,0x62,0xb9,0xf3 @ sha1h q3,q0 @ 10
|
INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 10
|
||||||
.byte 0x68,0x0c,0x24,0xf2 @ sha1m q0,q2,q12
|
INST(0x68,0x0c,0x24,0xe2) @ sha1m q0,q2,q12
|
||||||
vadd.i32 q12,q10,q4
|
vadd.i32 q12,q10,q4
|
||||||
.byte 0x88,0xa3,0xba,0xf3 @ sha1su1 q5,q4
|
INST(0x88,0xa3,0xba,0xf3) @ sha1su1 q5,q4
|
||||||
.byte 0x48,0xcc,0x3e,0xf2 @ sha1su0 q6,q7,q4
|
INST(0x48,0xcc,0x3e,0xe2) @ sha1su0 q6,q7,q4
|
||||||
.byte 0xc0,0x42,0xb9,0xf3 @ sha1h q2,q0 @ 11
|
INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 11
|
||||||
.byte 0x6a,0x0c,0x26,0xf2 @ sha1m q0,q3,q13
|
INST(0x6a,0x0c,0x26,0xe2) @ sha1m q0,q3,q13
|
||||||
vadd.i32 q13,q10,q5
|
vadd.i32 q13,q10,q5
|
||||||
.byte 0x8a,0xc3,0xba,0xf3 @ sha1su1 q6,q5
|
INST(0x8a,0xc3,0xba,0xf3) @ sha1su1 q6,q5
|
||||||
.byte 0x4a,0xec,0x38,0xf2 @ sha1su0 q7,q4,q5
|
INST(0x4a,0xec,0x38,0xe2) @ sha1su0 q7,q4,q5
|
||||||
.byte 0xc0,0x62,0xb9,0xf3 @ sha1h q3,q0 @ 12
|
INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 12
|
||||||
.byte 0x68,0x0c,0x24,0xf2 @ sha1m q0,q2,q12
|
INST(0x68,0x0c,0x24,0xe2) @ sha1m q0,q2,q12
|
||||||
vadd.i32 q12,q10,q6
|
vadd.i32 q12,q10,q6
|
||||||
.byte 0x8c,0xe3,0xba,0xf3 @ sha1su1 q7,q6
|
INST(0x8c,0xe3,0xba,0xf3) @ sha1su1 q7,q6
|
||||||
.byte 0x4c,0x8c,0x3a,0xf2 @ sha1su0 q4,q5,q6
|
INST(0x4c,0x8c,0x3a,0xe2) @ sha1su0 q4,q5,q6
|
||||||
.byte 0xc0,0x42,0xb9,0xf3 @ sha1h q2,q0 @ 13
|
INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 13
|
||||||
.byte 0x6a,0x0c,0x26,0xf2 @ sha1m q0,q3,q13
|
INST(0x6a,0x0c,0x26,0xe2) @ sha1m q0,q3,q13
|
||||||
vadd.i32 q13,q11,q7
|
vadd.i32 q13,q11,q7
|
||||||
.byte 0x8e,0x83,0xba,0xf3 @ sha1su1 q4,q7
|
INST(0x8e,0x83,0xba,0xf3) @ sha1su1 q4,q7
|
||||||
.byte 0x4e,0xac,0x3c,0xf2 @ sha1su0 q5,q6,q7
|
INST(0x4e,0xac,0x3c,0xe2) @ sha1su0 q5,q6,q7
|
||||||
.byte 0xc0,0x62,0xb9,0xf3 @ sha1h q3,q0 @ 14
|
INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 14
|
||||||
.byte 0x68,0x0c,0x24,0xf2 @ sha1m q0,q2,q12
|
INST(0x68,0x0c,0x24,0xe2) @ sha1m q0,q2,q12
|
||||||
vadd.i32 q12,q11,q4
|
vadd.i32 q12,q11,q4
|
||||||
.byte 0x88,0xa3,0xba,0xf3 @ sha1su1 q5,q4
|
INST(0x88,0xa3,0xba,0xf3) @ sha1su1 q5,q4
|
||||||
.byte 0x48,0xcc,0x3e,0xf2 @ sha1su0 q6,q7,q4
|
INST(0x48,0xcc,0x3e,0xe2) @ sha1su0 q6,q7,q4
|
||||||
.byte 0xc0,0x42,0xb9,0xf3 @ sha1h q2,q0 @ 15
|
INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 15
|
||||||
.byte 0x6a,0x0c,0x16,0xf2 @ sha1p q0,q3,q13
|
INST(0x6a,0x0c,0x16,0xe2) @ sha1p q0,q3,q13
|
||||||
vadd.i32 q13,q11,q5
|
vadd.i32 q13,q11,q5
|
||||||
.byte 0x8a,0xc3,0xba,0xf3 @ sha1su1 q6,q5
|
INST(0x8a,0xc3,0xba,0xf3) @ sha1su1 q6,q5
|
||||||
.byte 0x4a,0xec,0x38,0xf2 @ sha1su0 q7,q4,q5
|
INST(0x4a,0xec,0x38,0xe2) @ sha1su0 q7,q4,q5
|
||||||
.byte 0xc0,0x62,0xb9,0xf3 @ sha1h q3,q0 @ 16
|
INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 16
|
||||||
.byte 0x68,0x0c,0x14,0xf2 @ sha1p q0,q2,q12
|
INST(0x68,0x0c,0x14,0xe2) @ sha1p q0,q2,q12
|
||||||
vadd.i32 q12,q11,q6
|
vadd.i32 q12,q11,q6
|
||||||
.byte 0x8c,0xe3,0xba,0xf3 @ sha1su1 q7,q6
|
INST(0x8c,0xe3,0xba,0xf3) @ sha1su1 q7,q6
|
||||||
.byte 0xc0,0x42,0xb9,0xf3 @ sha1h q2,q0 @ 17
|
INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 17
|
||||||
.byte 0x6a,0x0c,0x16,0xf2 @ sha1p q0,q3,q13
|
INST(0x6a,0x0c,0x16,0xe2) @ sha1p q0,q3,q13
|
||||||
vadd.i32 q13,q11,q7
|
vadd.i32 q13,q11,q7
|
||||||
|
|
||||||
.byte 0xc0,0x62,0xb9,0xf3 @ sha1h q3,q0 @ 18
|
INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 18
|
||||||
.byte 0x68,0x0c,0x14,0xf2 @ sha1p q0,q2,q12
|
INST(0x68,0x0c,0x14,0xe2) @ sha1p q0,q2,q12
|
||||||
|
|
||||||
.byte 0xc0,0x42,0xb9,0xf3 @ sha1h q2,q0 @ 19
|
INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 19
|
||||||
.byte 0x6a,0x0c,0x16,0xf2 @ sha1p q0,q3,q13
|
INST(0x6a,0x0c,0x16,0xe2) @ sha1p q0,q3,q13
|
||||||
|
|
||||||
vadd.i32 q1,q1,q2
|
vadd.i32 q1,q1,q2
|
||||||
vadd.i32 q0,q0,q14
|
vadd.i32 q0,q0,q14
|
||||||
@ -1448,7 +1484,7 @@ sha1_block_data_order_armv8:
|
|||||||
vst1.32 {q0},[r0]!
|
vst1.32 {q0},[r0]!
|
||||||
vst1.32 {d2[0]},[r0]
|
vst1.32 {d2[0]},[r0]
|
||||||
|
|
||||||
vldmia sp!,{d8-d15}
|
vldmia sp!,{d8,d9,d10,d11,d12,d13,d14,d15}
|
||||||
bx lr @ bx lr
|
bx lr @ bx lr
|
||||||
.size sha1_block_data_order_armv8,.-sha1_block_data_order_armv8
|
.size sha1_block_data_order_armv8,.-sha1_block_data_order_armv8
|
||||||
#endif
|
#endif
|
||||||
|
@ -1,5 +1,12 @@
|
|||||||
/* $FreeBSD$ */
|
/* $FreeBSD$ */
|
||||||
/* Do not modify. This file is auto-generated from sha256-armv4.pl. */
|
/* Do not modify. This file is auto-generated from sha256-armv4.pl. */
|
||||||
|
@ Copyright 2007-2018 The OpenSSL Project Authors. All Rights Reserved.
|
||||||
|
@
|
||||||
|
@ Licensed under the OpenSSL license (the "License"). You may not use
|
||||||
|
@ this file except in compliance with the License. You can obtain a copy
|
||||||
|
@ in the file LICENSE in the source distribution or at
|
||||||
|
@ https://www.openssl.org/source/license.html
|
||||||
|
|
||||||
|
|
||||||
@ ====================================================================
|
@ ====================================================================
|
||||||
@ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
|
@ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
|
||||||
@ -46,16 +53,12 @@
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
.text
|
.text
|
||||||
#if __ARM_ARCH__<7
|
#if defined(__thumb2__)
|
||||||
.code 32
|
|
||||||
#else
|
|
||||||
.syntax unified
|
.syntax unified
|
||||||
# ifdef __thumb2__
|
|
||||||
.thumb
|
.thumb
|
||||||
#else
|
#else
|
||||||
.code 32
|
.code 32
|
||||||
#endif
|
#endif
|
||||||
#endif
|
|
||||||
|
|
||||||
.type K256,%object
|
.type K256,%object
|
||||||
.align 5
|
.align 5
|
||||||
@ -80,21 +83,25 @@ K256:
|
|||||||
.word 0 @ terminator
|
.word 0 @ terminator
|
||||||
#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
|
#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
|
||||||
.LOPENSSL_armcap:
|
.LOPENSSL_armcap:
|
||||||
.word OPENSSL_armcap_P-sha256_block_data_order
|
.word OPENSSL_armcap_P-.Lsha256_block_data_order
|
||||||
#endif
|
#endif
|
||||||
.align 5
|
.align 5
|
||||||
|
|
||||||
.global sha256_block_data_order
|
.globl sha256_block_data_order
|
||||||
.type sha256_block_data_order,%function
|
.type sha256_block_data_order,%function
|
||||||
sha256_block_data_order:
|
sha256_block_data_order:
|
||||||
#if __ARM_ARCH__<7
|
.Lsha256_block_data_order:
|
||||||
|
#if __ARM_ARCH__<7 && !defined(__thumb2__)
|
||||||
sub r3,pc,#8 @ sha256_block_data_order
|
sub r3,pc,#8 @ sha256_block_data_order
|
||||||
#else
|
#else
|
||||||
adr r3,.
|
adr r3,.Lsha256_block_data_order
|
||||||
#endif
|
#endif
|
||||||
#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
|
#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
|
||||||
ldr r12,.LOPENSSL_armcap
|
ldr r12,.LOPENSSL_armcap
|
||||||
ldr r12,[r3,r12] @ OPENSSL_armcap_P
|
ldr r12,[r3,r12] @ OPENSSL_armcap_P
|
||||||
|
#ifdef __APPLE__
|
||||||
|
ldr r12,[r12]
|
||||||
|
#endif
|
||||||
tst r12,#ARMV8_SHA256
|
tst r12,#ARMV8_SHA256
|
||||||
bne .LARMv8
|
bne .LARMv8
|
||||||
tst r12,#ARMV7_NEON
|
tst r12,#ARMV7_NEON
|
||||||
@ -121,7 +128,9 @@ sha256_block_data_order:
|
|||||||
eor r0,r8,r8,ror#5
|
eor r0,r8,r8,ror#5
|
||||||
add r4,r4,r12 @ h+=Maj(a,b,c) from the past
|
add r4,r4,r12 @ h+=Maj(a,b,c) from the past
|
||||||
eor r0,r0,r8,ror#19 @ Sigma1(e)
|
eor r0,r0,r8,ror#19 @ Sigma1(e)
|
||||||
|
# ifndef __ARMEB__
|
||||||
rev r2,r2
|
rev r2,r2
|
||||||
|
# endif
|
||||||
#else
|
#else
|
||||||
@ ldrb r2,[r1,#3] @ 0
|
@ ldrb r2,[r1,#3] @ 0
|
||||||
add r4,r4,r12 @ h+=Maj(a,b,c) from the past
|
add r4,r4,r12 @ h+=Maj(a,b,c) from the past
|
||||||
@ -177,7 +186,9 @@ sha256_block_data_order:
|
|||||||
eor r0,r7,r7,ror#5
|
eor r0,r7,r7,ror#5
|
||||||
add r11,r11,r3 @ h+=Maj(a,b,c) from the past
|
add r11,r11,r3 @ h+=Maj(a,b,c) from the past
|
||||||
eor r0,r0,r7,ror#19 @ Sigma1(e)
|
eor r0,r0,r7,ror#19 @ Sigma1(e)
|
||||||
|
# ifndef __ARMEB__
|
||||||
rev r2,r2
|
rev r2,r2
|
||||||
|
# endif
|
||||||
#else
|
#else
|
||||||
@ ldrb r2,[r1,#3] @ 1
|
@ ldrb r2,[r1,#3] @ 1
|
||||||
add r11,r11,r3 @ h+=Maj(a,b,c) from the past
|
add r11,r11,r3 @ h+=Maj(a,b,c) from the past
|
||||||
@ -233,7 +244,9 @@ sha256_block_data_order:
|
|||||||
eor r0,r6,r6,ror#5
|
eor r0,r6,r6,ror#5
|
||||||
add r10,r10,r12 @ h+=Maj(a,b,c) from the past
|
add r10,r10,r12 @ h+=Maj(a,b,c) from the past
|
||||||
eor r0,r0,r6,ror#19 @ Sigma1(e)
|
eor r0,r0,r6,ror#19 @ Sigma1(e)
|
||||||
|
# ifndef __ARMEB__
|
||||||
rev r2,r2
|
rev r2,r2
|
||||||
|
# endif
|
||||||
#else
|
#else
|
||||||
@ ldrb r2,[r1,#3] @ 2
|
@ ldrb r2,[r1,#3] @ 2
|
||||||
add r10,r10,r12 @ h+=Maj(a,b,c) from the past
|
add r10,r10,r12 @ h+=Maj(a,b,c) from the past
|
||||||
@ -289,7 +302,9 @@ sha256_block_data_order:
|
|||||||
eor r0,r5,r5,ror#5
|
eor r0,r5,r5,ror#5
|
||||||
add r9,r9,r3 @ h+=Maj(a,b,c) from the past
|
add r9,r9,r3 @ h+=Maj(a,b,c) from the past
|
||||||
eor r0,r0,r5,ror#19 @ Sigma1(e)
|
eor r0,r0,r5,ror#19 @ Sigma1(e)
|
||||||
|
# ifndef __ARMEB__
|
||||||
rev r2,r2
|
rev r2,r2
|
||||||
|
# endif
|
||||||
#else
|
#else
|
||||||
@ ldrb r2,[r1,#3] @ 3
|
@ ldrb r2,[r1,#3] @ 3
|
||||||
add r9,r9,r3 @ h+=Maj(a,b,c) from the past
|
add r9,r9,r3 @ h+=Maj(a,b,c) from the past
|
||||||
@ -345,7 +360,9 @@ sha256_block_data_order:
|
|||||||
eor r0,r4,r4,ror#5
|
eor r0,r4,r4,ror#5
|
||||||
add r8,r8,r12 @ h+=Maj(a,b,c) from the past
|
add r8,r8,r12 @ h+=Maj(a,b,c) from the past
|
||||||
eor r0,r0,r4,ror#19 @ Sigma1(e)
|
eor r0,r0,r4,ror#19 @ Sigma1(e)
|
||||||
|
# ifndef __ARMEB__
|
||||||
rev r2,r2
|
rev r2,r2
|
||||||
|
# endif
|
||||||
#else
|
#else
|
||||||
@ ldrb r2,[r1,#3] @ 4
|
@ ldrb r2,[r1,#3] @ 4
|
||||||
add r8,r8,r12 @ h+=Maj(a,b,c) from the past
|
add r8,r8,r12 @ h+=Maj(a,b,c) from the past
|
||||||
@ -401,7 +418,9 @@ sha256_block_data_order:
|
|||||||
eor r0,r11,r11,ror#5
|
eor r0,r11,r11,ror#5
|
||||||
add r7,r7,r3 @ h+=Maj(a,b,c) from the past
|
add r7,r7,r3 @ h+=Maj(a,b,c) from the past
|
||||||
eor r0,r0,r11,ror#19 @ Sigma1(e)
|
eor r0,r0,r11,ror#19 @ Sigma1(e)
|
||||||
|
# ifndef __ARMEB__
|
||||||
rev r2,r2
|
rev r2,r2
|
||||||
|
# endif
|
||||||
#else
|
#else
|
||||||
@ ldrb r2,[r1,#3] @ 5
|
@ ldrb r2,[r1,#3] @ 5
|
||||||
add r7,r7,r3 @ h+=Maj(a,b,c) from the past
|
add r7,r7,r3 @ h+=Maj(a,b,c) from the past
|
||||||
@ -457,7 +476,9 @@ sha256_block_data_order:
|
|||||||
eor r0,r10,r10,ror#5
|
eor r0,r10,r10,ror#5
|
||||||
add r6,r6,r12 @ h+=Maj(a,b,c) from the past
|
add r6,r6,r12 @ h+=Maj(a,b,c) from the past
|
||||||
eor r0,r0,r10,ror#19 @ Sigma1(e)
|
eor r0,r0,r10,ror#19 @ Sigma1(e)
|
||||||
|
# ifndef __ARMEB__
|
||||||
rev r2,r2
|
rev r2,r2
|
||||||
|
# endif
|
||||||
#else
|
#else
|
||||||
@ ldrb r2,[r1,#3] @ 6
|
@ ldrb r2,[r1,#3] @ 6
|
||||||
add r6,r6,r12 @ h+=Maj(a,b,c) from the past
|
add r6,r6,r12 @ h+=Maj(a,b,c) from the past
|
||||||
@ -513,7 +534,9 @@ sha256_block_data_order:
|
|||||||
eor r0,r9,r9,ror#5
|
eor r0,r9,r9,ror#5
|
||||||
add r5,r5,r3 @ h+=Maj(a,b,c) from the past
|
add r5,r5,r3 @ h+=Maj(a,b,c) from the past
|
||||||
eor r0,r0,r9,ror#19 @ Sigma1(e)
|
eor r0,r0,r9,ror#19 @ Sigma1(e)
|
||||||
|
# ifndef __ARMEB__
|
||||||
rev r2,r2
|
rev r2,r2
|
||||||
|
# endif
|
||||||
#else
|
#else
|
||||||
@ ldrb r2,[r1,#3] @ 7
|
@ ldrb r2,[r1,#3] @ 7
|
||||||
add r5,r5,r3 @ h+=Maj(a,b,c) from the past
|
add r5,r5,r3 @ h+=Maj(a,b,c) from the past
|
||||||
@ -569,7 +592,9 @@ sha256_block_data_order:
|
|||||||
eor r0,r8,r8,ror#5
|
eor r0,r8,r8,ror#5
|
||||||
add r4,r4,r12 @ h+=Maj(a,b,c) from the past
|
add r4,r4,r12 @ h+=Maj(a,b,c) from the past
|
||||||
eor r0,r0,r8,ror#19 @ Sigma1(e)
|
eor r0,r0,r8,ror#19 @ Sigma1(e)
|
||||||
|
# ifndef __ARMEB__
|
||||||
rev r2,r2
|
rev r2,r2
|
||||||
|
# endif
|
||||||
#else
|
#else
|
||||||
@ ldrb r2,[r1,#3] @ 8
|
@ ldrb r2,[r1,#3] @ 8
|
||||||
add r4,r4,r12 @ h+=Maj(a,b,c) from the past
|
add r4,r4,r12 @ h+=Maj(a,b,c) from the past
|
||||||
@ -625,7 +650,9 @@ sha256_block_data_order:
|
|||||||
eor r0,r7,r7,ror#5
|
eor r0,r7,r7,ror#5
|
||||||
add r11,r11,r3 @ h+=Maj(a,b,c) from the past
|
add r11,r11,r3 @ h+=Maj(a,b,c) from the past
|
||||||
eor r0,r0,r7,ror#19 @ Sigma1(e)
|
eor r0,r0,r7,ror#19 @ Sigma1(e)
|
||||||
|
# ifndef __ARMEB__
|
||||||
rev r2,r2
|
rev r2,r2
|
||||||
|
# endif
|
||||||
#else
|
#else
|
||||||
@ ldrb r2,[r1,#3] @ 9
|
@ ldrb r2,[r1,#3] @ 9
|
||||||
add r11,r11,r3 @ h+=Maj(a,b,c) from the past
|
add r11,r11,r3 @ h+=Maj(a,b,c) from the past
|
||||||
@ -681,7 +708,9 @@ sha256_block_data_order:
|
|||||||
eor r0,r6,r6,ror#5
|
eor r0,r6,r6,ror#5
|
||||||
add r10,r10,r12 @ h+=Maj(a,b,c) from the past
|
add r10,r10,r12 @ h+=Maj(a,b,c) from the past
|
||||||
eor r0,r0,r6,ror#19 @ Sigma1(e)
|
eor r0,r0,r6,ror#19 @ Sigma1(e)
|
||||||
|
# ifndef __ARMEB__
|
||||||
rev r2,r2
|
rev r2,r2
|
||||||
|
# endif
|
||||||
#else
|
#else
|
||||||
@ ldrb r2,[r1,#3] @ 10
|
@ ldrb r2,[r1,#3] @ 10
|
||||||
add r10,r10,r12 @ h+=Maj(a,b,c) from the past
|
add r10,r10,r12 @ h+=Maj(a,b,c) from the past
|
||||||
@ -737,7 +766,9 @@ sha256_block_data_order:
|
|||||||
eor r0,r5,r5,ror#5
|
eor r0,r5,r5,ror#5
|
||||||
add r9,r9,r3 @ h+=Maj(a,b,c) from the past
|
add r9,r9,r3 @ h+=Maj(a,b,c) from the past
|
||||||
eor r0,r0,r5,ror#19 @ Sigma1(e)
|
eor r0,r0,r5,ror#19 @ Sigma1(e)
|
||||||
|
# ifndef __ARMEB__
|
||||||
rev r2,r2
|
rev r2,r2
|
||||||
|
# endif
|
||||||
#else
|
#else
|
||||||
@ ldrb r2,[r1,#3] @ 11
|
@ ldrb r2,[r1,#3] @ 11
|
||||||
add r9,r9,r3 @ h+=Maj(a,b,c) from the past
|
add r9,r9,r3 @ h+=Maj(a,b,c) from the past
|
||||||
@ -793,7 +824,9 @@ sha256_block_data_order:
|
|||||||
eor r0,r4,r4,ror#5
|
eor r0,r4,r4,ror#5
|
||||||
add r8,r8,r12 @ h+=Maj(a,b,c) from the past
|
add r8,r8,r12 @ h+=Maj(a,b,c) from the past
|
||||||
eor r0,r0,r4,ror#19 @ Sigma1(e)
|
eor r0,r0,r4,ror#19 @ Sigma1(e)
|
||||||
|
# ifndef __ARMEB__
|
||||||
rev r2,r2
|
rev r2,r2
|
||||||
|
# endif
|
||||||
#else
|
#else
|
||||||
@ ldrb r2,[r1,#3] @ 12
|
@ ldrb r2,[r1,#3] @ 12
|
||||||
add r8,r8,r12 @ h+=Maj(a,b,c) from the past
|
add r8,r8,r12 @ h+=Maj(a,b,c) from the past
|
||||||
@ -849,7 +882,9 @@ sha256_block_data_order:
|
|||||||
eor r0,r11,r11,ror#5
|
eor r0,r11,r11,ror#5
|
||||||
add r7,r7,r3 @ h+=Maj(a,b,c) from the past
|
add r7,r7,r3 @ h+=Maj(a,b,c) from the past
|
||||||
eor r0,r0,r11,ror#19 @ Sigma1(e)
|
eor r0,r0,r11,ror#19 @ Sigma1(e)
|
||||||
|
# ifndef __ARMEB__
|
||||||
rev r2,r2
|
rev r2,r2
|
||||||
|
# endif
|
||||||
#else
|
#else
|
||||||
@ ldrb r2,[r1,#3] @ 13
|
@ ldrb r2,[r1,#3] @ 13
|
||||||
add r7,r7,r3 @ h+=Maj(a,b,c) from the past
|
add r7,r7,r3 @ h+=Maj(a,b,c) from the past
|
||||||
@ -905,7 +940,9 @@ sha256_block_data_order:
|
|||||||
eor r0,r10,r10,ror#5
|
eor r0,r10,r10,ror#5
|
||||||
add r6,r6,r12 @ h+=Maj(a,b,c) from the past
|
add r6,r6,r12 @ h+=Maj(a,b,c) from the past
|
||||||
eor r0,r0,r10,ror#19 @ Sigma1(e)
|
eor r0,r0,r10,ror#19 @ Sigma1(e)
|
||||||
|
# ifndef __ARMEB__
|
||||||
rev r2,r2
|
rev r2,r2
|
||||||
|
# endif
|
||||||
#else
|
#else
|
||||||
@ ldrb r2,[r1,#3] @ 14
|
@ ldrb r2,[r1,#3] @ 14
|
||||||
add r6,r6,r12 @ h+=Maj(a,b,c) from the past
|
add r6,r6,r12 @ h+=Maj(a,b,c) from the past
|
||||||
@ -961,7 +998,9 @@ sha256_block_data_order:
|
|||||||
eor r0,r9,r9,ror#5
|
eor r0,r9,r9,ror#5
|
||||||
add r5,r5,r3 @ h+=Maj(a,b,c) from the past
|
add r5,r5,r3 @ h+=Maj(a,b,c) from the past
|
||||||
eor r0,r0,r9,ror#19 @ Sigma1(e)
|
eor r0,r0,r9,ror#19 @ Sigma1(e)
|
||||||
|
# ifndef __ARMEB__
|
||||||
rev r2,r2
|
rev r2,r2
|
||||||
|
# endif
|
||||||
#else
|
#else
|
||||||
@ ldrb r2,[r1,#3] @ 15
|
@ ldrb r2,[r1,#3] @ 15
|
||||||
add r5,r5,r3 @ h+=Maj(a,b,c) from the past
|
add r5,r5,r3 @ h+=Maj(a,b,c) from the past
|
||||||
@ -1794,7 +1833,7 @@ sha256_block_data_order:
|
|||||||
eor r12,r12,r6 @ Maj(a,b,c)
|
eor r12,r12,r6 @ Maj(a,b,c)
|
||||||
add r4,r4,r0,ror#2 @ h+=Sigma0(a)
|
add r4,r4,r0,ror#2 @ h+=Sigma0(a)
|
||||||
@ add r4,r4,r12 @ h+=Maj(a,b,c)
|
@ add r4,r4,r12 @ h+=Maj(a,b,c)
|
||||||
#if __ARM_ARCH__>=7
|
#ifdef __thumb2__
|
||||||
ite eq @ Thumb2 thing, sanity check in ARM
|
ite eq @ Thumb2 thing, sanity check in ARM
|
||||||
#endif
|
#endif
|
||||||
ldreq r3,[sp,#16*4] @ pull ctx
|
ldreq r3,[sp,#16*4] @ pull ctx
|
||||||
@ -1826,9 +1865,9 @@ sha256_block_data_order:
|
|||||||
|
|
||||||
add sp,sp,#19*4 @ destroy frame
|
add sp,sp,#19*4 @ destroy frame
|
||||||
#if __ARM_ARCH__>=5
|
#if __ARM_ARCH__>=5
|
||||||
ldmia sp!,{r4-r11,pc}
|
ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,pc}
|
||||||
#else
|
#else
|
||||||
ldmia sp!,{r4-r11,lr}
|
ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,lr}
|
||||||
tst lr,#1
|
tst lr,#1
|
||||||
moveq pc,lr @ be binary compatible with V4, yet
|
moveq pc,lr @ be binary compatible with V4, yet
|
||||||
.word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
.word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
||||||
@ -1838,12 +1877,13 @@ sha256_block_data_order:
|
|||||||
.arch armv7-a
|
.arch armv7-a
|
||||||
.fpu neon
|
.fpu neon
|
||||||
|
|
||||||
.global sha256_block_data_order_neon
|
.globl sha256_block_data_order_neon
|
||||||
.type sha256_block_data_order_neon,%function
|
.type sha256_block_data_order_neon,%function
|
||||||
.align 4
|
.align 5
|
||||||
|
.skip 16
|
||||||
sha256_block_data_order_neon:
|
sha256_block_data_order_neon:
|
||||||
.LNEON:
|
.LNEON:
|
||||||
stmdb sp!,{r4-r12,lr}
|
stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
|
||||||
|
|
||||||
sub r11,sp,#16*4+16
|
sub r11,sp,#16*4+16
|
||||||
adr r14,K256
|
adr r14,K256
|
||||||
@ -1878,7 +1918,7 @@ sha256_block_data_order_neon:
|
|||||||
vst1.32 {q10},[r1,:128]!
|
vst1.32 {q10},[r1,:128]!
|
||||||
vst1.32 {q11},[r1,:128]!
|
vst1.32 {q11},[r1,:128]!
|
||||||
|
|
||||||
ldmia r0,{r4-r11}
|
ldmia r0,{r4,r5,r6,r7,r8,r9,r10,r11}
|
||||||
sub r1,r1,#64
|
sub r1,r1,#64
|
||||||
ldr r2,[sp,#0]
|
ldr r2,[sp,#0]
|
||||||
eor r12,r12,r12
|
eor r12,r12,r12
|
||||||
@ -2606,7 +2646,7 @@ sha256_block_data_order_neon:
|
|||||||
str r6,[r2],#4
|
str r6,[r2],#4
|
||||||
add r11,r11,r1
|
add r11,r11,r1
|
||||||
str r7,[r2],#4
|
str r7,[r2],#4
|
||||||
stmia r2,{r8-r11}
|
stmia r2,{r8,r9,r10,r11}
|
||||||
|
|
||||||
ittte ne
|
ittte ne
|
||||||
movne r1,sp
|
movne r1,sp
|
||||||
@ -2617,12 +2657,12 @@ sha256_block_data_order_neon:
|
|||||||
eorne r3,r5,r6
|
eorne r3,r5,r6
|
||||||
bne .L_00_48
|
bne .L_00_48
|
||||||
|
|
||||||
ldmia sp!,{r4-r12,pc}
|
ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,pc}
|
||||||
.size sha256_block_data_order_neon,.-sha256_block_data_order_neon
|
.size sha256_block_data_order_neon,.-sha256_block_data_order_neon
|
||||||
#endif
|
#endif
|
||||||
#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
|
#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
|
||||||
|
|
||||||
# ifdef __thumb2__
|
# if defined(__thumb2__)
|
||||||
# define INST(a,b,c,d) .byte c,d|0xc,a,b
|
# define INST(a,b,c,d) .byte c,d|0xc,a,b
|
||||||
# else
|
# else
|
||||||
# define INST(a,b,c,d) .byte a,b,c,d
|
# define INST(a,b,c,d) .byte a,b,c,d
|
||||||
@ -2633,17 +2673,14 @@ sha256_block_data_order_neon:
|
|||||||
sha256_block_data_order_armv8:
|
sha256_block_data_order_armv8:
|
||||||
.LARMv8:
|
.LARMv8:
|
||||||
vld1.32 {q0,q1},[r0]
|
vld1.32 {q0,q1},[r0]
|
||||||
# ifdef __thumb2__
|
|
||||||
adr r3,.LARMv8
|
|
||||||
sub r3,r3,#.LARMv8-K256
|
|
||||||
# else
|
|
||||||
sub r3,r3,#256+32
|
sub r3,r3,#256+32
|
||||||
# endif
|
|
||||||
add r2,r1,r2,lsl#6 @ len to point at the end of inp
|
add r2,r1,r2,lsl#6 @ len to point at the end of inp
|
||||||
|
b .Loop_v8
|
||||||
|
|
||||||
|
.align 4
|
||||||
.Loop_v8:
|
.Loop_v8:
|
||||||
vld1.8 {q8-q9},[r1]!
|
vld1.8 {q8,q9},[r1]!
|
||||||
vld1.8 {q10-q11},[r1]!
|
vld1.8 {q10,q11},[r1]!
|
||||||
vld1.32 {q12},[r3]!
|
vld1.32 {q12},[r3]!
|
||||||
vrev32.8 q8,q8
|
vrev32.8 q8,q8
|
||||||
vrev32.8 q9,q9
|
vrev32.8 q9,q9
|
||||||
@ -2770,7 +2807,8 @@ sha256_block_data_order_armv8:
|
|||||||
bx lr @ bx lr
|
bx lr @ bx lr
|
||||||
.size sha256_block_data_order_armv8,.-sha256_block_data_order_armv8
|
.size sha256_block_data_order_armv8,.-sha256_block_data_order_armv8
|
||||||
#endif
|
#endif
|
||||||
.asciz "SHA256 block transform for ARMv4/NEON/ARMv8, CRYPTOGAMS by <appro@openssl.org>"
|
.byte 83,72,65,50,53,54,32,98,108,111,99,107,32,116,114,97,110,115,102,111,114,109,32,102,111,114,32,65,82,77,118,52,47,78,69,79,78,47,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
|
||||||
|
.align 2
|
||||||
.align 2
|
.align 2
|
||||||
#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
|
#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
|
||||||
.comm OPENSSL_armcap_P,4,4
|
.comm OPENSSL_armcap_P,4,4
|
||||||
|
@ -1,6 +1,70 @@
|
|||||||
/* $FreeBSD$ */
|
/* $FreeBSD$ */
|
||||||
/* Do not modify. This file is auto-generated from sha512-armv4.pl. */
|
/* Do not modify. This file is auto-generated from sha512-armv4.pl. */
|
||||||
|
@ Copyright 2007-2018 The OpenSSL Project Authors. All Rights Reserved.
|
||||||
|
@
|
||||||
|
@ Licensed under the OpenSSL license (the "License"). You may not use
|
||||||
|
@ this file except in compliance with the License. You can obtain a copy
|
||||||
|
@ in the file LICENSE in the source distribution or at
|
||||||
|
@ https://www.openssl.org/source/license.html
|
||||||
|
|
||||||
|
|
||||||
|
@ ====================================================================
|
||||||
|
@ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
|
||||||
|
@ project. The module is, however, dual licensed under OpenSSL and
|
||||||
|
@ CRYPTOGAMS licenses depending on where you obtain it. For further
|
||||||
|
@ details see http://www.openssl.org/~appro/cryptogams/.
|
||||||
|
@
|
||||||
|
@ Permission to use under GPL terms is granted.
|
||||||
|
@ ====================================================================
|
||||||
|
|
||||||
|
@ SHA512 block procedure for ARMv4. September 2007.
|
||||||
|
|
||||||
|
@ This code is ~4.5 (four and a half) times faster than code generated
|
||||||
|
@ by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue
|
||||||
|
@ Xscale PXA250 core].
|
||||||
|
@
|
||||||
|
@ July 2010.
|
||||||
|
@
|
||||||
|
@ Rescheduling for dual-issue pipeline resulted in 6% improvement on
|
||||||
|
@ Cortex A8 core and ~40 cycles per processed byte.
|
||||||
|
|
||||||
|
@ February 2011.
|
||||||
|
@
|
||||||
|
@ Profiler-assisted and platform-specific optimization resulted in 7%
|
||||||
|
@ improvement on Coxtex A8 core and ~38 cycles per byte.
|
||||||
|
|
||||||
|
@ March 2011.
|
||||||
|
@
|
||||||
|
@ Add NEON implementation. On Cortex A8 it was measured to process
|
||||||
|
@ one byte in 23.3 cycles or ~60% faster than integer-only code.
|
||||||
|
|
||||||
|
@ August 2012.
|
||||||
|
@
|
||||||
|
@ Improve NEON performance by 12% on Snapdragon S4. In absolute
|
||||||
|
@ terms it's 22.6 cycles per byte, which is disappointing result.
|
||||||
|
@ Technical writers asserted that 3-way S4 pipeline can sustain
|
||||||
|
@ multiple NEON instructions per cycle, but dual NEON issue could
|
||||||
|
@ not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html
|
||||||
|
@ for further details. On side note Cortex-A15 processes one byte in
|
||||||
|
@ 16 cycles.
|
||||||
|
|
||||||
|
@ Byte order [in]dependence. =========================================
|
||||||
|
@
|
||||||
|
@ Originally caller was expected to maintain specific *dword* order in
|
||||||
|
@ h[0-7], namely with most significant dword at *lower* address, which
|
||||||
|
@ was reflected in below two parameters as 0 and 4. Now caller is
|
||||||
|
@ expected to maintain native byte order for whole 64-bit values.
|
||||||
|
#ifndef __KERNEL__
|
||||||
# include "arm_arch.h"
|
# include "arm_arch.h"
|
||||||
|
# define VFP_ABI_PUSH vstmdb sp!,{d8-d15}
|
||||||
|
# define VFP_ABI_POP vldmia sp!,{d8-d15}
|
||||||
|
#else
|
||||||
|
# define __ARM_ARCH__ __LINUX_ARM_ARCH__
|
||||||
|
# define __ARM_MAX_ARCH__ 7
|
||||||
|
# define VFP_ABI_PUSH
|
||||||
|
# define VFP_ABI_POP
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifdef __ARMEL__
|
#ifdef __ARMEL__
|
||||||
# define LO 0
|
# define LO 0
|
||||||
# define HI 4
|
# define HI 4
|
||||||
@ -12,7 +76,14 @@
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
.text
|
.text
|
||||||
|
#if defined(__thumb2__)
|
||||||
|
.syntax unified
|
||||||
|
.thumb
|
||||||
|
# define adrl adr
|
||||||
|
#else
|
||||||
.code 32
|
.code 32
|
||||||
|
#endif
|
||||||
|
|
||||||
.type K512,%object
|
.type K512,%object
|
||||||
.align 5
|
.align 5
|
||||||
K512:
|
K512:
|
||||||
@ -57,26 +128,34 @@ WORD64(0x3c9ebe0a,0x15c9bebc, 0x431d67c4,0x9c100d4c)
|
|||||||
WORD64(0x4cc5d4be,0xcb3e42b6, 0x597f299c,0xfc657e2a)
|
WORD64(0x4cc5d4be,0xcb3e42b6, 0x597f299c,0xfc657e2a)
|
||||||
WORD64(0x5fcb6fab,0x3ad6faec, 0x6c44198c,0x4a475817)
|
WORD64(0x5fcb6fab,0x3ad6faec, 0x6c44198c,0x4a475817)
|
||||||
.size K512,.-K512
|
.size K512,.-K512
|
||||||
#if __ARM_MAX_ARCH__>=7
|
#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
|
||||||
.LOPENSSL_armcap:
|
.LOPENSSL_armcap:
|
||||||
.word OPENSSL_armcap_P-sha512_block_data_order
|
.word OPENSSL_armcap_P-.Lsha512_block_data_order
|
||||||
.skip 32-4
|
.skip 32-4
|
||||||
#else
|
#else
|
||||||
.skip 32
|
.skip 32
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
.global sha512_block_data_order
|
.globl sha512_block_data_order
|
||||||
.type sha512_block_data_order,%function
|
.type sha512_block_data_order,%function
|
||||||
sha512_block_data_order:
|
sha512_block_data_order:
|
||||||
|
.Lsha512_block_data_order:
|
||||||
|
#if __ARM_ARCH__<7 && !defined(__thumb2__)
|
||||||
sub r3,pc,#8 @ sha512_block_data_order
|
sub r3,pc,#8 @ sha512_block_data_order
|
||||||
add r2,r1,r2,lsl#7 @ len to point at the end of inp
|
#else
|
||||||
#if __ARM_MAX_ARCH__>=7
|
adr r3,.Lsha512_block_data_order
|
||||||
|
#endif
|
||||||
|
#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
|
||||||
ldr r12,.LOPENSSL_armcap
|
ldr r12,.LOPENSSL_armcap
|
||||||
ldr r12,[r3,r12] @ OPENSSL_armcap_P
|
ldr r12,[r3,r12] @ OPENSSL_armcap_P
|
||||||
tst r12,#1
|
#ifdef __APPLE__
|
||||||
|
ldr r12,[r12]
|
||||||
|
#endif
|
||||||
|
tst r12,#ARMV7_NEON
|
||||||
bne .LNEON
|
bne .LNEON
|
||||||
#endif
|
#endif
|
||||||
stmdb sp!,{r4-r12,lr}
|
add r2,r1,r2,lsl#7 @ len to point at the end of inp
|
||||||
|
stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
|
||||||
sub r14,r3,#672 @ K512
|
sub r14,r3,#672 @ K512
|
||||||
sub sp,sp,#9*8
|
sub sp,sp,#9*8
|
||||||
|
|
||||||
@ -188,6 +267,9 @@ sha512_block_data_order:
|
|||||||
teq r9,#148
|
teq r9,#148
|
||||||
|
|
||||||
ldr r12,[sp,#16+0] @ c.lo
|
ldr r12,[sp,#16+0] @ c.lo
|
||||||
|
#ifdef __thumb2__
|
||||||
|
it eq @ Thumb2 thing, sanity check in ARM
|
||||||
|
#endif
|
||||||
orreq r14,r14,#1
|
orreq r14,r14,#1
|
||||||
@ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
|
@ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
|
||||||
@ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25
|
@ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25
|
||||||
@ -325,6 +407,9 @@ sha512_block_data_order:
|
|||||||
teq r9,#23
|
teq r9,#23
|
||||||
|
|
||||||
ldr r12,[sp,#16+0] @ c.lo
|
ldr r12,[sp,#16+0] @ c.lo
|
||||||
|
#ifdef __thumb2__
|
||||||
|
it eq @ Thumb2 thing, sanity check in ARM
|
||||||
|
#endif
|
||||||
orreq r14,r14,#1
|
orreq r14,r14,#1
|
||||||
@ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
|
@ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
|
||||||
@ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25
|
@ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25
|
||||||
@ -359,6 +444,9 @@ sha512_block_data_order:
|
|||||||
adc r6,r6,r4 @ h += T
|
adc r6,r6,r4 @ h += T
|
||||||
tst r14,#1
|
tst r14,#1
|
||||||
add r14,r14,#8
|
add r14,r14,#8
|
||||||
|
#ifdef __thumb2__
|
||||||
|
ittt eq @ Thumb2 thing, sanity check in ARM
|
||||||
|
#endif
|
||||||
ldreq r9,[sp,#184+0]
|
ldreq r9,[sp,#184+0]
|
||||||
ldreq r10,[sp,#184+4]
|
ldreq r10,[sp,#184+4]
|
||||||
beq .L16_79
|
beq .L16_79
|
||||||
@ -436,23 +524,28 @@ sha512_block_data_order:
|
|||||||
|
|
||||||
add sp,sp,#8*9 @ destroy frame
|
add sp,sp,#8*9 @ destroy frame
|
||||||
#if __ARM_ARCH__>=5
|
#if __ARM_ARCH__>=5
|
||||||
ldmia sp!,{r4-r12,pc}
|
ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,pc}
|
||||||
#else
|
#else
|
||||||
ldmia sp!,{r4-r12,lr}
|
ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
|
||||||
tst lr,#1
|
tst lr,#1
|
||||||
moveq pc,lr @ be binary compatible with V4, yet
|
moveq pc,lr @ be binary compatible with V4, yet
|
||||||
.word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
.word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
||||||
#endif
|
#endif
|
||||||
|
.size sha512_block_data_order,.-sha512_block_data_order
|
||||||
#if __ARM_MAX_ARCH__>=7
|
#if __ARM_MAX_ARCH__>=7
|
||||||
.arch armv7-a
|
.arch armv7-a
|
||||||
.fpu neon
|
.fpu neon
|
||||||
|
|
||||||
|
.globl sha512_block_data_order_neon
|
||||||
|
.type sha512_block_data_order_neon,%function
|
||||||
.align 4
|
.align 4
|
||||||
|
sha512_block_data_order_neon:
|
||||||
.LNEON:
|
.LNEON:
|
||||||
dmb @ errata #451034 on early Cortex A8
|
dmb @ errata #451034 on early Cortex A8
|
||||||
vstmdb sp!,{d8-d15} @ ABI specification says so
|
add r2,r1,r2,lsl#7 @ len to point at the end of inp
|
||||||
sub r3,r3,#672 @ K512
|
adr r3,K512
|
||||||
vldmia r0,{d16-d23} @ load context
|
VFP_ABI_PUSH
|
||||||
|
vldmia r0,{d16,d17,d18,d19,d20,d21,d22,d23} @ load context
|
||||||
.Loop_neon:
|
.Loop_neon:
|
||||||
vshr.u64 d24,d20,#14 @ 0
|
vshr.u64 d24,d20,#14 @ 0
|
||||||
#if 0<16
|
#if 0<16
|
||||||
@ -1756,22 +1849,23 @@ sha512_block_data_order:
|
|||||||
bne .L16_79_neon
|
bne .L16_79_neon
|
||||||
|
|
||||||
vadd.i64 d16,d30 @ h+=Maj from the past
|
vadd.i64 d16,d30 @ h+=Maj from the past
|
||||||
vldmia r0,{d24-d31} @ load context to temp
|
vldmia r0,{d24,d25,d26,d27,d28,d29,d30,d31} @ load context to temp
|
||||||
vadd.i64 q8,q12 @ vectorized accumulate
|
vadd.i64 q8,q12 @ vectorized accumulate
|
||||||
vadd.i64 q9,q13
|
vadd.i64 q9,q13
|
||||||
vadd.i64 q10,q14
|
vadd.i64 q10,q14
|
||||||
vadd.i64 q11,q15
|
vadd.i64 q11,q15
|
||||||
vstmia r0,{d16-d23} @ save context
|
vstmia r0,{d16,d17,d18,d19,d20,d21,d22,d23} @ save context
|
||||||
teq r1,r2
|
teq r1,r2
|
||||||
sub r3,#640 @ rewind K512
|
sub r3,#640 @ rewind K512
|
||||||
bne .Loop_neon
|
bne .Loop_neon
|
||||||
|
|
||||||
vldmia sp!,{d8-d15} @ epilogue
|
VFP_ABI_POP
|
||||||
bx lr @ .word 0xe12fff1e
|
bx lr @ .word 0xe12fff1e
|
||||||
|
.size sha512_block_data_order_neon,.-sha512_block_data_order_neon
|
||||||
#endif
|
#endif
|
||||||
.size sha512_block_data_order,.-sha512_block_data_order
|
.byte 83,72,65,53,49,50,32,98,108,111,99,107,32,116,114,97,110,115,102,111,114,109,32,102,111,114,32,65,82,77,118,52,47,78,69,79,78,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
|
||||||
.asciz "SHA512 block transform for ARMv4/NEON, CRYPTOGAMS by <appro@openssl.org>"
|
|
||||||
.align 2
|
.align 2
|
||||||
#if __ARM_MAX_ARCH__>=7
|
.align 2
|
||||||
|
#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
|
||||||
.comm OPENSSL_armcap_P,4,4
|
.comm OPENSSL_armcap_P,4,4
|
||||||
#endif
|
#endif
|
||||||
|
Loading…
Reference in New Issue
Block a user