Some K8 chipsets don't expose all of the PCI devices on bus 0 via PCIe
memory-mapped config access. Add a workaround for these systems by checking the first function of each slot on bus 0 using both the memory-mapped config access and the older type 1 I/O port config access. If we find a slot that is only visible via the type 1 I/O port config access, we flag that slot. Future PCI config transactions to flagged slots on bus 0 use type 1 I/O port config access rather than memory mapped config access.
This commit is contained in:
parent
bf9c6c31e7
commit
2d10570afe
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=182910
@ -46,6 +46,8 @@ enum {
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CFGMECH_PCIE,
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};
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static uint32_t pci_docfgregread(int bus, int slot, int func, int reg,
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int bytes);
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static int pciereg_cfgread(int bus, unsigned slot, unsigned func,
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unsigned reg, unsigned bytes);
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static void pciereg_cfgwrite(int bus, unsigned slot, unsigned func,
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@ -56,6 +58,7 @@ static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int
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static int cfgmech;
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static vm_offset_t pcie_base;
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static int pcie_minbus, pcie_maxbus;
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static uint32_t pcie_badslots;
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static struct mtx pcicfg_mtx;
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/*
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@ -64,12 +67,17 @@ static struct mtx pcicfg_mtx;
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int
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pci_cfgregopen(void)
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{
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static int once = 0;
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uint64_t pciebar;
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uint16_t did, vid;
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if (!once) {
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mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
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once = 1;
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}
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if (cfgmech != CFGMECH_NONE)
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return (1);
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mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
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cfgmech = CFGMECH_1;
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/*
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@ -103,6 +111,17 @@ pci_cfgregopen(void)
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return (1);
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}
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static uint32_t
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pci_docfgregread(int bus, int slot, int func, int reg, int bytes)
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{
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if (cfgmech == CFGMECH_PCIE &&
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(bus != 0 || !(1 << slot & pcie_badslots)))
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return (pciereg_cfgread(bus, slot, func, reg, bytes));
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else
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return (pcireg_cfgread(bus, slot, func, reg, bytes));
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}
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/*
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* Read configuration space register
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*/
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@ -120,12 +139,12 @@ pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
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* as an invalid IRQ.
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*/
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if (reg == PCIR_INTLINE && bytes == 1) {
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line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
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line = pci_docfgregread(bus, slot, func, PCIR_INTLINE, 1);
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if (line == 0 || line >= 128)
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line = PCI_INVALID_IRQ;
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return (line);
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}
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return (pcireg_cfgread(bus, slot, func, reg, bytes));
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return (pci_docfgregread(bus, slot, func, reg, bytes));
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}
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/*
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@ -135,7 +154,11 @@ void
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pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
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{
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pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
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if (cfgmech == CFGMECH_PCIE &&
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(bus != 0 || !(1 << slot & pcie_badslots)))
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pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
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else
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pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
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}
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/*
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@ -175,11 +198,6 @@ pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
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int data = -1;
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int port;
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if (cfgmech == CFGMECH_PCIE) {
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data = pciereg_cfgread(bus, slot, func, reg, bytes);
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return (data);
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}
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mtx_lock_spin(&pcicfg_mtx);
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port = pci_cfgenable(bus, slot, func, reg, bytes);
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if (port != 0) {
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@ -205,11 +223,6 @@ pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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{
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int port;
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if (cfgmech == CFGMECH_PCIE) {
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pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
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return;
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}
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mtx_lock_spin(&pcicfg_mtx);
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port = pci_cfgenable(bus, slot, func, reg, bytes);
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if (port != 0) {
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@ -232,6 +245,8 @@ pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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int
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pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
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{
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uint32_t val1, val2;
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int slot;
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if (minbus != 0)
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return (0);
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@ -245,6 +260,25 @@ pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
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pcie_minbus = minbus;
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pcie_maxbus = maxbus;
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cfgmech = CFGMECH_PCIE;
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/*
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* On some AMD systems, some of the devices on bus 0 are
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* inaccessible using memory-mapped PCI config access. Walk
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* bus 0 looking for such devices. For these devices, we will
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* fall back to using type 1 config access instead.
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*/
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if (pci_cfgregopen() != 0) {
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for (slot = 0; slot < 32; slot++) {
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val1 = pcireg_cfgread(0, slot, 0, 0, 4);
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if (val1 == 0xffffffff)
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continue;
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val2 = pciereg_cfgread(0, slot, 0, 0, 4);
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if (val2 != val1)
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pcie_badslots |= (1 << slot);
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}
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}
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return (1);
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}
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@ -77,10 +77,13 @@ enum {
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static TAILQ_HEAD(pcie_cfg_list, pcie_cfg_elem) pcie_list[MAXCPU];
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static uint64_t pcie_base;
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static int pcie_minbus, pcie_maxbus;
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static uint32_t pcie_badslots;
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static int cfgmech;
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static int devmax;
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static struct mtx pcicfg_mtx;
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static uint32_t pci_docfgregread(int bus, int slot, int func, int reg,
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int bytes);
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static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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#ifndef XEN
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@ -195,6 +198,17 @@ pci_cfgregopen(void)
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#endif
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}
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static uint32_t
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pci_docfgregread(int bus, int slot, int func, int reg, int bytes)
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{
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if (cfgmech == CFGMECH_PCIE &&
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(bus != 0 || !(1 << slot & pcie_badslots)))
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return (pciereg_cfgread(bus, slot, func, reg, bytes));
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else
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return (pcireg_cfgread(bus, slot, func, reg, bytes));
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}
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/*
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* Read configuration space register
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*/
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@ -209,10 +223,10 @@ pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
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* the code uses 255 as an invalid IRQ.
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*/
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if (reg == PCIR_INTLINE && bytes == 1) {
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line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
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line = pci_docfgregread(bus, slot, func, PCIR_INTLINE, 1);
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return (pci_i386_map_intline(line));
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}
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return (pcireg_cfgread(bus, slot, func, reg, bytes));
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return (pci_docfgregread(bus, slot, func, reg, bytes));
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}
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/*
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@ -222,7 +236,11 @@ void
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pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
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{
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pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
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if (cfgmech == CFGMECH_PCIE &&
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(bus != 0 || !(1 << slot & pcie_badslots)))
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pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
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else
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pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
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}
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/*
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@ -276,6 +294,7 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
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&& (unsigned) bytes <= 4
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&& (reg & (bytes - 1)) == 0) {
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switch (cfgmech) {
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case CFGMECH_PCIE:
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case CFGMECH_1:
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outl(CONF1_ADDR_PORT, (1 << 31)
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| (bus << 16) | (slot << 11)
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@ -297,6 +316,7 @@ static void
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pci_cfgdisable(void)
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{
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switch (cfgmech) {
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case CFGMECH_PCIE:
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case CFGMECH_1:
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/*
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* Do nothing for the config mechanism 1 case.
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@ -317,11 +337,6 @@ pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
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int data = -1;
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int port;
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if (cfgmech == CFGMECH_PCIE) {
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data = pciereg_cfgread(bus, slot, func, reg, bytes);
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return (data);
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}
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mtx_lock_spin(&pcicfg_mtx);
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port = pci_cfgenable(bus, slot, func, reg, bytes);
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if (port != 0) {
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@ -347,11 +362,6 @@ pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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{
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int port;
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if (cfgmech == CFGMECH_PCIE) {
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pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
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return;
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}
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mtx_lock_spin(&pcicfg_mtx);
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port = pci_cfgenable(bus, slot, func, reg, bytes);
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if (port != 0) {
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@ -509,7 +519,8 @@ pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
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struct pcpu *pc;
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#endif
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vm_offset_t va;
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int i;
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uint32_t val1, val2;
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int i, slot;
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if (minbus != 0)
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return (0);
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@ -563,6 +574,25 @@ pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
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pcie_maxbus = maxbus;
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cfgmech = CFGMECH_PCIE;
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devmax = 32;
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/*
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* On some AMD systems, some of the devices on bus 0 are
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* inaccessible using memory-mapped PCI config access. Walk
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* bus 0 looking for such devices. For these devices, we will
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* fall back to using type 1 config access instead.
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*/
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if (pci_cfgregopen() != 0) {
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for (slot = 0; slot < 32; slot++) {
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val1 = pcireg_cfgread(0, slot, 0, 0, 4);
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if (val1 == 0xffffffff)
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continue;
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val2 = pciereg_cfgread(0, slot, 0, 0, 4);
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if (val2 != val1)
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pcie_badslots |= (1 << slot);
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}
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}
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return (1);
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}
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#endif /* !XEN */
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