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mpi3mr: 3rd Generation Tri-Mode NVMe/SAS/SATA MegaRaid / eHBA

Browse Source 
This is Broadcom's mpi3mr driver for FreeBSD version 8.6.0.2.0.
The mpi3mr driver supports Broadcom SAS4116-based cards in the 9600
series: 9670W-16i, 9670-24i, 9660-16i, 9620-16i, 9600-24i, 9600-16i,
9600W-16e, 9600-16e, 9600-8i8e.

Initially only available as a module and on amd64/arm64, since that's
how it has been tested to date. Future commits will add it to the kernel
build and may expand the architectures it is supported on.

Co-authored-by: Chandrakanth Patil <chandrakanth.patil@broadcom.com>
Feedback-by: ken (prior versions)
Reviewed-by: imp
RelNotes: yes
Differential-Revision: https://reviews.freebsd.org/D36771
Differential-Revision: https://reviews.freebsd.org/D36772
This commit is contained in:
Sumit Saxena 2023-06-14 16:22:30 -06:00 committed by Warner Losh
parent 2b5dd8b890
commit 2d1d418e1e
21 changed files with 20817 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

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/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2016-2023, Broadcom Inc. All rights reserved.
* Support: <fbsd-storage-driver.pdl@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
* 3. Neither the name of the Broadcom Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are
* those of the authors and should not be interpreted as representing
* official policies,either expressed or implied, of the FreeBSD Project.
*
* Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131
*
* Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD
*
*/
#ifndef MPI30_API_H
#define MPI30_API_H 1
#include "mpi30_type.h"
#include "mpi30_transport.h"
#include "mpi30_cnfg.h"
#include "mpi30_image.h"
#include "mpi30_init.h"
#include "mpi30_ioc.h"
#include "mpi30_pci.h"
#include "mpi30_raid.h"
#include "mpi30_sas.h"
#include "mpi30_targ.h"
#include "mpi30_tool.h"
#endif /* MPI30_API_H */

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/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2016-2023, Broadcom Inc. All rights reserved.
* Support: <fbsd-storage-driver.pdl@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
* 3. Neither the name of the Broadcom Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are
* those of the authors and should not be interpreted as representing
* official policies,either expressed or implied, of the FreeBSD Project.
*
* Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131
*
* Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD
*
*/
#ifndef MPI30_IMAGE_H
#define MPI30_IMAGE_H 1
/* Component Image Version */
typedef struct _MPI3_COMP_IMAGE_VERSION
{
U16 BuildNum; /* 0x00 */
U16 CustomerID; /* 0x02 */
U8 PhaseMinor; /* 0x04 */
U8 PhaseMajor; /* 0x05 */
U8 GenMinor; /* 0x06 */
U8 GenMajor; /* 0x07 */
} MPI3_COMP_IMAGE_VERSION, MPI3_POINTER PTR_MPI3_COMP_IMAGE_VERSION,
Mpi3CompImageVersion_t, MPI3_POINTER pMpi3CompImageVersion_t;
/* Hash Exclusion Format */
typedef struct _MPI3_HASH_EXCLUSION_FORMAT
{
U32 Offset; /* 0x00 */
U32 Size; /* 0x04 */
} MPI3_HASH_EXCLUSION_FORMAT, MPI3_POINTER PTR_MPI3_HASH_EXCLUSION_FORMAT,
Mpi3HashSxclusionFormat_t, MPI3_POINTER pMpi3HashExclusionFormat_t;
#define MPI3_IMAGE_HASH_EXCUSION_NUM (4)
/* FW Image Header */
typedef struct _MPI3_COMPONENT_IMAGE_HEADER
{
U32 Signature0; /* 0x00 */
U32 LoadAddress; /* 0x04 */
U32 DataSize; /* 0x08 */
U32 StartOffset; /* 0x0C */
U32 Signature1; /* 0x10 */
U32 FlashOffset; /* 0x14 */
U32 ImageSize; /* 0x18 */
U32 VersionStringOffset; /* 0x1C */
U32 BuildDateStringOffset; /* 0x20 */
U32 BuildTimeStringOffset; /* 0x24 */
U32 EnvironmentVariableOffset; /* 0x28 */
U32 ApplicationSpecific; /* 0x2C */
U32 Signature2; /* 0x30 */
U32 HeaderSize; /* 0x34 */
U32 Crc; /* 0x38 */
U32 Flags; /* 0x3C */
U32 SecondaryFlashOffset; /* 0x40 */
U32 ETPOffset; /* 0x44 */
U32 ETPSize; /* 0x48 */
MPI3_VERSION_UNION RMCInterfaceVersion; /* 0x4C */
MPI3_VERSION_UNION ETPInterfaceVersion; /* 0x50 */
MPI3_COMP_IMAGE_VERSION ComponentImageVersion; /* 0x54 */
MPI3_HASH_EXCLUSION_FORMAT HashExclusion[MPI3_IMAGE_HASH_EXCUSION_NUM]; /* 0x5C */
U32 NextImageHeaderOffset; /* 0x7C */
MPI3_VERSION_UNION SecurityVersion; /* 0x80 */
U32 Reserved84[31]; /* 0x84 -- 0xFC */
} MPI3_COMPONENT_IMAGE_HEADER, MPI3_POINTER PTR_MPI3_COMPONENT_IMAGE_HEADER,
Mpi3ComponentImageHeader_t, MPI3_POINTER pMpi3ComponentImageHeader_t;
/**** Definitions for Signature0 field ****/
#define MPI3_IMAGE_HEADER_SIGNATURE0_MPI3 (0xEB00003E)
/**** Definitions for LoadAddress field ****/
#define MPI3_IMAGE_HEADER_LOAD_ADDRESS_INVALID (0x00000000)
/**** Definitions for Signature1 field ****/
#define MPI3_IMAGE_HEADER_SIGNATURE1_APPLICATION (0x20505041) /* string "APP " */
#define MPI3_IMAGE_HEADER_SIGNATURE1_FIRST_MUTABLE (0x20434D46) /* string "FMC " */
#define MPI3_IMAGE_HEADER_SIGNATURE1_BSP (0x20505342) /* string "BSP " */
#define MPI3_IMAGE_HEADER_SIGNATURE1_ROM_BIOS (0x534F4942) /* string "BIOS" */
#define MPI3_IMAGE_HEADER_SIGNATURE1_HII_X64 (0x4D494948) /* string "HIIM" */
#define MPI3_IMAGE_HEADER_SIGNATURE1_HII_ARM (0x41494948) /* string "HIIA" */
#define MPI3_IMAGE_HEADER_SIGNATURE1_CPLD (0x444C5043) /* string "CPLD" */
#define MPI3_IMAGE_HEADER_SIGNATURE1_SPD (0x20445053) /* string "SPD " */
#define MPI3_IMAGE_HEADER_SIGNATURE1_GAS_GAUGE (0x20534147) /* string "GAS " */
#define MPI3_IMAGE_HEADER_SIGNATURE1_PBLP (0x504C4250) /* string "PBLP" */
#define MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST (0x464E414D) /* string "MANF" */
#define MPI3_IMAGE_HEADER_SIGNATURE1_OEM (0x204D454F) /* string "OEM " */
#define MPI3_IMAGE_HEADER_SIGNATURE1_RMC (0x20434D52) /* string "RMC " */
#define MPI3_IMAGE_HEADER_SIGNATURE1_SMM (0x204D4D53) /* string "SMM " */
#define MPI3_IMAGE_HEADER_SIGNATURE1_PSW (0x20575350) /* string "PSW " */
/**** Definitions for Signature2 field ****/
#define MPI3_IMAGE_HEADER_SIGNATURE2_VALUE (0x50584546)
/**** Definitions for Flags field ****/
#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_MASK (0x00000030)
#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_CDI (0x00000000)
#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_DI (0x00000010)
#define MPI3_IMAGE_HEADER_FLAGS_SIGNED_NVDATA (0x00000008)
#define MPI3_IMAGE_HEADER_FLAGS_REQUIRES_ACTIVATION (0x00000004)
#define MPI3_IMAGE_HEADER_FLAGS_COMPRESSED (0x00000002)
#define MPI3_IMAGE_HEADER_FLAGS_FLASH (0x00000001)
/**** Offsets for Image Header Fields ****/
#define MPI3_IMAGE_HEADER_SIGNATURE0_OFFSET (0x00)
#define MPI3_IMAGE_HEADER_LOAD_ADDRESS_OFFSET (0x04)
#define MPI3_IMAGE_HEADER_DATA_SIZE_OFFSET (0x08)
#define MPI3_IMAGE_HEADER_START_OFFSET_OFFSET (0x0C)
#define MPI3_IMAGE_HEADER_SIGNATURE1_OFFSET (0x10)
#define MPI3_IMAGE_HEADER_FLASH_OFFSET_OFFSET (0x14)
#define MPI3_IMAGE_HEADER_FLASH_SIZE_OFFSET (0x18)
#define MPI3_IMAGE_HEADER_VERSION_STRING_OFFSET_OFFSET (0x1C)
#define MPI3_IMAGE_HEADER_BUILD_DATE_STRING_OFFSET_OFFSET (0x20)
#define MPI3_IMAGE_HEADER_BUILD_TIME_OFFSET_OFFSET (0x24)
#define MPI3_IMAGE_HEADER_ENVIROMENT_VAR_OFFSET_OFFSET (0x28)
#define MPI3_IMAGE_HEADER_APPLICATION_SPECIFIC_OFFSET (0x2C)
#define MPI3_IMAGE_HEADER_SIGNATURE2_OFFSET (0x30)
#define MPI3_IMAGE_HEADER_HEADER_SIZE_OFFSET (0x34)
#define MPI3_IMAGE_HEADER_CRC_OFFSET (0x38)
#define MPI3_IMAGE_HEADER_FLAGS_OFFSET (0x3C)
#define MPI3_IMAGE_HEADER_SECONDARY_FLASH_OFFSET_OFFSET (0x40)
#define MPI3_IMAGE_HEADER_ETP_OFFSET_OFFSET (0x44)
#define MPI3_IMAGE_HEADER_ETP_SIZE_OFFSET (0x48)
#define MPI3_IMAGE_HEADER_RMC_INTERFACE_VER_OFFSET (0x4C)
#define MPI3_IMAGE_HEADER_ETP_INTERFACE_VER_OFFSET (0x50)
#define MPI3_IMAGE_HEADER_COMPONENT_IMAGE_VER_OFFSET (0x54)
#define MPI3_IMAGE_HEADER_HASH_EXCLUSION_OFFSET (0x5C)
#define MPI3_IMAGE_HEADER_NEXT_IMAGE_HEADER_OFFSET_OFFSET (0x7C)
#define MPI3_IMAGE_HEADER_SIZE (0x100)
/*****************************************************************************
* Component Image Data *
*****************************************************************************/
/* Package Manifest Data */
#ifndef MPI3_CI_MANIFEST_MPI_MAX
#define MPI3_CI_MANIFEST_MPI_MAX (1)
#endif /* MPI3_CI_MANIFEST_MPI_MAX */
typedef struct _MPI3_CI_MANIFEST_MPI_COMP_IMAGE_REF
{
U32 Signature1; /* 0x00 */
U32 Reserved04[3]; /* 0x04 */
MPI3_COMP_IMAGE_VERSION ComponentImageVersion; /* 0x10 */
U32 ComponentImageVersionStringOffset; /* 0x18 */
U32 CRC; /* 0x1C */
} MPI3_CI_MANIFEST_MPI_COMP_IMAGE_REF, MPI3_POINTER PTR_MPI3_CI_MANIFEST_MPI_COMP_IMAGE_REF,
Mpi3CIManifestMpiCompImageRef_t, MPI3_POINTER pMpi3CIManifestMpiCompImageRef_t;
typedef struct _MPI3_CI_MANIFEST_MPI
{
U8 ManifestType; /* 0x00 */
U8 Reserved01[3]; /* 0x01 */
U32 Reserved04[3]; /* 0x04 */
U8 NumImageReferences; /* 0x10 */
U8 ReleaseLevel; /* 0x11 */
U16 Reserved12; /* 0x12 */
U16 Reserved14; /* 0x14 */
U16 Flags; /* 0x16 */
U32 Reserved18[2]; /* 0x18 */
U16 VendorID; /* 0x20 */
U16 DeviceID; /* 0x22 */
U16 SubsystemVendorID; /* 0x24 */
U16 SubsystemID; /* 0x26 */
U32 Reserved28[2]; /* 0x28 */
MPI3_VERSION_UNION PackageSecurityVersion; /* 0x30 */
U32 Reserved34; /* 0x34 */
MPI3_COMP_IMAGE_VERSION PackageVersion; /* 0x38 */
U32 PackageVersionStringOffset; /* 0x40 */
U32 PackageBuildDateStringOffset; /* 0x44 */
U32 PackageBuildTimeStringOffset; /* 0x48 */
U32 Reserved4C; /* 0x4C */
U32 DiagAuthorizationIdentifier[16]; /* 0x50 */
MPI3_CI_MANIFEST_MPI_COMP_IMAGE_REF ComponentImageRef[MPI3_CI_MANIFEST_MPI_MAX]; /* 0x90 */ /* variable length */
/* StringData - offset of this field must be calculated */ /* variable length */
} MPI3_CI_MANIFEST_MPI, MPI3_POINTER PTR_MPI3_CI_MANIFEST_MPI,
Mpi3CIManifestMpi_t, MPI3_POINTER pMpi3CIManifestMpi_t;
/* defines for the ReleaseLevel field */
#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_DEV (0x00)
#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_PREALPHA (0x10)
#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_ALPHA (0x20)
#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_BETA (0x30)
#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_RC (0x40)
#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_GCA (0x50)
#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_POINT (0x60)
/* defines for the Flags field */
#define MPI3_CI_MANIFEST_MPI_FLAGS_DIAG_AUTHORIZATION (0x01)
/* defines for the SubsystemID field */
#define MPI3_CI_MANIFEST_MPI_SUBSYSTEMID_IGNORED (0xFFFF)
/* defines for the PackageVersionStringOffset field */
#define MPI3_CI_MANIFEST_MPI_PKG_VER_STR_OFF_UNSPECIFIED (0x00000000)
/* defines for the PackageBuildDateStringOffset field */
#define MPI3_CI_MANIFEST_MPI_PKG_BUILD_DATE_STR_OFF_UNSPECIFIED (0x00000000)
/* defines for the PackageBuildTimeStringOffset field */
#define MPI3_CI_MANIFEST_MPI_PKG_BUILD_TIME_STR_OFF_UNSPECIFIED (0x00000000)
typedef union _MPI3_CI_MANIFEST
{
MPI3_CI_MANIFEST_MPI Mpi;
U32 Dword[1];
} MPI3_CI_MANIFEST, MPI3_POINTER PTR_MPI3_CI_MANIFEST,
Mpi3CIManifest_t, MPI3_POINTER pMpi3CIManifest_t;
/* defines for ManifestType field */
#define MPI3_CI_MANIFEST_TYPE_MPI (0x00)
/*****************************************************************************
* Extended Image Data *
*****************************************************************************/
/* Extended Image Header */
typedef struct _MPI3_EXTENDED_IMAGE_HEADER
{
U8 ImageType; /* 0x00 */
U8 Reserved01[3]; /* 0x01 */
U32 Checksum; /* 0x04 */
U32 ImageSize; /* 0x08 */
U32 NextImageHeaderOffset; /* 0x0C */
U32 Reserved10[4]; /* 0x10 */
U32 IdentifyString[8]; /* 0x20 */
} MPI3_EXTENDED_IMAGE_HEADER, MPI3_POINTER PTR_MPI3_EXTENDED_IMAGE_HEADER,
Mpi3ExtendedImageHeader_t, MPI3_POINTER pMpi3ExtendedImageHeader_t;
/* useful offsets */
#define MPI3_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
#define MPI3_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
#define MPI3_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
#define MPI3_EXT_IMAGE_HEADER_SIZE (0x40)
/* defines for the ImageType field */
#define MPI3_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
#define MPI3_EXT_IMAGE_TYPE_NVDATA (0x03)
#define MPI3_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
#define MPI3_EXT_IMAGE_TYPE_ENCRYPTED_HASH (0x09)
#define MPI3_EXT_IMAGE_TYPE_RDE (0x0A)
#define MPI3_EXT_IMAGE_TYPE_AUXILIARY_PROCESSOR (0x0B)
#define MPI3_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80)
#define MPI3_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF)
/* Supported Device Data Format */
typedef struct _MPI3_SUPPORTED_DEVICE
{
U16 DeviceID; /* 0x00 */
U16 VendorID; /* 0x02 */
U16 DeviceIDMask; /* 0x04 */
U16 Reserved06; /* 0x06 */
U8 LowPCIRev; /* 0x08 */
U8 HighPCIRev; /* 0x09 */
U16 Reserved0A; /* 0x0A */
U32 Reserved0C; /* 0x0C */
} MPI3_SUPPORTED_DEVICE, MPI3_POINTER PTR_MPI3_SUPPORTED_DEVICE,
Mpi3SupportedDevice_t, MPI3_POINTER pMpi3SupportedDevice_t;
#ifndef MPI3_SUPPORTED_DEVICE_MAX
#define MPI3_SUPPORTED_DEVICE_MAX (1)
#endif /* MPI3_SUPPORTED_DEVICE_MAX */
/* Supported Devices Extended Image Data */
typedef struct _MPI3_SUPPORTED_DEVICES_DATA
{
U8 ImageVersion; /* 0x00 */
U8 Reserved01; /* 0x01 */
U8 NumDevices; /* 0x02 */
U8 Reserved03; /* 0x03 */
U32 Reserved04; /* 0x04 */
MPI3_SUPPORTED_DEVICE SupportedDevice[MPI3_SUPPORTED_DEVICE_MAX]; /* 0x08 */ /* variable length */
} MPI3_SUPPORTED_DEVICES_DATA, MPI3_POINTER PTR_MPI3_SUPPORTED_DEVICES_DATA,
Mpi3SupportedDevicesData_t, MPI3_POINTER pMpi3SupportedDevicesData_t;
#ifndef MPI3_ENCRYPTED_HASH_MAX
#define MPI3_ENCRYPTED_HASH_MAX (1)
#endif /* MPI3_ENCRYPTED_HASH_MAX */
/* Encrypted Hash Entry Format */
typedef struct _MPI3_ENCRYPTED_HASH_ENTRY
{
U8 HashImageType; /* 0x00 */
U8 HashAlgorithm; /* 0x01 */
U8 EncryptionAlgorithm; /* 0x02 */
U8 Reserved03; /* 0x03 */
U32 Reserved04; /* 0x04 */
U32 EncryptedHash[MPI3_ENCRYPTED_HASH_MAX]; /* 0x08 */ /* variable length */
} MPI3_ENCRYPTED_HASH_ENTRY, MPI3_POINTER PTR_MPI3_ENCRYPTED_HASH_ENTRY,
Mpi3EncryptedHashEntry_t, MPI3_POINTER pMpi3EncryptedHashEntry_t;
/* defines for the HashImageType field */
#define MPI3_HASH_IMAGE_TYPE_KEY_WITH_SIGNATURE (0x03)
/* defines for the HashAlgorithm field */
#define MPI3_HASH_ALGORITHM_VERSION_MASK (0xE0)
#define MPI3_HASH_ALGORITHM_VERSION_NONE (0x00)
#define MPI3_HASH_ALGORITHM_VERSION_SHA1 (0x20) /* Obsolete */
#define MPI3_HASH_ALGORITHM_VERSION_SHA2 (0x40)
#define MPI3_HASH_ALGORITHM_VERSION_SHA3 (0x60)
#define MPI3_HASH_ALGORITHM_SIZE_MASK (0x1F)
#define MPI3_HASH_ALGORITHM_SIZE_UNUSED (0x00)
#define MPI3_HASH_ALGORITHM_SIZE_SHA256 (0x01)
#define MPI3_HASH_ALGORITHM_SIZE_SHA512 (0x02)
#define MPI3_HASH_ALGORITHM_SIZE_SHA384 (0x03)
/* defines for the EncryptionAlgorithm field */
#define MPI3_ENCRYPTION_ALGORITHM_UNUSED (0x00)
#define MPI3_ENCRYPTION_ALGORITHM_RSA256 (0x01) /* Obsolete */
#define MPI3_ENCRYPTION_ALGORITHM_RSA512 (0x02) /* Obsolete */
#define MPI3_ENCRYPTION_ALGORITHM_RSA1024 (0x03) /* Obsolete */
#define MPI3_ENCRYPTION_ALGORITHM_RSA2048 (0x04)
#define MPI3_ENCRYPTION_ALGORITHM_RSA4096 (0x05)
#define MPI3_ENCRYPTION_ALGORITHM_RSA3072 (0x06)
#define MPI3_ENCRYPTION_ALGORITHM_ECDSA_P256 (0x07) /* NIST secp256r1 curve */
#define MPI3_ENCRYPTION_ALGORITHM_ECDSA_P384 (0x08) /* NIST secp384r1 curve */
#define MPI3_ENCRYPTION_ALGORITHM_ECDSA_P521 (0x09) /* NIST secp521r1 curve */
#ifndef MPI3_PUBLIC_KEY_MAX
#define MPI3_PUBLIC_KEY_MAX (1)
#endif /* MPI3_PUBLIC_KEY_MAX */
/* Encrypted Key with Hash Entry Format */
typedef struct _MPI3_ENCRYPTED_KEY_WITH_HASH_ENTRY
{
U8 HashImageType; /* 0x00 */
U8 HashAlgorithm; /* 0x01 */
U8 EncryptionAlgorithm; /* 0x02 */
U8 Reserved03; /* 0x03 */
U32 Reserved04; /* 0x04 */
U32 PublicKey[MPI3_PUBLIC_KEY_MAX]; /* 0x08 */ /* variable length */
/* EncryptedHash - offset of this field must be calculated */ /* variable length */
} MPI3_ENCRYPTED_KEY_WITH_HASH_ENTRY, MPI3_POINTER PTR_MPI3_ENCRYPTED_KEY_WITH_HASH_ENTRY,
Mpi3EncryptedKeyWithHashEntry_t, MPI3_POINTER pMpi3EncryptedKeyWithHashEntry_t;
#ifndef MPI3_ENCRYPTED_HASH_ENTRY_MAX
#define MPI3_ENCRYPTED_HASH_ENTRY_MAX (1)
#endif /* MPI3_ENCRYPTED_HASH_ENTRY_MAX */
/* Encrypted Hash Image Data */
typedef struct _MPI3_ENCRYPTED_HASH_DATA
{
U8 ImageVersion; /* 0x00 */
U8 NumHash; /* 0x01 */
U16 Reserved02; /* 0x02 */
U32 Reserved04; /* 0x04 */
MPI3_ENCRYPTED_HASH_ENTRY EncryptedHashEntry[MPI3_ENCRYPTED_HASH_ENTRY_MAX]; /* 0x08 */ /* variable length */
} MPI3_ENCRYPTED_HASH_DATA, MPI3_POINTER PTR_MPI3_ENCRYPTED_HASH_DATA,
Mpi3EncryptedHashData_t, MPI3_POINTER pMpi3EncryptedHashData_t;
#ifndef MPI3_AUX_PROC_DATA_MAX
#define MPI3_AUX_PROC_DATA_MAX (1)
#endif /* MPI3_ENCRYPTED_HASH_ENTRY_MAX */
/* Auxiliary Processor Extended Image Data */
typedef struct _MPI3_AUX_PROCESSOR_DATA
{
U8 BootMethod; /* 0x00 */
U8 NumLoadAddr; /* 0x01 */
U8 Reserved02; /* 0x02 */
U8 Type; /* 0x03 */
U32 Version; /* 0x04 */
U32 LoadAddress[8]; /* 0x08 */
U32 Reserved28[22]; /* 0x28 */
U32 AuxProcessorData[MPI3_AUX_PROC_DATA_MAX]; /* 0x80 */ /* variable length */
} MPI3_AUX_PROCESSOR_DATA, MPI3_POINTER PTR_MPI3_AUX_PROCESSOR_DATA,
Mpi3AuxProcessorData_t, MPI3_POINTER pMpi3AuxProcessorData_t;
#define MPI3_AUX_PROC_DATA_OFFSET (0x80)
/* defines for the BootMethod field */
#define MPI3_AUXPROCESSOR_BOOT_METHOD_MO_MSG (0x00)
#define MPI3_AUXPROCESSOR_BOOT_METHOD_MO_DOORBELL (0x01)
#define MPI3_AUXPROCESSOR_BOOT_METHOD_COMPONENT (0x02)
/* defines for the Type field */
#define MPI3_AUXPROCESSOR_TYPE_ARM_A15 (0x00)
#define MPI3_AUXPROCESSOR_TYPE_ARM_M0 (0x01)
#define MPI3_AUXPROCESSOR_TYPE_ARM_R4 (0x02)
#endif /* MPI30_IMAGE_H */

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/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2016-2023, Broadcom Inc. All rights reserved.
* Support: <fbsd-storage-driver.pdl@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
* 3. Neither the name of the Broadcom Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are
* those of the authors and should not be interpreted as representing
* official policies,either expressed or implied, of the FreeBSD Project.
*
* Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131
*
* Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD
*
*/
#ifndef MPI30_INIT_H
#define MPI30_INIT_H 1
/*****************************************************************************
* SCSI Initiator Messages *
****************************************************************************/
/*****************************************************************************
* SCSI IO Request Message *
****************************************************************************/
typedef struct _MPI3_SCSI_IO_CDB_EEDP32
{
U8 CDB[20]; /* 0x00 */
U32 PrimaryReferenceTag; /* 0x14 */
U16 PrimaryApplicationTag; /* 0x18 */
U16 PrimaryApplicationTagMask; /* 0x1A */
U32 TransferLength; /* 0x1C */
} MPI3_SCSI_IO_CDB_EEDP32, MPI3_POINTER PTR_MPI3_SCSI_IO_CDB_EEDP32,
Mpi3ScsiIoCdbEedp32_t, MPI3_POINTER pMpi3ScsiIoCdbEedp32_t;
typedef union _MPI3_SCSI_IO_CDB_UNION
{
U8 CDB32[32];
MPI3_SCSI_IO_CDB_EEDP32 EEDP32;
MPI3_SGE_SIMPLE SGE;
} MPI3_SCSI_IO_CDB_UNION, MPI3_POINTER PTR_MPI3_SCSI_IO_CDB_UNION,
Mpi3ScsiIoCdb_t, MPI3_POINTER pMpi3ScsiIoCdb_t;
typedef struct _MPI3_SCSI_IO_REQUEST
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 ChangeCount; /* 0x08 */
U16 DevHandle; /* 0x0A */
U32 Flags; /* 0x0C */
U32 SkipCount; /* 0x10 */
U32 DataLength; /* 0x14 */
U8 LUN[8]; /* 0x18 */
MPI3_SCSI_IO_CDB_UNION CDB; /* 0x20 */
MPI3_SGE_UNION SGL[4]; /* 0x40 */
} MPI3_SCSI_IO_REQUEST, MPI3_POINTER PTR_MPI3_SCSI_IO_REQUEST,
Mpi3SCSIIORequest_t, MPI3_POINTER pMpi3SCSIIORequest_t;
/**** Defines for the MsgFlags field ****/
#define MPI3_SCSIIO_MSGFLAGS_METASGL_VALID (0x80)
#define MPI3_SCSIIO_MSGFLAGS_DIVERT_TO_FIRMWARE (0x40)
/**** Defines for the Flags field ****/
#define MPI3_SCSIIO_FLAGS_LARGE_CDB (0x60000000)
#define MPI3_SCSIIO_FLAGS_CDB_16_OR_LESS (0x00000000)
#define MPI3_SCSIIO_FLAGS_CDB_GREATER_THAN_16 (0x20000000)
#define MPI3_SCSIIO_FLAGS_CDB_IN_SEPARATE_BUFFER (0x40000000)
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_MASK (0x07000000)
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_SIMPLEQ (0x00000000)
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_HEADOFQ (0x01000000)
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_ORDEREDQ (0x02000000)
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_ACAQ (0x04000000)
#define MPI3_SCSIIO_FLAGS_CMDPRI_MASK (0x00F00000)
#define MPI3_SCSIIO_FLAGS_CMDPRI_SHIFT (20)
#define MPI3_SCSIIO_FLAGS_DATADIRECTION_MASK (0x000C0000)
#define MPI3_SCSIIO_FLAGS_DATADIRECTION_NO_DATA_TRANSFER (0x00000000)
#define MPI3_SCSIIO_FLAGS_DATADIRECTION_WRITE (0x00040000)
#define MPI3_SCSIIO_FLAGS_DATADIRECTION_READ (0x00080000)
#define MPI3_SCSIIO_FLAGS_DMAOPERATION_MASK (0x00030000)
#define MPI3_SCSIIO_FLAGS_DMAOPERATION_HOST_PI (0x00010000)
#define MPI3_SCSIIO_FLAGS_DIVERT_REASON_MASK (0x000000F0)
#define MPI3_SCSIIO_FLAGS_DIVERT_REASON_IO_THROTTLING (0x00000010)
#define MPI3_SCSIIO_FLAGS_DIVERT_REASON_WRITE_SAME_TOO_LARGE (0x00000020)
#define MPI3_SCSIIO_FLAGS_DIVERT_REASON_PROD_SPECIFIC (0x00000080)
/**** Defines for the SGL field ****/
#define MPI3_SCSIIO_METASGL_INDEX (3)
/*****************************************************************************
* SCSI IO Error Reply Message *
****************************************************************************/
typedef struct _MPI3_SCSI_IO_REPLY
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 IOCUseOnly08; /* 0x08 */
U16 IOCStatus; /* 0x0A */
U32 IOCLogInfo; /* 0x0C */
U8 SCSIStatus; /* 0x10 */
U8 SCSIState; /* 0x11 */
U16 DevHandle; /* 0x12 */
U32 TransferCount; /* 0x14 */
U32 SenseCount; /* 0x18 */
U32 ResponseData; /* 0x1C */
U16 TaskTag; /* 0x20 */
U16 SCSIStatusQualifier; /* 0x22 */
U32 EEDPErrorOffset; /* 0x24 */
U16 EEDPObservedAppTag; /* 0x28 */
U16 EEDPObservedGuard; /* 0x2A */
U32 EEDPObservedRefTag; /* 0x2C */
U64 SenseDataBufferAddress; /* 0x30 */
} MPI3_SCSI_IO_REPLY, MPI3_POINTER PTR_MPI3_SCSI_IO_REPLY,
Mpi3SCSIIOReply_t, MPI3_POINTER pMpi3SCSIIOReply_t;
/**** Defines for the MsgFlags field ****/
#define MPI3_SCSIIO_REPLY_MSGFLAGS_REFTAG_OBSERVED_VALID (0x01)
#define MPI3_SCSIIO_REPLY_MSGFLAGS_APPTAG_OBSERVED_VALID (0x02)
#define MPI3_SCSIIO_REPLY_MSGFLAGS_GUARD_OBSERVED_VALID (0x04)
/**** Defines for the SCSIStatus field ****/
#define MPI3_SCSI_STATUS_GOOD (0x00)
#define MPI3_SCSI_STATUS_CHECK_CONDITION (0x02)
#define MPI3_SCSI_STATUS_CONDITION_MET (0x04)
#define MPI3_SCSI_STATUS_BUSY (0x08)
#define MPI3_SCSI_STATUS_INTERMEDIATE (0x10)
#define MPI3_SCSI_STATUS_INTERMEDIATE_CONDMET (0x14)
#define MPI3_SCSI_STATUS_RESERVATION_CONFLICT (0x18)
#define MPI3_SCSI_STATUS_COMMAND_TERMINATED (0x22)
#define MPI3_SCSI_STATUS_TASK_SET_FULL (0x28)
#define MPI3_SCSI_STATUS_ACA_ACTIVE (0x30)
#define MPI3_SCSI_STATUS_TASK_ABORTED (0x40)
/**** Defines for the SCSIState field ****/
#define MPI3_SCSI_STATE_SENSE_MASK (0x03)
#define MPI3_SCSI_STATE_SENSE_VALID (0x00)
#define MPI3_SCSI_STATE_SENSE_FAILED (0x01)
#define MPI3_SCSI_STATE_SENSE_BUFF_Q_EMPTY (0x02)
#define MPI3_SCSI_STATE_SENSE_NOT_AVAILABLE (0x03)
#define MPI3_SCSI_STATE_NO_SCSI_STATUS (0x04)
#define MPI3_SCSI_STATE_TERMINATED (0x08)
#define MPI3_SCSI_STATE_RESPONSE_DATA_VALID (0x10)
/**** Defines for the ResponseData field ****/
#define MPI3_SCSI_RSP_RESPONSECODE_MASK (0x000000FF)
#define MPI3_SCSI_RSP_RESPONSECODE_SHIFT (0)
#define MPI3_SCSI_RSP_ARI2_MASK (0x0000FF00)
#define MPI3_SCSI_RSP_ARI2_SHIFT (8)
#define MPI3_SCSI_RSP_ARI1_MASK (0x00FF0000)
#define MPI3_SCSI_RSP_ARI1_SHIFT (16)
#define MPI3_SCSI_RSP_ARI0_MASK (0xFF000000)
#define MPI3_SCSI_RSP_ARI0_SHIFT (24)
/**** Defines for the TaskTag field ****/
#define MPI3_SCSI_TASKTAG_UNKNOWN (0xFFFF)
/*****************************************************************************
* SCSI Task Management Request Message *
****************************************************************************/
typedef struct _MPI3_SCSI_TASK_MGMT_REQUEST
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 ChangeCount; /* 0x08 */
U16 DevHandle; /* 0x0A */
U16 TaskHostTag; /* 0x0C */
U8 TaskType; /* 0x0E */
U8 Reserved0F; /* 0x0F */
U16 TaskRequestQueueID; /* 0x10 */
U8 IOCUseOnly12; /* 0x12 */
U8 Reserved13; /* 0x13 */
U32 Reserved14; /* 0x14 */
U8 LUN[8]; /* 0x18 */
} MPI3_SCSI_TASK_MGMT_REQUEST, MPI3_POINTER PTR_MPI3_SCSI_TASK_MGMT_REQUEST,
Mpi3SCSITaskMgmtRequest_t, MPI3_POINTER pMpi3SCSITaskMgmtRequest_t;
/**** Defines for the MsgFlags field ****/
#define MPI3_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU (0x08)
/**** Defines for the TaskType field ****/
#define MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
#define MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK_SET (0x02)
#define MPI3_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
#define MPI3_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
#define MPI3_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
#define MPI3_SCSITASKMGMT_TASKTYPE_CLEAR_ACA (0x08)
#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK_SET (0x09)
#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_ASYNC_EVENT (0x0A)
#define MPI3_SCSITASKMGMT_TASKTYPE_I_T_NEXUS_RESET (0x0B)
/*****************************************************************************
* SCSI Task Management Reply Message *
****************************************************************************/
typedef struct _MPI3_SCSI_TASK_MGMT_REPLY
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 IOCUseOnly08; /* 0x08 */
U16 IOCStatus; /* 0x0A */
U32 IOCLogInfo; /* 0x0C */
U32 TerminationCount; /* 0x10 */
U32 ResponseData; /* 0x14 */
U32 Reserved18; /* 0x18 */
} MPI3_SCSI_TASK_MGMT_REPLY, MPI3_POINTER PTR_MPI3_SCSI_TASK_MGMT_REPLY,
Mpi3SCSITaskMgmtReply_t, MPI3_POINTER pMpi3SCSITaskMgmtReply_t;
/**** Defines for the ResponseData field - use MPI3_SCSI_RSP_ defines ****/
/**** Defines for the ResponseCode field - Byte 0 of ResponseData ****/
#define MPI3_SCSITASKMGMT_RSPCODE_TM_COMPLETE (0x00)
#define MPI3_SCSITASKMGMT_RSPCODE_INVALID_FRAME (0x02)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_FUNCTION_NOT_SUPPORTED (0x04)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_FAILED (0x05)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_SUCCEEDED (0x08)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_INVALID_LUN (0x09)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_OVERLAPPED_TAG (0x0A)
#define MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC (0x80)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_NVME_DENIED (0x81)
#endif /* MPI30_INIT_H */

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/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2016-2023, Broadcom Inc. All rights reserved.
* Support: <fbsd-storage-driver.pdl@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
* 3. Neither the name of the Broadcom Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are
* those of the authors and should not be interpreted as representing
* official policies,either expressed or implied, of the FreeBSD Project.
*
* Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131
*
* Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD
*
*/
#ifndef MPI30_PCI_H
#define MPI30_PCI_H 1
/*****************************************************************************
* NVMe Encapsulated Request Message *
****************************************************************************/
#ifndef MPI3_NVME_ENCAP_CMD_MAX
#define MPI3_NVME_ENCAP_CMD_MAX (1)
#endif /* MPI3_NVME_ENCAP_CMD_MAX */
typedef struct _MPI3_NVME_ENCAPSULATED_REQUEST
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 ChangeCount; /* 0x08 */
U16 DevHandle; /* 0x0A */
U16 EncapsulatedCommandLength; /* 0x0C */
U16 Flags; /* 0x0E */
U32 DataLength; /* 0x10 */
U32 Reserved14[3]; /* 0x14 */
U32 Command[MPI3_NVME_ENCAP_CMD_MAX]; /* 0x20 */ /* variable length */
} MPI3_NVME_ENCAPSULATED_REQUEST, MPI3_POINTER PTR_MPI3_NVME_ENCAPSULATED_REQUEST,
Mpi3NVMeEncapsulatedRequest_t, MPI3_POINTER pMpi3NVMeEncapsulatedRequest_t;
/**** Defines for the Flags field ****/
#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_MASK (0x0002)
#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_FAIL_ONLY (0x0000)
#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_ALL (0x0002)
#define MPI3_NVME_FLAGS_SUBMISSIONQ_MASK (0x0001)
#define MPI3_NVME_FLAGS_SUBMISSIONQ_IO (0x0000)
#define MPI3_NVME_FLAGS_SUBMISSIONQ_ADMIN (0x0001)
/*****************************************************************************
* NVMe Encapsulated Error Reply Message *
****************************************************************************/
typedef struct _MPI3_NVME_ENCAPSULATED_ERROR_REPLY
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 IOCUseOnly08; /* 0x08 */
U16 IOCStatus; /* 0x0A */
U32 IOCLogInfo; /* 0x0C */
U32 NVMeCompletionEntry[4]; /* 0x10 */
} MPI3_NVME_ENCAPSULATED_ERROR_REPLY, MPI3_POINTER PTR_MPI3_NVME_ENCAPSULATED_ERROR_REPLY,
Mpi3NVMeEncapsulatedErrorReply_t, MPI3_POINTER pMpi3NVMeEncapsulatedErrorReply_t;
#endif /* MPI30_PCI_H */

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/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2016-2023, Broadcom Inc. All rights reserved.
* Support: <fbsd-storage-driver.pdl@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
* 3. Neither the name of the Broadcom Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are
* those of the authors and should not be interpreted as representing
* official policies,either expressed or implied, of the FreeBSD Project.
*
* Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131
*
* Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD
*
*/
#ifndef MPI30_RAID_H
#define MPI30_RAID_H 1
#endif /* MPI30_RAID_H */

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/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2016-2023, Broadcom Inc. All rights reserved.
* Support: <fbsd-storage-driver.pdl@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
* 3. Neither the name of the Broadcom Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are
* those of the authors and should not be interpreted as representing
* official policies,either expressed or implied, of the FreeBSD Project.
*
* Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131
*
* Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD
*
*/
#ifndef MPI30_SAS_H
#define MPI30_SAS_H 1
/*****************************************************************************
* SAS Device Info Definitions *
****************************************************************************/
#define MPI3_SAS_DEVICE_INFO_SSP_TARGET (0x00000100)
#define MPI3_SAS_DEVICE_INFO_STP_SATA_TARGET (0x00000080)
#define MPI3_SAS_DEVICE_INFO_SMP_TARGET (0x00000040)
#define MPI3_SAS_DEVICE_INFO_SSP_INITIATOR (0x00000020)
#define MPI3_SAS_DEVICE_INFO_STP_INITIATOR (0x00000010)
#define MPI3_SAS_DEVICE_INFO_SMP_INITIATOR (0x00000008)
#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_MASK (0x00000007)
#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_NO_DEVICE (0x00000000)
#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_END_DEVICE (0x00000001)
#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_EXPANDER (0x00000002)
/*****************************************************************************
* SMP Passthrough Request Message *
****************************************************************************/
typedef struct _MPI3_SMP_PASSTHROUGH_REQUEST
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 ChangeCount; /* 0x08 */
U8 Reserved0A; /* 0x0A */
U8 IOUnitPort; /* 0x0B */
U32 Reserved0C[3]; /* 0x0C */
U64 SASAddress; /* 0x18 */
MPI3_SGE_SIMPLE RequestSGE; /* 0x20 */
MPI3_SGE_SIMPLE ResponseSGE; /* 0x30 */
} MPI3_SMP_PASSTHROUGH_REQUEST, MPI3_POINTER PTR_MPI3_SMP_PASSTHROUGH_REQUEST,
Mpi3SmpPassthroughRequest_t, MPI3_POINTER pMpi3SmpPassthroughRequest_t;
/*****************************************************************************
* SMP Passthrough Reply Message *
****************************************************************************/
typedef struct _MPI3_SMP_PASSTHROUGH_REPLY
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 IOCUseOnly08; /* 0x08 */
U16 IOCStatus; /* 0x0A */
U32 IOCLogInfo; /* 0x0C */
U16 ResponseDataLength; /* 0x10 */
U16 Reserved12; /* 0x12 */
} MPI3_SMP_PASSTHROUGH_REPLY, MPI3_POINTER PTR_MPI3_SMP_PASSTHROUGH_REPLY,
Mpi3SmpPassthroughReply_t, MPI3_POINTER pMpi3SmpPassthroughReply_t;
#endif /* MPI30_SAS_H */

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/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2016-2023, Broadcom Inc. All rights reserved.
* Support: <fbsd-storage-driver.pdl@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
* 3. Neither the name of the Broadcom Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are
* those of the authors and should not be interpreted as representing
* official policies,either expressed or implied, of the FreeBSD Project.
*
* Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131
*
* Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD
*
*/
#ifndef MPI30_TARG_H
#define MPI30_TARG_H 1
/*****************************************************************************
* Command Buffer Formats *
****************************************************************************/
typedef struct _MPI3_TARGET_SSP_CMD_BUFFER
{
U8 FrameType; /* 0x00 */
U8 Reserved01; /* 0x01 */
U16 InitiatorConnectionTag; /* 0x02 */
U32 HashedSourceSASAddress; /* 0x04 */
U16 Reserved08; /* 0x08 */
U16 Flags; /* 0x0A */
U32 Reserved0C; /* 0x0C */
U16 Tag; /* 0x10 */
U16 TargetPortTransferTag; /* 0x12 */
U32 DataOffset; /* 0x14 */
U8 LogicalUnitNumber[8]; /* 0x18 */
U8 Reserved20; /* 0x20 */
U8 TaskAttribute; /* 0x21 */
U8 Reserved22; /* 0x22 */
U8 AdditionalCDBLength; /* 0x23 */
U8 CDB[16]; /* 0x24 */
/* AdditionalCDBBytes field starts here */ /* 0x34 */
} MPI3_TARGET_SSP_CMD_BUFFER, MPI3_POINTER PTR_MPI3_TARGET_SSP_CMD_BUFFER,
Mpi3TargetSspCmdBuffer_t, MPI3_POINTER pMpi3TargetSspCmdBuffer_t;
typedef struct _MPI3_TARGET_SSP_TASK_BUFFER
{
U8 FrameType; /* 0x00 */
U8 Reserved01; /* 0x01 */
U16 InitiatorConnectionTag; /* 0x02 */
U32 HashedSourceSASAddress; /* 0x04 */
U16 Reserved08; /* 0x08 */
U16 Flags; /* 0x0A */
U32 Reserved0C; /* 0x0C */
U16 Tag; /* 0x10 */
U16 TargetPortTransferTag; /* 0x12 */
U32 DataOffset; /* 0x14 */
U8 LogicalUnitNumber[8]; /* 0x18 */
U16 Reserved20; /* 0x20 */
U8 TaskManagementFunction; /* 0x22 */
U8 Reserved23; /* 0x23 */
U16 ManagedTaskTag; /* 0x24 */
U16 Reserved26; /* 0x26 */
U32 Reserved28[3]; /* 0x28 */
} MPI3_TARGET_SSP_TASK_BUFFER, MPI3_POINTER PTR_MPI3_TARGET_SSP_TASK_BUFFER,
Mpi3TargetSspTaskBuffer_t, MPI3_POINTER pMpi3TargetSspTaskBuffer_t;
/**** Defines for the FrameType field ****/
#define MPI3_TARGET_FRAME_TYPE_COMMAND (0x06)
#define MPI3_TARGET_FRAME_TYPE_TASK (0x16)
/**** Defines for the HashedSourceSASAddress field ****/
#define MPI3_TARGET_HASHED_SAS_ADDRESS_MASK (0xFFFFFF00)
#define MPI3_TARGET_HASHED_SAS_ADDRESS_SHIFT (8)
/*****************************************************************************
* Target Command Buffer Post Base Request Message *
****************************************************************************/
typedef struct _MPI3_TARGET_CMD_BUF_POST_BASE_REQUEST
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 ChangeCount; /* 0x08 */
U8 BufferPostFlags; /* 0x0A */
U8 Reserved0B; /* 0x0B */
U16 MinReplyQueueID; /* 0x0C */
U16 MaxReplyQueueID; /* 0x0E */
U64 BaseAddress; /* 0x10 */
U16 CmdBufferLength; /* 0x18 */
U16 TotalCmdBuffers; /* 0x1A */
U32 Reserved1C; /* 0x1C */
} MPI3_TARGET_CMD_BUF_POST_BASE_REQUEST, MPI3_POINTER PTR_MPI3_TARGET_CMD_BUF_POST_BASE_REQUEST,
Mpi3TargetCmdBufPostBaseRequest_t, MPI3_POINTER pMpi3TargetCmdBufPostBaseRequest_t;
/**** Defines for the BufferPostFlags field ****/
#define MPI3_CMD_BUF_POST_BASE_FLAGS_DLAS_MASK (0x0C)
#define MPI3_CMD_BUF_POST_BASE_FLAGS_DLAS_SYSTEM (0x00)
#define MPI3_CMD_BUF_POST_BASE_FLAGS_DLAS_IOCUDP (0x04)
#define MPI3_CMD_BUF_POST_BASE_FLAGS_DLAS_IOCCTL (0x08)
#define MPI3_CMD_BUF_POST_BASE_FLAGS_AUTO_POST_ALL (0x01)
/**** Defines for the CmdBufferLength field ****/
#define MPI3_CMD_BUF_POST_BASE_MIN_BUF_LENGTH (0x34)
#define MPI3_CMD_BUF_POST_BASE_MAX_BUF_LENGTH (0x3FC)
/*****************************************************************************
* Target Command Buffer Post List Request Message *
****************************************************************************/
typedef struct _MPI3_TARGET_CMD_BUF_POST_LIST_REQUEST
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 ChangeCount; /* 0x08 */
U16 Reserved0A; /* 0x0A */
U8 CmdBufferCount; /* 0x0C */
U8 Reserved0D[3]; /* 0x0D */
U16 IoIndex[2]; /* 0x10 */
} MPI3_TARGET_CMD_BUF_POST_LIST_REQUEST, MPI3_POINTER PTR_MPI3_TARGET_CMD_BUF_POST_LIST_REQUEST,
Mpi3TargetCmdBufPostListRequest_t, MPI3_POINTER pMpi3TargetCmdBufPostListRequest_t;
/*****************************************************************************
* Target Command Buffer Post Base List Reply Message *
****************************************************************************/
typedef struct _MPI3_TARGET_CMD_BUF_POST_REPLY
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 IOCUseOnly08; /* 0x08 */
U16 IOCStatus; /* 0x0A */
U32 IOCLogInfo; /* 0x0C */
U8 CmdBufferCount; /* 0x10 */
U8 Reserved11[3]; /* 0x11 */
U16 IoIndex[2]; /* 0x14 */
} MPI3_TARGET_CMD_BUF_POST_REPLY, MPI3_POINTER PTR_MPI3_TARGET_CMD_BUF_POST_REPLY,
Mpi3TargetCmdBufPostReply_t, MPI3_POINTER pMpi3TargetCmdBufPostReply_t;
/*****************************************************************************
* Target Assist Request Message *
****************************************************************************/
typedef struct _MPI3_TARGET_ASSIST_REQUEST
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 ChangeCount; /* 0x08 */
U16 DevHandle; /* 0x0A */
U32 Flags; /* 0x0C */
U16 Reserved10; /* 0x10 */
U16 QueueTag; /* 0x12 */
U16 IoIndex; /* 0x14 */
U16 InitiatorConnectionTag; /* 0x16 */
U32 SkipCount; /* 0x18 */
U32 DataLength; /* 0x1C */
U32 PortTransferLength; /* 0x20 */
U32 PrimaryReferenceTag; /* 0x24 */
U16 PrimaryApplicationTag; /* 0x28 */
U16 PrimaryApplicationTagMask; /* 0x2A */
U32 RelativeOffset; /* 0x2C */
MPI3_SGE_UNION SGL[5]; /* 0x30 */
} MPI3_TARGET_ASSIST_REQUEST, MPI3_POINTER PTR_MPI3_TARGET_ASSIST_REQUEST,
Mpi3TargetAssistRequest_t, MPI3_POINTER pMpi3TargetAssistRequest_t;
/**** Defines for the MsgFlags field ****/
#define MPI3_TARGET_ASSIST_MSGFLAGS_METASGL_VALID (0x80)
/**** Defines for the Flags field ****/
#define MPI3_TARGET_ASSIST_FLAGS_REPOST_CMD_BUFFER (0x00200000)
#define MPI3_TARGET_ASSIST_FLAGS_AUTO_STATUS (0x00100000)
#define MPI3_TARGET_ASSIST_FLAGS_DATADIRECTION_MASK (0x000C0000)
#define MPI3_TARGET_ASSIST_FLAGS_DATADIRECTION_WRITE (0x00040000)
#define MPI3_TARGET_ASSIST_FLAGS_DATADIRECTION_READ (0x00080000)
#define MPI3_TARGET_ASSIST_FLAGS_DMAOPERATION_MASK (0x00030000)
#define MPI3_TARGET_ASSIST_FLAGS_DMAOPERATION_HOST_PI (0x00010000)
/**** Defines for the SGL field ****/
#define MPI3_TARGET_ASSIST_METASGL_INDEX (4)
/*****************************************************************************
* Target Status Send Request Message *
****************************************************************************/
typedef struct _MPI3_TARGET_STATUS_SEND_REQUEST
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 ChangeCount; /* 0x08 */
U16 DevHandle; /* 0x0A */
U16 ResponseIULength; /* 0x0C */
U16 Flags; /* 0x0E */
U16 Reserved10; /* 0x10 */
U16 QueueTag; /* 0x12 */
U16 IoIndex; /* 0x14 */
U16 InitiatorConnectionTag; /* 0x16 */
U32 IOCUseOnly18[6]; /* 0x18 */
U32 IOCUseOnly30[4]; /* 0x30 */
MPI3_SGE_UNION SGL; /* 0x40 */
} MPI3_TARGET_STATUS_SEND_REQUEST, MPI3_POINTER PTR_MPI3_TARGET_STATUS_SEND_REQUEST,
Mpi3TargetStatusSendRequest_t, MPI3_POINTER pMpi3TargetStatusSendRequest_t;
/**** Defines for the Flags field ****/
#define MPI3_TSS_FLAGS_REPOST_CMD_BUFFER (0x0020)
#define MPI3_TSS_FLAGS_AUTO_SEND_GOOD_STATUS (0x0010)
/*****************************************************************************
* Standard Target Mode Reply Message *
****************************************************************************/
typedef struct _MPI3_TARGET_STANDARD_REPLY
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 IOCUseOnly08; /* 0x08 */
U16 IOCStatus; /* 0x0A */
U32 IOCLogInfo; /* 0x0C */
U32 TransferCount; /* 0x10 */
} MPI3_TARGET_STANDARD_REPLY, MPI3_POINTER PTR_MPI3_TARGET_STANDARD_REPLY,
Mpi3TargetStandardReply_t, MPI3_POINTER pMpi3TargetStandardReply_t;
/*****************************************************************************
* Target Mode Abort Request Message *
****************************************************************************/
typedef struct _MPI3_TARGET_MODE_ABORT_REQUEST
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 ChangeCount; /* 0x08 */
U8 AbortType; /* 0x0A */
U8 Reserved0B; /* 0x0B */
U16 RequestQueueIDToAbort; /* 0x0C */
U16 HostTagToAbort; /* 0x0E */
U16 DevHandle; /* 0x10 */
U8 IOCUseOnly12; /* 0x12 */
U8 Reserved13; /* 0x13 */
} MPI3_TARGET_MODE_ABORT_REQUEST, MPI3_POINTER PTR_MPI3_TARGET_MODE_ABORT_REQUEST,
Mpi3TargetModeAbortRequest_t, MPI3_POINTER pMpi3TargetModeAbortRequest_t;
/**** Defines for the AbortType field ****/
#define MPI3_TARGET_MODE_ABORT_ALL_CMD_BUFFERS (0x00)
#define MPI3_TARGET_MODE_ABORT_EXACT_IO_REQUEST (0x01)
#define MPI3_TARGET_MODE_ABORT_ALL_COMMANDS (0x02)
/*****************************************************************************
* Target Mode Abort Reply Message *
****************************************************************************/
typedef struct _MPI3_TARGET_MODE_ABORT_REPLY
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 IOCUseOnly08; /* 0x08 */
U16 IOCStatus; /* 0x0A */
U32 IOCLogInfo; /* 0x0C */
U32 AbortCount; /* 0x10 */
} MPI3_TARGET_MODE_ABORT_REPLY, MPI3_POINTER PTR_MPI3_TARGET_MODE_ABORT_REPLY,
Mpi3TargetModeAbortReply_t, MPI3_POINTER pMpi3TargetModeAbortReply_t;
#endif /* MPI30_TARG_H */

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/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2016-2023, Broadcom Inc. All rights reserved.
* Support: <fbsd-storage-driver.pdl@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
* 3. Neither the name of the Broadcom Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are
* those of the authors and should not be interpreted as representing
* official policies,either expressed or implied, of the FreeBSD Project.
*
* Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131
*
* Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD
*
*/
#ifndef MPI30_TOOL_H
#define MPI30_TOOL_H 1
/*****************************************************************************
* Toolbox Messages *
*****************************************************************************/
/*****************************************************************************
* Clean Tool Request Message *
*****************************************************************************/
typedef struct _MPI3_TOOL_CLEAN_REQUEST
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 ChangeCount; /* 0x08 */
U8 Tool; /* 0x0A */
U8 Reserved0B; /* 0x0B */
U32 Area; /* 0x0C */
} MPI3_TOOL_CLEAN_REQUEST, MPI3_POINTER PTR_MPI3_TOOL_CLEAN_REQUEST,
Mpi3ToolCleanRequest_t, MPI3_POINTER pMpi3ToolCleanRequest_t;
/**** Defines for the Tool field ****/
#define MPI3_TOOLBOX_TOOL_CLEAN (0x01)
#define MPI3_TOOLBOX_TOOL_ISTWI_READ_WRITE (0x02)
#define MPI3_TOOLBOX_TOOL_DIAGNOSTIC_CLI (0x03)
#define MPI3_TOOLBOX_TOOL_LANE_MARGINING (0x04)
#define MPI3_TOOLBOX_TOOL_RECOVER_DEVICE (0x05)
#define MPI3_TOOLBOX_TOOL_LOOPBACK (0x06)
/**** Bitfield definitions for Area field ****/
#define MPI3_TOOLBOX_CLEAN_AREA_BIOS_BOOT_SERVICES (0x00000008)
#define MPI3_TOOLBOX_CLEAN_AREA_ALL_BUT_MFG (0x00000002)
#define MPI3_TOOLBOX_CLEAN_AREA_NVSTORE (0x00000001)
/*****************************************************************************
* ISTWI Read Write Tool Request Message *
*****************************************************************************/
typedef struct _MPI3_TOOL_ISTWI_READ_WRITE_REQUEST
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 ChangeCount; /* 0x08 */
U8 Tool; /* 0x0A */
U8 Flags; /* 0x0B */
U8 DevIndex; /* 0x0C */
U8 Action; /* 0x0D */
U16 Reserved0E; /* 0x0E */
U16 TxDataLength; /* 0x10 */
U16 RxDataLength; /* 0x12 */
U32 Reserved14[3]; /* 0x14 */
MPI3_MAN11_ISTWI_DEVICE_FORMAT IstwiDevice; /* 0x20 */
MPI3_SGE_UNION SGL; /* 0x30 */
} MPI3_TOOL_ISTWI_READ_WRITE_REQUEST, MPI3_POINTER PTR_MPI3_TOOL_ISTWI_READ_WRITE_REQUEST,
Mpi3ToolIstwiReadWriteRequest_t, MPI3_POINTER pMpi3ToolIstwiReadWRiteRequest_t;
/**** Bitfield definitions for Flags field ****/
#define MPI3_TOOLBOX_ISTWI_FLAGS_AUTO_RESERVE_RELEASE (0x80)
#define MPI3_TOOLBOX_ISTWI_FLAGS_ADDRESS_MODE_MASK (0x04)
#define MPI3_TOOLBOX_ISTWI_FLAGS_ADDRESS_MODE_DEVINDEX (0x00)
#define MPI3_TOOLBOX_ISTWI_FLAGS_ADDRESS_MODE_DEVICE_FIELD (0x04)
#define MPI3_TOOLBOX_ISTWI_FLAGS_PAGE_ADDRESS_MASK (0x03)
/**** Definitions for the Action field ****/
#define MPI3_TOOLBOX_ISTWI_ACTION_RESERVE_BUS (0x00)
#define MPI3_TOOLBOX_ISTWI_ACTION_RELEASE_BUS (0x01)
#define MPI3_TOOLBOX_ISTWI_ACTION_RESET (0x02)
#define MPI3_TOOLBOX_ISTWI_ACTION_READ_DATA (0x03)
#define MPI3_TOOLBOX_ISTWI_ACTION_WRITE_DATA (0x04)
#define MPI3_TOOLBOX_ISTWI_ACTION_SEQUENCE (0x05)
/**** Defines for the IstwiDevice field - refer to struct definition in mpi30_cnfg.h ****/
/*****************************************************************************
* ISTWI Read Write Tool Reply Message *
*****************************************************************************/
typedef struct _MPI3_TOOL_ISTWI_READ_WRITE_REPLY
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 IOCUseOnly08; /* 0x08 */
U16 IOCStatus; /* 0x0A */
U32 IOCLogInfo; /* 0x0C */
U16 IstwiStatus; /* 0x10 */
U16 Reserved12; /* 0x12 */
U16 TxDataCount; /* 0x14 */
U16 RxDataCount; /* 0x16 */
} MPI3_TOOL_ISTWI_READ_WRITE_REPLY, MPI3_POINTER PTR_MPI3_TOOL_ISTWI_READ_WRITE_REPLY,
Mpi3ToolIstwiReadWriteReply_t, MPI3_POINTER pMpi3ToolIstwiReadWRiteReply_t;
/*****************************************************************************
* Diagnostic CLI Tool Request Message *
*****************************************************************************/
typedef struct _MPI3_TOOL_DIAGNOSTIC_CLI_REQUEST
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 ChangeCount; /* 0x08 */
U8 Tool; /* 0x0A */
U8 Reserved0B; /* 0x0B */
U32 CommandDataLength; /* 0x0C */
U32 ResponseDataLength; /* 0x10 */
U32 Reserved14[3]; /* 0x14 */
MPI3_SGE_UNION SGL; /* 0x20 */
} MPI3_TOOL_DIAGNOSTIC_CLI_REQUEST, MPI3_POINTER PTR_MPI3_TOOL_DIAGNOSTIC_CLI_REQUEST,
Mpi3ToolDiagnosticCliRequest_t, MPI3_POINTER pMpi3ToolDiagnosticCliRequest_t;
/*****************************************************************************
* Diagnostic CLI Tool Reply Message *
*****************************************************************************/
typedef struct _MPI3_TOOL_DIAGNOSTIC_CLI_REPLY
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 IOCUseOnly08; /* 0x08 */
U16 IOCStatus; /* 0x0A */
U32 IOCLogInfo; /* 0x0C */
U32 ReturnedDataLength; /* 0x10 */
} MPI3_TOOL_DIAGNOSTIC_CLI_REPLY, MPI3_POINTER PTR_MPI3_TOOL_DIAGNOSTIC_CLI_REPLY,
Mpi3ToolDiagnosticCliReply_t, MPI3_POINTER pMpi3ToolDiagnosticCliReply_t;
/*****************************************************************************
* Lane Margining Tool Request Message *
*****************************************************************************/
typedef struct _MPI3_TOOL_LANE_MARGIN_REQUEST
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 ChangeCount; /* 0x08 */
U8 Tool; /* 0x0A */
U8 Reserved0B; /* 0x0B */
U8 Action; /* 0x0C */
U8 SwitchPort; /* 0x0D */
U16 DevHandle; /* 0x0E */
U8 StartLane; /* 0x10 */
U8 NumLanes; /* 0x11 */
U16 Reserved12; /* 0x12 */
U32 Reserved14[3]; /* 0x14 */
MPI3_SGE_UNION SGL; /* 0x20 */
} MPI3_TOOL_LANE_MARGIN_REQUEST, MPI3_POINTER PTR_MPI3_TOOL_LANE_MARGIN_REQUEST,
Mpi3ToolIstwiLaneMarginRequest_t, MPI3_POINTER pMpi3ToolLaneMarginRequest_t;
/**** Definitions for the Action field ****/
#define MPI3_TOOLBOX_LM_ACTION_ENTER (0x00)
#define MPI3_TOOLBOX_LM_ACTION_EXIT (0x01)
#define MPI3_TOOLBOX_LM_ACTION_READ (0x02)
#define MPI3_TOOLBOX_LM_ACTION_WRITE (0x03)
typedef struct _MPI3_LANE_MARGIN_ELEMENT
{
U16 Control; /* 0x00 */
U16 Status; /* 0x02 */
} MPI3_LANE_MARGIN_ELEMENT, MPI3_POINTER PTR_MPI3_LANE_MARGIN_ELEMENT,
Mpi3LaneMarginElement_t, MPI3_POINTER pMpi3LaneMarginElement_t;
/*****************************************************************************
* Lane Margining Tool Reply Message *
*****************************************************************************/
typedef struct _MPI3_TOOL_LANE_MARGIN_REPLY
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 IOCUseOnly08; /* 0x08 */
U16 IOCStatus; /* 0x0A */
U32 IOCLogInfo; /* 0x0C */
U32 ReturnedDataLength; /* 0x10 */
} MPI3_TOOL_LANE_MARGIN_REPLY, MPI3_POINTER PTR_MPI3_TOOL_LANE_MARGIN_REPLY,
Mpi3ToolLaneMarginReply_t, MPI3_POINTER pMpi3ToolLaneMarginReply_t;
/*****************************************************************************
* Recover Device Request Message *
*****************************************************************************/
typedef struct _MPI3_TOOL_RECOVER_DEVICE_REQUEST
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 ChangeCount; /* 0x08 */
U8 Tool; /* 0x0A */
U8 Reserved0B; /* 0x0B */
U8 Action; /* 0x0C */
U8 Reserved0D; /* 0x0D */
U16 DevHandle; /* 0x0E */
} MPI3_TOOL_RECOVER_DEVICE_REQUEST, MPI3_POINTER PTR_MPI3_TOOL_RECOVER_DEVICE_REQUEST,
Mpi3ToolRecoverDeviceRequest_t, MPI3_POINTER pMpi3ToolRecoverDeviceRequest_t;
/**** Bitfield definitions for the Action field ****/
#define MPI3_TOOLBOX_RD_ACTION_START (0x01)
#define MPI3_TOOLBOX_RD_ACTION_GET_STATUS (0x02)
#define MPI3_TOOLBOX_RD_ACTION_ABORT (0x03)
/*****************************************************************************
* Recover Device Reply Message *
*****************************************************************************/
typedef struct _MPI3_TOOL_RECOVER_DEVICE_REPLY
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 IOCUseOnly08; /* 0x08 */
U16 IOCStatus; /* 0x0A */
U32 IOCLogInfo; /* 0x0C */
U8 Status; /* 0x10 */
U8 Reserved11; /* 0x11 */
U16 Reserved1C; /* 0x12 */
} MPI3_TOOL_RECOVER_DEVICE_REPLY, MPI3_POINTER PTR_MPI3_TOOL_RECOVER_DEVICE_REPLY,
Mpi3ToolRecoverDeviceReply_t, MPI3_POINTER pMpi3ToolRecoverDeviceReply_t;
/**** Bitfield definitions for the Status field ****/
#define MPI3_TOOLBOX_RD_STATUS_NOT_NEEDED (0x01)
#define MPI3_TOOLBOX_RD_STATUS_NEEDED (0x02)
#define MPI3_TOOLBOX_RD_STATUS_IN_PROGRESS (0x03)
#define MPI3_TOOLBOX_RD_STATUS_ABORTING (0x04)
/*****************************************************************************
* Loopback Tool Request Message *
*****************************************************************************/
typedef struct _MPI3_TOOL_LOOPBACK_REQUEST
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 ChangeCount; /* 0x08 */
U8 Tool; /* 0x0A */
U8 Reserved0B; /* 0x0B */
U32 Reserved0C; /* 0x0C */
U64 Phys; /* 0x10 */
} MPI3_TOOL_LOOPBACK_REQUEST, MPI3_POINTER PTR_MPI3_TOOL_LOOPBACK_REQUEST,
Mpi3ToolLoopbackRequest_t, MPI3_POINTER pMpi3ToolLoopbackRequest_t;
/*****************************************************************************
* Loopback Tool Reply Message *
*****************************************************************************/
typedef struct _MPI3_TOOL_LOOPBACK_REPLY
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 IOCUseOnly08; /* 0x08 */
U16 IOCStatus; /* 0x0A */
U32 IOCLogInfo; /* 0x0C */
U64 TestedPhys; /* 0x10 */
U64 FailedPhys; /* 0x18 */
} MPI3_TOOL_LOOPBACK_REPLY, MPI3_POINTER PTR_MPI3_TOOL_LOOPBACK_REPLY,
Mpi3ToolLoopbackReply_t, MPI3_POINTER pMpi3ToolLoopbackReply_t;
/*****************************************************************************
* Diagnostic Buffer Messages *
*****************************************************************************/
/*****************************************************************************
* Diagnostic Buffer Post Request Message *
*****************************************************************************/
typedef struct _MPI3_DIAG_BUFFER_POST_REQUEST
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 ChangeCount; /* 0x08 */
U16 Reserved0A; /* 0x0A */
U8 Type; /* 0x0C */
U8 Reserved0D; /* 0x0D */
U16 Reserved0E; /* 0x0E */
U64 Address; /* 0x10 */
U32 Length; /* 0x18 */
U32 Reserved1C; /* 0x1C */
} MPI3_DIAG_BUFFER_POST_REQUEST, MPI3_POINTER PTR_MPI3_DIAG_BUFFER_POST_REQUEST,
Mpi3DiagBufferPostRequest_t, MPI3_POINTER pMpi3DiagBufferPostRequest_t;
/**** Defines for the MsgFlags field ****/
#define MPI3_DIAG_BUFFER_POST_MSGFLAGS_SEGMENTED (0x01)
/**** Defines for the Type field ****/
#define MPI3_DIAG_BUFFER_TYPE_TRACE (0x01)
#define MPI3_DIAG_BUFFER_TYPE_FW (0x02)
#define MPI3_DIAG_BUFFER_TYPE_DRIVER (0x10)
#define MPI3_DIAG_BUFFER_TYPE_FDL (0x20)
#define MPI3_DIAG_BUFFER_MIN_PRODUCT_SPECIFIC (0xF0)
#define MPI3_DIAG_BUFFER_MAX_PRODUCT_SPECIFIC (0xFF)
/*****************************************************************************
* DRIVER DIAGNOSTIC Buffer *
*****************************************************************************/
typedef struct _MPI3_DRIVER_BUFFER_HEADER
{
U32 Signature; /* 0x00 */
U16 HeaderSize; /* 0x04 */
U16 RTTFileHeaderOffset; /* 0x06 */
U32 Flags; /* 0x08 */
U32 CircularBufferSize; /* 0x0C */
U32 LogicalBufferEnd; /* 0x10 */
U32 LogicalBufferStart; /* 0x14 */
U32 IOCUseOnly18[2]; /* 0x18 */
U32 Reserved20[760]; /* 0x20 - 0xBFC */
U32 ReservedRTTRACE[256]; /* 0xC00 - 0xFFC */
} MPI3_DRIVER_BUFFER_HEADER, MPI3_POINTER PTR_MPI3_DRIVER_BUFFER_HEADER,
Mpi3DriverBufferHeader_t, MPI3_POINTER pMpi3DriverBufferHeader_t;
/**** Defines for the Type field ****/
#define MPI3_DRIVER_DIAG_BUFFER_HEADER_SIGNATURE_CIRCULAR (0x43495243)
/**** Defines for the Flags field ****/
#define MPI3_DRIVER_DIAG_BUFFER_HEADER_FLAGS_CIRCULAR_BUF_FORMAT_MASK (0x00000003)
#define MPI3_DRIVER_DIAG_BUFFER_HEADER_FLAGS_CIRCULAR_BUF_FORMAT_ASCII (0x00000000)
#define MPI3_DRIVER_DIAG_BUFFER_HEADER_FLAGS_CIRCULAR_BUF_FORMAT_RTTRACE (0x00000001)
/*****************************************************************************
* Diagnostic Buffer Manage Request Message *
*****************************************************************************/
typedef struct _MPI3_DIAG_BUFFER_MANAGE_REQUEST
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 ChangeCount; /* 0x08 */
U16 Reserved0A; /* 0x0A */
U8 Type; /* 0x0C */
U8 Action; /* 0x0D */
U16 Reserved0E; /* 0x0E */
} MPI3_DIAG_BUFFER_MANAGE_REQUEST, MPI3_POINTER PTR_MPI3_DIAG_BUFFER_MANAGE_REQUEST,
Mpi3DiagBufferManageRequest_t, MPI3_POINTER pMpi3DiagBufferManageRequest_t;
/**** Defines for the Type field - use MPI3_DIAG_BUFFER_TYPE_ values ****/
/**** Defined for the Action field ****/
#define MPI3_DIAG_BUFFER_ACTION_RELEASE (0x01)
#define MPI3_DIAG_BUFFER_ACTION_PAUSE (0x02)
#define MPI3_DIAG_BUFFER_ACTION_RESUME (0x03)
/*****************************************************************************
* Diagnostic Buffer Upload Request Message *
*****************************************************************************/
typedef struct _MPI3_DIAG_BUFFER_UPLOAD_REQUEST
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 ChangeCount; /* 0x08 */
U16 Reserved0A; /* 0x0A */
U8 Type; /* 0x0C */
U8 Flags; /* 0x0D */
U16 Reserved0E; /* 0x0E */
U64 Context; /* 0x10 */
U32 Reserved18; /* 0x18 */
U32 Reserved1C; /* 0x1C */
MPI3_SGE_UNION SGL; /* 0x20 */
} MPI3_DIAG_BUFFER_UPLOAD_REQUEST, MPI3_POINTER PTR_MPI3_DIAG_BUFFER_UPLOAD_REQUEST,
Mpi3DiagBufferUploadRequest_t, MPI3_POINTER pMpi3DiagBufferUploadRequest_t;
/**** Defines for the Type field - use MPI3_DIAG_BUFFER_TYPE_ values ****/
/**** Defined for the Flags field ****/
#define MPI3_DIAG_BUFFER_UPLOAD_FLAGS_FORMAT_MASK (0x01)
#define MPI3_DIAG_BUFFER_UPLOAD_FLAGS_FORMAT_DECODED (0x00)
#define MPI3_DIAG_BUFFER_UPLOAD_FLAGS_FORMAT_ENCODED (0x01)
/*****************************************************************************
* Diagnostic Buffer Upload Reply Message *
*****************************************************************************/
typedef struct _MPI3_DIAG_BUFFER_UPLOAD_REPLY
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 IOCUseOnly08; /* 0x08 */
U16 IOCStatus; /* 0x0A */
U32 IOCLogInfo; /* 0x0C */
U64 Context; /* 0x10 */
U32 ReturnedDataLength; /* 0x18 */
U32 Reserved1C; /* 0x1C */
} MPI3_DIAG_BUFFER_UPLOAD_REPLY, MPI3_POINTER PTR_MPI3_DIAG_BUFFER_UPLOAD_REPLY,
Mpi3DiagBufferUploadReply_t, MPI3_POINTER pMpi3DiagBufferUploadReply_t;
#endif /* MPI30_TOOL_H */

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sys/dev/mpi3mr/mpi/mpi30_transport.h Normal file
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@ -0,0 +1,748 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2016-2023, Broadcom Inc. All rights reserved.
* Support: <fbsd-storage-driver.pdl@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
* 3. Neither the name of the Broadcom Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are
* those of the authors and should not be interpreted as representing
* official policies,either expressed or implied, of the FreeBSD Project.
*
* Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131
*
* Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD
*
*/
/*
* Version History
* ---------------
*
* Date Version Description
* -------- ----------- ------------------------------------------------------
* 11-30-18 03.00.00.08 Corresponds to Fusion-MPT MPI 3.0 Specification Rev H.
* 02-08-19 03.00.00.09 Corresponds to Fusion-MPT MPI 3.0 Specification Rev I.
* 05-03-19 03.00.00.10 Corresponds to Fusion-MPT MPI 3.0 Specification Rev J.
* 08-30-19 03.00.00.12 Corresponds to Fusion-MPT MPI 3.0 Specification Rev L.
* 11-01-19 03.00.00.13 Corresponds to Fusion-MPT MPI 3.0 Specification Rev M.
* 12-16-19 03.00.00.14 Corresponds to Fusion-MPT MPI 3.0 Specification Rev N.
* 02-28-20 03.00.00.15 Corresponds to Fusion-MPT MPI 3.0 Specification Rev O.
* 05-01-20 03.00.00.16 Corresponds to Fusion-MPT MPI 3.0 Specification Rev P.
* 06-26-20 03.00.00.17 Corresponds to Fusion-MPT MPI 3.0 Specification Rev Q.
* 08-28-20 03.00.00.18 Corresponds to Fusion-MPT MPI 3.0 Specification Rev R.
* 10-30-20 03.00.00.19 Corresponds to Fusion-MPT MPI 3.0 Specification Rev S.
* 12-18-20 03.00.00.20 Corresponds to Fusion-MPT MPI 3.0 Specification Rev T.
* 02-09-21 03.00.20.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev T - Interim Release 1.
* 02-26-21 03.00.21.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev U.
* 04-16-21 03.00.21.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev U - Interim Release 1.
* 04-28-21 03.00.21.02 Corresponds to Fusion-MPT MPI 3.0 Specification Rev U - Interim Release 2.
* 05-28-21 03.00.22.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev V.
* 07-23-21 03.00.22.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev V - Interim Release 1.
* 09-03-21 03.00.23.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 23.
* 10-23-21 03.00.23.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 23 - Interim Release 1.
* 12-03-21 03.00.24.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 24.
* 02-25-22 03.00.25.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 25.
* 06-03-22 03.00.26.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 26.
* 08-09-22 03.00.26.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 26 - Interim Release 1.
* 09-02-22 03.00.27.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 27.
* 10-20-22 03.00.27.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 27 - Interim Release 1.
* 12-02-22 03.00.28.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 28.
* 02-24-22 03.00.29.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 29.
*/
#ifndef MPI30_TRANSPORT_H
#define MPI30_TRANSPORT_H 1
/*****************************************************************************
* Common version structure/union used in *
* messages and configuration pages *
****************************************************************************/
typedef struct _MPI3_VERSION_STRUCT
{
U8 Dev; /* 0x00 */
U8 Unit; /* 0x01 */
U8 Minor; /* 0x02 */
U8 Major; /* 0x03 */
} MPI3_VERSION_STRUCT, MPI3_POINTER PTR_MPI3_VERSION_STRUCT,
Mpi3VersionStruct_t, MPI3_POINTER pMpi3VersionStruct_t;
typedef union _MPI3_VERSION_UNION
{
MPI3_VERSION_STRUCT Struct;
U32 Word;
} MPI3_VERSION_UNION, MPI3_POINTER PTR_MPI3_VERSION_UNION,
Mpi3VersionUnion_t, MPI3_POINTER pMpi3VersionUnion_t;
/****** Version constants for this revision ****/
#define MPI3_VERSION_MAJOR (3)
#define MPI3_VERSION_MINOR (0)
#define MPI3_VERSION_UNIT (29)
#define MPI3_VERSION_DEV (0)
/****** DevHandle definitions *****/
#define MPI3_DEVHANDLE_INVALID (0xFFFF)
/*****************************************************************************
* System Interface Register Definitions *
****************************************************************************/
typedef struct _MPI3_SYSIF_OPER_QUEUE_INDEXES
{
U16 ProducerIndex; /* 0x00 */
U16 Reserved02; /* 0x02 */
U16 ConsumerIndex; /* 0x04 */
U16 Reserved06; /* 0x06 */
} MPI3_SYSIF_OPER_QUEUE_INDEXES, MPI3_POINTER PTR_MPI3_SYSIF_OPER_QUEUE_INDEXES;
typedef volatile struct _MPI3_SYSIF_REGISTERS
{
U64 IOCInformation; /* 0x00 */
MPI3_VERSION_UNION Version; /* 0x08 */
U32 Reserved0C[2]; /* 0x0C */
U32 IOCConfiguration; /* 0x14 */
U32 Reserved18; /* 0x18 */
U32 IOCStatus; /* 0x1C */
U32 Reserved20; /* 0x20 */
U32 AdminQueueNumEntries; /* 0x24 */
U64 AdminRequestQueueAddress; /* 0x28 */
U64 AdminReplyQueueAddress; /* 0x30 */
U32 Reserved38[2]; /* 0x38 */
U32 CoalesceControl; /* 0x40 */
U32 Reserved44[1007]; /* 0x44 */
U16 AdminRequestQueuePI; /* 0x1000 */
U16 Reserved1002; /* 0x1002 */
U16 AdminReplyQueueCI; /* 0x1004 */
U16 Reserved1006; /* 0x1006 */
MPI3_SYSIF_OPER_QUEUE_INDEXES OperQueueIndexes[383]; /* 0x1008 */
U32 Reserved1C00; /* 0x1C00 */
U32 WriteSequence; /* 0x1C04 */
U32 HostDiagnostic; /* 0x1C08 */
U32 Reserved1C0C; /* 0x1C0C */
U32 Fault; /* 0x1C10 */
U32 FaultInfo[3]; /* 0x1C14 */
U32 Reserved1C20[4]; /* 0x1C20 */
U64 HCBAddress; /* 0x1C30 */
U32 HCBSize; /* 0x1C38 */
U32 Reserved1C3C; /* 0x1C3C */
U32 ReplyFreeHostIndex; /* 0x1C40 */
U32 SenseBufferFreeHostIndex; /* 0x1C44 */
U32 Reserved1C48[2]; /* 0x1C48 */
U64 DiagRWData; /* 0x1C50 */
U64 DiagRWAddress; /* 0x1C58 */
U16 DiagRWControl; /* 0x1C60 */
U16 DiagRWStatus; /* 0x1C62 */
U32 Reserved1C64[35]; /* 0x1C64 */
U32 Scratchpad[4]; /* 0x1CF0 */
U32 Reserved1D00[192]; /* 0x1D00 */
U32 DeviceAssignedRegisters[2048]; /* 0x2000 */
} MPI3_SYSIF_REGS, MPI3_POINTER PTR_MPI3_SYSIF_REGS,
Mpi3SysIfRegs_t, MPI3_POINTER pMpi3SysIfRegs_t;
/**** Defines for the IOCInformation register ****/
#define MPI3_SYSIF_IOC_INFO_LOW_OFFSET (0x00000000)
#define MPI3_SYSIF_IOC_INFO_HIGH_OFFSET (0x00000004)
#define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK (0xFF000000)
#define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT (24)
#define MPI3_SYSIF_IOC_INFO_LOW_HCB_DISABLED (0x00000001)
/**** Defines for the IOCConfiguration register ****/
#define MPI3_SYSIF_IOC_CONFIG_OFFSET (0x00000014)
#define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ (0x00F00000)
#define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT (20)
#define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ (0x000F0000)
#define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT (16)
#define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_MASK (0x0000C000)
#define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NO (0x00000000)
#define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL (0x00004000)
#define MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ (0x00002000)
#define MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE (0x00000010)
#define MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC (0x00000001)
/**** Defines for the IOCStatus register ****/
#define MPI3_SYSIF_IOC_STATUS_OFFSET (0x0000001C)
#define MPI3_SYSIF_IOC_STATUS_RESET_HISTORY (0x00000010)
#define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK (0x0000000C)
#define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_SHIFT (0x00000002)
#define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_NONE (0x00000000)
#define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS (0x00000004)
#define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE (0x00000008)
#define MPI3_SYSIF_IOC_STATUS_FAULT (0x00000002)
#define MPI3_SYSIF_IOC_STATUS_READY (0x00000001)
/**** Defines for the AdminQueueNumEntries register ****/
#define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_OFFSET (0x00000024)
#define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REQ_MASK (0x0FFF)
#define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_OFFSET (0x00000026)
#define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_MASK (0x0FFF0000)
#define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_SHIFT (16)
/**** Defines for the AdminRequestQueueAddress register ****/
#define MPI3_SYSIF_ADMIN_REQ_Q_ADDR_LOW_OFFSET (0x00000028)
#define MPI3_SYSIF_ADMIN_REQ_Q_ADDR_HIGH_OFFSET (0x0000002C)
/**** Defines for the AdminReplyQueueAddress register ****/
#define MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_LOW_OFFSET (0x00000030)
#define MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_HIGH_OFFSET (0x00000034)
/**** Defines for the CoalesceControl register ****/
#define MPI3_SYSIF_COALESCE_CONTROL_OFFSET (0x00000040)
#define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_MASK (0xC0000000)
#define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_NO_CHANGE (0x00000000)
#define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_DISABLE (0x40000000)
#define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_ENABLE (0xC0000000)
#define MPI3_SYSIF_COALESCE_CONTROL_VALID (0x20000000)
#define MPI3_SYSIF_COALESCE_CONTROL_MSIX_IDX_MASK (0x01FF0000)
#define MPI3_SYSIF_COALESCE_CONTROL_MSIX_IDX_SHIFT (16)
#define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_MASK (0x0000FF00)
#define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_SHIFT (8)
#define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_MASK (0x000000FF)
#define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_SHIFT (0)
/**** Defines for the AdminRequestQueuePI register ****/
#define MPI3_SYSIF_ADMIN_REQ_Q_PI_OFFSET (0x00001000)
/**** Defines for the AdminReplyQueueCI register ****/
#define MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET (0x00001004)
/**** Defines for the OperationalRequestQueuePI register */
#define MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET (0x00001008)
#define MPI3_SYSIF_OPER_REQ_Q_N_PI_OFFSET(N) (MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET + (((N)-1)*8)) /* N = 1, 2, 3, ..., 255 */
/**** Defines for the OperationalReplyQueueCI register */
#define MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET (0x0000100C)
#define MPI3_SYSIF_OPER_REPLY_Q_N_CI_OFFSET(N) (MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET + (((N)-1)*8)) /* N = 1, 2, 3, ..., 255 */
/**** Defines for the WriteSequence register *****/
#define MPI3_SYSIF_WRITE_SEQUENCE_OFFSET (0x00001C04)
#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_MASK (0x0000000F)
#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH (0x0)
#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST (0xF)
#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND (0x4)
#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD (0xB)
#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH (0x2)
#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH (0x7)
#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH (0xD)
/**** Defines for the HostDiagnostic register *****/
#define MPI3_SYSIF_HOST_DIAG_OFFSET (0x00001C08)
#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_MASK (0x00000700)
#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_NO_RESET (0x00000000)
#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET (0x00000100)
#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_HOST_CONTROL_BOOT_RESET (0x00000200)
#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_COMPLETE_RESET (0x00000300)
#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT (0x00000700)
#define MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS (0x00000080)
#define MPI3_SYSIF_HOST_DIAG_SECURE_BOOT (0x00000040)
#define MPI3_SYSIF_HOST_DIAG_CLEAR_INVALID_FW_IMAGE (0x00000020)
#define MPI3_SYSIF_HOST_DIAG_INVALID_FW_IMAGE (0x00000010)
#define MPI3_SYSIF_HOST_DIAG_HCBENABLE (0x00000008)
#define MPI3_SYSIF_HOST_DIAG_HCBMODE (0x00000004)
#define MPI3_SYSIF_HOST_DIAG_DIAG_RW_ENABLE (0x00000002)
#define MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE (0x00000001)
/**** Defines for the Fault register ****/
#define MPI3_SYSIF_FAULT_OFFSET (0x00001C10)
#define MPI3_SYSIF_FAULT_CODE_MASK (0x0000FFFF)
#define MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET (0x0000F000)
#define MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET (0x0000F001)
#define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS (0x0000F002)
#define MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED (0x0000F003)
#define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_NEEDED (0x0000F004)
#define MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED (0x0000F005)
#define MPI3_SYSIF_FAULT_CODE_TEMP_THRESHOLD_EXCEEDED (0x0000F006)
/**** Defines for FaultCodeAdditionalInfo registers ****/
#define MPI3_SYSIF_FAULT_INFO0_OFFSET (0x00001C14)
#define MPI3_SYSIF_FAULT_INFO1_OFFSET (0x00001C18)
#define MPI3_SYSIF_FAULT_INFO2_OFFSET (0x00001C1C)
/**** Defines for HCBAddress register ****/
#define MPI3_SYSIF_HCB_ADDRESS_LOW_OFFSET (0x00001C30)
#define MPI3_SYSIF_HCB_ADDRESS_HIGH_OFFSET (0x00001C34)
/**** Defines for HCBSize register ****/
#define MPI3_SYSIF_HCB_SIZE_OFFSET (0x00001C38)
#define MPI3_SYSIF_HCB_SIZE_SIZE_MASK (0xFFFFF000)
#define MPI3_SYSIF_HCB_SIZE_SIZE_SHIFT (12)
#define MPI3_SYSIF_HCB_SIZE_HCDW_ENABLE (0x00000001)
/**** Defines for ReplyFreeHostIndex register ****/
#define MPI3_SYSIF_REPLY_FREE_HOST_INDEX_OFFSET (0x00001C40)
/**** Defines for SenseBufferFreeHostIndex register ****/
#define MPI3_SYSIF_SENSE_BUF_FREE_HOST_INDEX_OFFSET (0x00001C44)
/**** Defines for DiagRWData register ****/
#define MPI3_SYSIF_DIAG_RW_DATA_LOW_OFFSET (0x00001C50)
#define MPI3_SYSIF_DIAG_RW_DATA_HIGH_OFFSET (0x00001C54)
/**** Defines for DiagRWAddress ****/
#define MPI3_SYSIF_DIAG_RW_ADDRESS_LOW_OFFSET (0x00001C58)
#define MPI3_SYSIF_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00001C5C)
/**** Defines for DiagRWControl register ****/
#define MPI3_SYSIF_DIAG_RW_CONTROL_OFFSET (0x00001C60)
#define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_MASK (0x00000030)
#define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_1BYTE (0x00000000)
#define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_2BYTES (0x00000010)
#define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_4BYTES (0x00000020)
#define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_8BYTES (0x00000030)
#define MPI3_SYSIF_DIAG_RW_CONTROL_RESET (0x00000004)
#define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_MASK (0x00000002)
#define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_READ (0x00000000)
#define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_WRITE (0x00000002)
#define MPI3_SYSIF_DIAG_RW_CONTROL_START (0x00000001)
/**** Defines for DiagRWStatus register ****/
#define MPI3_SYSIF_DIAG_RW_STATUS_OFFSET (0x00001C62)
#define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_MASK (0x0000000E)
#define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_SUCCESS (0x00000000)
#define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_INV_ADDR (0x00000002)
#define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_ACC_ERR (0x00000004)
#define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_PAR_ERR (0x00000006)
#define MPI3_SYSIF_DIAG_RW_STATUS_BUSY (0x00000001)
/**** Defines for Scratchpad registers ****/
#define MPI3_SYSIF_SCRATCHPAD0_OFFSET (0x00001CF0)
#define MPI3_SYSIF_SCRATCHPAD1_OFFSET (0x00001CF4)
#define MPI3_SYSIF_SCRATCHPAD2_OFFSET (0x00001CF8)
#define MPI3_SYSIF_SCRATCHPAD3_OFFSET (0x00001CFC)
/**** Defines for Device Assigned registers ****/
#define MPI3_SYSIF_DEVICE_ASSIGNED_REGS_OFFSET (0x00002000)
/**** Default Defines for Diag Save Timeout ****/
#define MPI3_SYSIF_DIAG_SAVE_TIMEOUT (60) /* seconds */
/*****************************************************************************
* Reply Descriptors *
****************************************************************************/
/*****************************************************************************
* Default Reply Descriptor *
****************************************************************************/
typedef struct _MPI3_DEFAULT_REPLY_DESCRIPTOR
{
U32 DescriptorTypeDependent1[2]; /* 0x00 */
U16 RequestQueueCI; /* 0x08 */
U16 RequestQueueID; /* 0x0A */
U16 DescriptorTypeDependent2; /* 0x0C */
U16 ReplyFlags; /* 0x0E */
} MPI3_DEFAULT_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_DEFAULT_REPLY_DESCRIPTOR,
Mpi3DefaultReplyDescriptor_t, MPI3_POINTER pMpi3DefaultReplyDescriptor_t;
/**** Defines for the ReplyFlags field ****/
#define MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK (0x0001)
#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK (0xF000)
#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY (0x0000)
#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS (0x1000)
#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_TARGET_COMMAND_BUFFER (0x2000)
#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS (0x3000)
/**** Defines for the RequestQueueID field ****/
#define MPI3_REPLY_DESCRIPT_REQUEST_QUEUE_ID_INVALID (0xFFFF)
/*****************************************************************************
* Address Reply Descriptor *
****************************************************************************/
typedef struct _MPI3_ADDRESS_REPLY_DESCRIPTOR
{
U64 ReplyFrameAddress; /* 0x00 */
U16 RequestQueueCI; /* 0x08 */
U16 RequestQueueID; /* 0x0A */
U16 Reserved0C; /* 0x0C */
U16 ReplyFlags; /* 0x0E */
} MPI3_ADDRESS_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_ADDRESS_REPLY_DESCRIPTOR,
Mpi3AddressReplyDescriptor_t, MPI3_POINTER pMpi3AddressReplyDescriptor_t;
/*****************************************************************************
* Success Reply Descriptor *
****************************************************************************/
typedef struct _MPI3_SUCCESS_REPLY_DESCRIPTOR
{
U32 Reserved00[2]; /* 0x00 */
U16 RequestQueueCI; /* 0x08 */
U16 RequestQueueID; /* 0x0A */
U16 HostTag; /* 0x0C */
U16 ReplyFlags; /* 0x0E */
} MPI3_SUCCESS_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_SUCCESS_REPLY_DESCRIPTOR,
Mpi3SuccessReplyDescriptor_t, MPI3_POINTER pMpi3SuccessReplyDescriptor_t;
/*****************************************************************************
* Target Command Buffer Reply Descriptor *
****************************************************************************/
typedef struct _MPI3_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
{
U32 Reserved00; /* 0x00 */
U16 InitiatorDevHandle; /* 0x04 */
U8 PhyNum; /* 0x06 */
U8 Reserved07; /* 0x07 */
U16 RequestQueueCI; /* 0x08 */
U16 RequestQueueID; /* 0x0A */
U16 IOIndex; /* 0x0C */
U16 ReplyFlags; /* 0x0E */
} MPI3_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
Mpi3TargetCommandBufferReplyDescriptor_t, MPI3_POINTER pMpi3TargetCommandBufferReplyDescriptor_t;
/**** See Default Reply Descriptor Defines above for definitions in the ReplyFlags field ****/
/*****************************************************************************
* Status Reply Descriptor *
****************************************************************************/
typedef struct _MPI3_STATUS_REPLY_DESCRIPTOR
{
U16 IOCStatus; /* 0x00 */
U16 Reserved02; /* 0x02 */
U32 IOCLogInfo; /* 0x04 */
U16 RequestQueueCI; /* 0x08 */
U16 RequestQueueID; /* 0x0A */
U16 HostTag; /* 0x0C */
U16 ReplyFlags; /* 0x0E */
} MPI3_STATUS_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_STATUS_REPLY_DESCRIPTOR,
Mpi3StatusReplyDescriptor_t, MPI3_POINTER pMpi3StatusReplyDescriptor_t;
/**** Defines for the IOCStatus field ****/
#define MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL (0x8000)
#define MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK (0x7FFF)
/**** Defines for the IOCLogInfo field ****/
#define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_MASK (0xF0000000)
#define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_NO_INFO (0x00000000)
#define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_SAS (0x30000000)
#define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_DATA_MASK (0x0FFFFFFF)
/*****************************************************************************
* Union of Reply Descriptors *
****************************************************************************/
typedef union _MPI3_REPLY_DESCRIPTORS_UNION
{
MPI3_DEFAULT_REPLY_DESCRIPTOR Default;
MPI3_ADDRESS_REPLY_DESCRIPTOR AddressReply;
MPI3_SUCCESS_REPLY_DESCRIPTOR Success;
MPI3_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
MPI3_STATUS_REPLY_DESCRIPTOR Status;
U32 Words[4];
} MPI3_REPLY_DESCRIPTORS_UNION, MPI3_POINTER PTR_MPI3_REPLY_DESCRIPTORS_UNION,
Mpi3ReplyDescriptorsUnion_t, MPI3_POINTER pMpi3ReplyDescriptorsUnion_t;
/*****************************************************************************
* Scatter Gather Elements *
****************************************************************************/
/*****************************************************************************
* Common structure for Simple, Chain, and Last Chain *
* scatter gather elements *
****************************************************************************/
typedef struct _MPI3_SGE_COMMON
{
U64 Address; /* 0x00 */
U32 Length; /* 0x08 */
U8 Reserved0C[3]; /* 0x0C */
U8 Flags; /* 0x0F */
} MPI3_SGE_SIMPLE, MPI3_POINTER PTR_MPI3_SGE_SIMPLE,
Mpi3SGESimple_t, MPI3_POINTER pMpi3SGESimple_t,
MPI3_SGE_CHAIN, MPI3_POINTER PTR_MPI3_SGE_CHAIN,
Mpi3SGEChain_t, MPI3_POINTER pMpi3SGEChain_t,
MPI3_SGE_LAST_CHAIN, MPI3_POINTER PTR_MPI3_SGE_LAST_CHAIN,
Mpi3SGELastChain_t, MPI3_POINTER pMpi3SGELastChain_t;
/*****************************************************************************
* Bit Bucket scatter gather element *
****************************************************************************/
typedef struct _MPI3_SGE_BIT_BUCKET
{
U64 Reserved00; /* 0x00 */
U32 Length; /* 0x08 */
U8 Reserved0C[3]; /* 0x0C */
U8 Flags; /* 0x0F */
} MPI3_SGE_BIT_BUCKET, MPI3_POINTER PTR_MPI3_SGE_BIT_BUCKET,
Mpi3SGEBitBucket_t, MPI3_POINTER pMpi3SGEBitBucket_t;
/*****************************************************************************
* Extended EEDP scatter gather element *
****************************************************************************/
typedef struct _MPI3_SGE_EXTENDED_EEDP
{
U8 UserDataSize; /* 0x00 */
U8 Reserved01; /* 0x01 */
U16 EEDPFlags; /* 0x02 */
U32 SecondaryReferenceTag; /* 0x04 */
U16 SecondaryApplicationTag; /* 0x08 */
U16 ApplicationTagTranslationMask; /* 0x0A */
U16 Reserved0C; /* 0x0C */
U8 ExtendedOperation; /* 0x0E */
U8 Flags; /* 0x0F */
} MPI3_SGE_EXTENDED_EEDP, MPI3_POINTER PTR_MPI3_SGE_EXTENDED_EEDP,
Mpi3SGEExtendedEEDP_t, MPI3_POINTER pMpi3SGEExtendedEEDP_t;
/*****************************************************************************
* Union of scatter gather elements *
****************************************************************************/
typedef union _MPI3_SGE_UNION
{
MPI3_SGE_SIMPLE Simple;
MPI3_SGE_CHAIN Chain;
MPI3_SGE_LAST_CHAIN LastChain;
MPI3_SGE_BIT_BUCKET BitBucket;
MPI3_SGE_EXTENDED_EEDP Eedp;
U32 Words[4];
} MPI3_SGE_UNION, MPI3_POINTER PTR_MPI3_SGE_UNION,
Mpi3SGEUnion_t, MPI3_POINTER pMpi3SGEUnion_t;
/**** Definitions for the Flags field ****/
#define MPI3_SGE_FLAGS_ELEMENT_TYPE_MASK (0xF0)
#define MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE (0x00)
#define MPI3_SGE_FLAGS_ELEMENT_TYPE_BIT_BUCKET (0x10)
#define MPI3_SGE_FLAGS_ELEMENT_TYPE_CHAIN (0x20)
#define MPI3_SGE_FLAGS_ELEMENT_TYPE_LAST_CHAIN (0x30)
#define MPI3_SGE_FLAGS_ELEMENT_TYPE_EXTENDED (0xF0)
#define MPI3_SGE_FLAGS_END_OF_LIST (0x08)
#define MPI3_SGE_FLAGS_END_OF_BUFFER (0x04)
#define MPI3_SGE_FLAGS_DLAS_MASK (0x03)
#define MPI3_SGE_FLAGS_DLAS_SYSTEM (0x00)
#define MPI3_SGE_FLAGS_DLAS_IOC_UDP (0x01)
#define MPI3_SGE_FLAGS_DLAS_IOC_CTL (0x02)
/**** Definitions for the ExtendedOperation field of Extended element ****/
#define MPI3_SGE_EXT_OPER_EEDP (0x00)
/**** Definitions for the EEDPFlags field of Extended EEDP element ****/
#define MPI3_EEDPFLAGS_INCR_PRI_REF_TAG (0x8000)
#define MPI3_EEDPFLAGS_INCR_SEC_REF_TAG (0x4000)
#define MPI3_EEDPFLAGS_INCR_PRI_APP_TAG (0x2000)
#define MPI3_EEDPFLAGS_INCR_SEC_APP_TAG (0x1000)
#define MPI3_EEDPFLAGS_ESC_PASSTHROUGH (0x0800)
#define MPI3_EEDPFLAGS_CHK_REF_TAG (0x0400)
#define MPI3_EEDPFLAGS_CHK_APP_TAG (0x0200)
#define MPI3_EEDPFLAGS_CHK_GUARD (0x0100)
#define MPI3_EEDPFLAGS_ESC_MODE_MASK (0x00C0)
#define MPI3_EEDPFLAGS_ESC_MODE_DO_NOT_DISABLE (0x0040)
#define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_DISABLE (0x0080)
#define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_REFTAG_DISABLE (0x00C0)
#define MPI3_EEDPFLAGS_HOST_GUARD_MASK (0x0030)
#define MPI3_EEDPFLAGS_HOST_GUARD_T10_CRC (0x0000)
#define MPI3_EEDPFLAGS_HOST_GUARD_IP_CHKSUM (0x0010)
#define MPI3_EEDPFLAGS_HOST_GUARD_OEM_SPECIFIC (0x0020)
#define MPI3_EEDPFLAGS_PT_REF_TAG (0x0008)
#define MPI3_EEDPFLAGS_EEDP_OP_MASK (0x0007)
#define MPI3_EEDPFLAGS_EEDP_OP_CHECK (0x0001)
#define MPI3_EEDPFLAGS_EEDP_OP_STRIP (0x0002)
#define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REMOVE (0x0003)
#define MPI3_EEDPFLAGS_EEDP_OP_INSERT (0x0004)
#define MPI3_EEDPFLAGS_EEDP_OP_REPLACE (0x0006)
#define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REGEN (0x0007)
/**** Definitions for the UserDataSize field of Extended EEDP element ****/
#define MPI3_EEDP_UDS_512 (0x01)
#define MPI3_EEDP_UDS_520 (0x02)
#define MPI3_EEDP_UDS_4080 (0x03)
#define MPI3_EEDP_UDS_4088 (0x04)
#define MPI3_EEDP_UDS_4096 (0x05)
#define MPI3_EEDP_UDS_4104 (0x06)
#define MPI3_EEDP_UDS_4160 (0x07)
/*****************************************************************************
* Standard Message Structures *
****************************************************************************/
/*****************************************************************************
* Request Message Header for all request messages *
****************************************************************************/
typedef struct _MPI3_REQUEST_HEADER
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 ChangeCount; /* 0x08 */
U16 FunctionDependent; /* 0x0A */
} MPI3_REQUEST_HEADER, MPI3_POINTER PTR_MPI3_REQUEST_HEADER,
Mpi3RequestHeader_t, MPI3_POINTER pMpi3RequestHeader_t;
/*****************************************************************************
* Default Reply *
****************************************************************************/
typedef struct _MPI3_DEFAULT_REPLY
{
U16 HostTag; /* 0x00 */
U8 IOCUseOnly02; /* 0x02 */
U8 Function; /* 0x03 */
U16 IOCUseOnly04; /* 0x04 */
U8 IOCUseOnly06; /* 0x06 */
U8 MsgFlags; /* 0x07 */
U16 IOCUseOnly08; /* 0x08 */
U16 IOCStatus; /* 0x0A */
U32 IOCLogInfo; /* 0x0C */
} MPI3_DEFAULT_REPLY, MPI3_POINTER PTR_MPI3_DEFAULT_REPLY,
Mpi3DefaultReply_t, MPI3_POINTER pMpi3DefaultReply_t;
/**** Defines for the HostTag field ****/
#define MPI3_HOST_TAG_INVALID (0xFFFF)
/**** Defines for message Function ****/
/* I/O Controller functions */
#define MPI3_FUNCTION_IOC_FACTS (0x01) /* IOC Facts */
#define MPI3_FUNCTION_IOC_INIT (0x02) /* IOC Init */
#define MPI3_FUNCTION_PORT_ENABLE (0x03) /* Port Enable */
#define MPI3_FUNCTION_EVENT_NOTIFICATION (0x04) /* Event Notification */
#define MPI3_FUNCTION_EVENT_ACK (0x05) /* Event Acknowledge */
#define MPI3_FUNCTION_CI_DOWNLOAD (0x06) /* Component Image Download */
#define MPI3_FUNCTION_CI_UPLOAD (0x07) /* Component Image Upload */
#define MPI3_FUNCTION_IO_UNIT_CONTROL (0x08) /* IO Unit Control */
#define MPI3_FUNCTION_PERSISTENT_EVENT_LOG (0x09) /* Persistent Event Log */
#define MPI3_FUNCTION_MGMT_PASSTHROUGH (0x0A) /* Management Passthrough */
#define MPI3_FUNCTION_CONFIG (0x10) /* Configuration */
/* SCSI Initiator I/O functions */
#define MPI3_FUNCTION_SCSI_IO (0x20) /* SCSI IO */
#define MPI3_FUNCTION_SCSI_TASK_MGMT (0x21) /* SCSI Task Management */
#define MPI3_FUNCTION_SMP_PASSTHROUGH (0x22) /* SMP Passthrough */
#define MPI3_FUNCTION_NVME_ENCAPSULATED (0x24) /* NVMe Encapsulated */
/* SCSI Target I/O functions */
#define MPI3_FUNCTION_TARGET_ASSIST (0x30) /* Target Assist */
#define MPI3_FUNCTION_TARGET_STATUS_SEND (0x31) /* Target Status Send */
#define MPI3_FUNCTION_TARGET_MODE_ABORT (0x32) /* Target Mode Abort */
#define MPI3_FUNCTION_TARGET_CMD_BUF_POST_BASE (0x33) /* Target Command Buffer Post Base */
#define MPI3_FUNCTION_TARGET_CMD_BUF_POST_LIST (0x34) /* Target Command Buffer Post List */
/* Queue Management functions */
#define MPI3_FUNCTION_CREATE_REQUEST_QUEUE (0x70) /* Create an operational request queue */
#define MPI3_FUNCTION_DELETE_REQUEST_QUEUE (0x71) /* Delete an operational request queue */
#define MPI3_FUNCTION_CREATE_REPLY_QUEUE (0x72) /* Create an operational reply queue */
#define MPI3_FUNCTION_DELETE_REPLY_QUEUE (0x73) /* Delete an operational reply queue */
/* Diagnostic Tools */
#define MPI3_FUNCTION_TOOLBOX (0x80) /* Toolbox */
#define MPI3_FUNCTION_DIAG_BUFFER_POST (0x81) /* Post a Diagnostic Buffer to the I/O Unit */
#define MPI3_FUNCTION_DIAG_BUFFER_MANAGE (0x82) /* Manage a Diagnostic Buffer */
#define MPI3_FUNCTION_DIAG_BUFFER_UPLOAD (0x83) /* Upload a Diagnostic Buffer */
/* Miscellaneous functions */
#define MPI3_FUNCTION_MIN_IOC_USE_ONLY (0xC0) /* Beginning of IOC Use Only range of function codes */
#define MPI3_FUNCTION_MAX_IOC_USE_ONLY (0xEF) /* End of IOC Use Only range of function codes */
#define MPI3_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* Beginning of the product-specific range of function codes */
#define MPI3_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* End of the product-specific range of function codes */
/**** Defines for IOCStatus ****/
#define MPI3_IOCSTATUS_LOG_INFO_AVAIL_MASK (0x8000)
#define MPI3_IOCSTATUS_LOG_INFO_AVAILABLE (0x8000)
#define MPI3_IOCSTATUS_STATUS_MASK (0x7FFF)
/* Common IOCStatus values for all replies */
#define MPI3_IOCSTATUS_SUCCESS (0x0000)
#define MPI3_IOCSTATUS_INVALID_FUNCTION (0x0001)
#define MPI3_IOCSTATUS_BUSY (0x0002)
#define MPI3_IOCSTATUS_INVALID_SGL (0x0003)
#define MPI3_IOCSTATUS_INTERNAL_ERROR (0x0004)
#define MPI3_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
#define MPI3_IOCSTATUS_INVALID_FIELD (0x0007)
#define MPI3_IOCSTATUS_INVALID_STATE (0x0008)
#define MPI3_IOCSTATUS_INSUFFICIENT_POWER (0x000A)
#define MPI3_IOCSTATUS_INVALID_CHANGE_COUNT (0x000B)
#define MPI3_IOCSTATUS_ALLOWED_CMD_BLOCK (0x000C)
#define MPI3_IOCSTATUS_SUPERVISOR_ONLY (0x000D)
#define MPI3_IOCSTATUS_FAILURE (0x001F)
/* Config IOCStatus values */
#define MPI3_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
#define MPI3_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
#define MPI3_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
#define MPI3_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
#define MPI3_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
#define MPI3_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
/* SCSI IO IOCStatus values */
#define MPI3_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
#define MPI3_IOCSTATUS_SCSI_TM_NOT_SUPPORTED (0x0041)
#define MPI3_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
#define MPI3_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
#define MPI3_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
#define MPI3_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
#define MPI3_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
#define MPI3_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
#define MPI3_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
#define MPI3_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
#define MPI3_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
#define MPI3_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
#define MPI3_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
/* SCSI Initiator and SCSI Target end-to-end data protection values */
#define MPI3_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
#define MPI3_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
#define MPI3_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
/* SCSI Target IOCStatus values */
#define MPI3_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
#define MPI3_IOCSTATUS_TARGET_ABORTED (0x0063)
#define MPI3_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
#define MPI3_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
#define MPI3_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
#define MPI3_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
#define MPI3_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
#define MPI3_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
#define MPI3_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
#define MPI3_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
/* Serial Attached SCSI IOCStatus values */
#define MPI3_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
#define MPI3_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
/* Diagnostic Buffer Post/Release IOCStatus values */
#define MPI3_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
/* Component Image Upload/Download */
#define MPI3_IOCSTATUS_CI_UNSUPPORTED (0x00B0)
#define MPI3_IOCSTATUS_CI_UPDATE_SEQUENCE (0x00B1)
#define MPI3_IOCSTATUS_CI_VALIDATION_FAILED (0x00B2)
#define MPI3_IOCSTATUS_CI_KEY_UPDATE_PENDING (0x00B3)
#define MPI3_IOCSTATUS_CI_KEY_UPDATE_NOT_POSSIBLE (0x00B4)
/* Security values */
#define MPI3_IOCSTATUS_SECURITY_KEY_REQUIRED (0x00C0)
#define MPI3_IOCSTATUS_SECURITY_VIOLATION (0x00C1)
/* Request and Reply Queues related IOCStatus values */
#define MPI3_IOCSTATUS_INVALID_QUEUE_ID (0x0F00)
#define MPI3_IOCSTATUS_INVALID_QUEUE_SIZE (0x0F01)
#define MPI3_IOCSTATUS_INVALID_MSIX_VECTOR (0x0F02)
#define MPI3_IOCSTATUS_INVALID_REPLY_QUEUE_ID (0x0F03)
#define MPI3_IOCSTATUS_INVALID_QUEUE_DELETION (0x0F04)
/**** Defines for IOCLogInfo ****/
#define MPI3_IOCLOGINFO_TYPE_MASK (0xF0000000)
#define MPI3_IOCLOGINFO_TYPE_SHIFT (28)
#define MPI3_IOCLOGINFO_TYPE_NONE (0x0)
#define MPI3_IOCLOGINFO_TYPE_SAS (0x3)
#define MPI3_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
#endif /* MPI30_TRANSPORT_H */

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sys/dev/mpi3mr/mpi/mpi30_type.h Normal file
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/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2016-2023, Broadcom Inc. All rights reserved.
* Support: <fbsd-storage-driver.pdl@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
* 3. Neither the name of the Broadcom Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are
* those of the authors and should not be interpreted as representing
* official policies,either expressed or implied, of the FreeBSD Project.
*
* Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131
*
* Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD
*
*/
#ifndef MPI30_TYPE_H
#define MPI30_TYPE_H 1
/*****************************************************************************
* Define MPI3_POINTER if it has not already been defined. By default *
* MPI3_POINTER is defined to be a near pointer. MPI3_POINTER can be defined *
* as a far pointer by defining MPI3_POINTER as "far *" before this header *
* file is included. *
****************************************************************************/
#ifndef MPI3_POINTER
#define MPI3_POINTER *
#endif /* MPI3_POINTER */
/* The basic types may have already been included by mpi_type.h or mpi2_type.h */
#if !defined(MPI_TYPE_H) && !defined(MPI2_TYPE_H)
/*****************************************************************************
* Basic Types *
****************************************************************************/
typedef int8_t S8;
typedef uint8_t U8;
typedef int16_t S16;
typedef uint16_t U16;
typedef int32_t S32;
typedef uint32_t U32;
typedef int64_t S64;
typedef uint64_t U64;
/*****************************************************************************
* Structure Types *
****************************************************************************/
typedef struct _S64struct
{
U32 Low;
S32 High;
} S64struct;
typedef struct _U64struct
{
U32 Low;
U32 High;
} U64struct;
/*****************************************************************************
* Pointer Types *
****************************************************************************/
typedef S8 *PS8;
typedef U8 *PU8;
typedef S16 *PS16;
typedef U16 *PU16;
typedef S32 *PS32;
typedef U32 *PU32;
typedef S64 *PS64;
typedef U64 *PU64;
typedef S64struct *PS64struct;
typedef U64struct *PU64struct;
#endif /* MPI_TYPE_H && MPI2_TYPE_H */
#endif /* MPI30_TYPE_H */

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/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2020-2023, Broadcom Inc. All rights reserved.
* Support: <fbsd-storage-driver.pdl@broadcom.com>
*
* Authors: Sumit Saxena <sumit.saxena@broadcom.com>
* Chandrakanth Patil <chandrakanth.patil@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
* 3. Neither the name of the Broadcom Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are
* those of the authors and should not be interpreted as representing
* official policies,either expressed or implied, of the FreeBSD Project.
*
* Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131
*
* Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD
*/
#ifndef _MPI3MRVAR_H
#define _MPI3MRVAR_H
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/types.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <sys/conf.h>
#include <sys/malloc.h>
#include <sys/sysctl.h>
#include <sys/uio.h>
#include <sys/selinfo.h>
#include <sys/poll.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/endian.h>
#include <sys/sysent.h>
#include <sys/taskqueue.h>
#include <sys/smp.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/rman.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pci_private.h>
#include <cam/cam.h>
#include <cam/cam_ccb.h>
#include <cam/cam_debug.h>
#include <cam/cam_sim.h>
#include <cam/cam_xpt_sim.h>
#include <cam/cam_xpt_periph.h>
#include <cam/cam_periph.h>
#include <cam/scsi/scsi_all.h>
#include <cam/scsi/scsi_message.h>
#include <cam/scsi/smp_all.h>
#include <sys/queue.h>
#include <sys/kthread.h>
#include "mpi/mpi30_api.h"
#define MPI3MR_DRIVER_VERSION "8.6.0.2.0"
#define MPI3MR_DRIVER_RELDATE "17th May 2023"
#define MPI3MR_DRIVER_NAME "mpi3mr"
#define MPI3MR_NAME_LENGTH 32
#define IOCNAME "%s: "
#define SAS4116_CHIP_REV_A0 0
#define SAS4116_CHIP_REV_B0 1
#define MPI3MR_SG_DEPTH (MPI3MR_4K_PGSZ/sizeof(Mpi3SGESimple_t))
#define MPI3MR_MAX_SECTORS 2048
#define MPI3MR_MAX_CMDS_LUN 7
#define MPI3MR_MAX_CDB_LENGTH 16
#define MPI3MR_MAX_LUN 16895
#define MPI3MR_SATA_QDEPTH 32
#define MPI3MR_SAS_QDEPTH 64
#define MPI3MR_RAID_QDEPTH 128
#define MPI3MR_NVME_QDEPTH 128
#define MPI3MR_4K_PGSZ 4096
#define MPI3MR_AREQQ_SIZE (2 * MPI3MR_4K_PGSZ)
#define MPI3MR_AREPQ_SIZE (4 * MPI3MR_4K_PGSZ)
#define MPI3MR_AREQ_FRAME_SZ 128
#define MPI3MR_AREP_FRAME_SZ 16
#define MPI3MR_OPREQQ_SIZE (8 * MPI3MR_4K_PGSZ)
#define MPI3MR_OPREPQ_SIZE (4 * MPI3MR_4K_PGSZ)
/* Operational queue management definitions */
#define MPI3MR_OP_REQ_Q_QD 512
#define MPI3MR_OP_REP_Q_QD 1024
#define MPI3MR_OP_REP_Q_QD_A0 4096
#define MPI3MR_CHAINSGE_SIZE MPI3MR_4K_PGSZ
#define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \
(MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \
MPI3_SGE_FLAGS_END_OF_LIST)
#define MPI3MR_HOSTTAG_INVALID 0xFFFF
#define MPI3MR_HOSTTAG_INITCMDS 1
#define MPI3MR_HOSTTAG_IOCTLCMDS 2
#define MPI3MR_HOSTTAG_PELABORT 3
#define MPI3MR_HOSTTAG_PELWAIT 4
#define MPI3MR_HOSTTAG_TMS 5
#define MAX_MGMT_ADAPTERS 8
#define MPI3MR_WAIT_BEFORE_CTRL_RESET 5
struct mpi3mr_mgmt_info {
uint16_t count;
struct mpi3mr_softc *sc_ptr[MAX_MGMT_ADAPTERS];
int max_index;
};
extern char fmt_os_ver[16];
#define MPI3MR_OS_VERSION(raw_os_ver, fmt_os_ver) sprintf(raw_os_ver, "%d", __FreeBSD_version); \
sprintf(fmt_os_ver, "%c%c.%c%c.%c%c%c",\
raw_os_ver[0], raw_os_ver[1], raw_os_ver[2],\
raw_os_ver[3], raw_os_ver[4], raw_os_ver[5],\
raw_os_ver[6]);
#define MPI3MR_NUM_DEVRMCMD 1
#define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_TMS + 1)
#define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \
MPI3MR_NUM_DEVRMCMD - 1)
#define MPI3MR_INTERNALCMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX
#define MPI3MR_NUM_EVTACKCMD 4
#define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1)
#define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \
MPI3MR_NUM_EVTACKCMD - 1)
/* command/controller interaction timeout definitions in seconds */
#define MPI3MR_INTADMCMD_TIMEOUT 60
#define MPI3MR_PORTENABLE_TIMEOUT 300
#define MPI3MR_ABORTTM_TIMEOUT 60
#define MPI3MR_RESETTM_TIMEOUT 60
#define MPI3MR_TSUPDATE_INTERVAL 900
#define MPI3MR_DEFAULT_SHUTDOWN_TIME 120
#define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180
#define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5
#define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180
#define MPI3MR_RESET_ACK_TIMEOUT 30
#define MPI3MR_MUR_TIMEOUT 120
#define MPI3MR_CMD_NOTUSED 0x8000
#define MPI3MR_CMD_COMPLETE 0x0001
#define MPI3MR_CMD_PENDING 0x0002
#define MPI3MR_CMD_REPLYVALID 0x0004
#define MPI3MR_CMD_RESET 0x0008
#define MPI3MR_NUM_EVTREPLIES 64
#define MPI3MR_SENSEBUF_SZ 256
#define MPI3MR_SENSEBUF_FACTOR 3
#define MPI3MR_CHAINBUF_FACTOR 3
#define MPT3SAS_HOSTPGSZ_4KEXP 12
#define MPI3MR_INVALID_DEV_HANDLE 0xFFFF
/* Controller Reset related definitions */
#define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5
#define MPI3MR_MAX_SHUTDOWN_RETRY_COUNT 2
/* ResponseCode values */
#define MPI3MR_RI_MASK_RESPCODE (0x000000FF)
#define MPI3MR_RSP_TM_COMPLETE 0x00
#define MPI3MR_RSP_INVALID_FRAME 0x02
#define MPI3MR_RSP_TM_NOT_SUPPORTED 0x04
#define MPI3MR_RSP_TM_FAILED 0x05
#define MPI3MR_RSP_TM_SUCCEEDED 0x08
#define MPI3MR_RSP_TM_INVALID_LUN 0x09
#define MPI3MR_RSP_TM_OVERLAPPED_TAG 0x0A
#define MPI3MR_RSP_IO_QUEUED_ON_IOC \
MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC
/* Definitions for the controller security status*/
#define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C
#define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02
#define MPI3MR_INVALID_DEVICE 0x00
#define MPI3MR_CONFIG_SECURE_DEVICE 0x04
#define MPI3MR_HARD_SECURE_DEVICE 0x08
#define MPI3MR_TAMPERED_DEVICE 0x0C
#define MPI3MR_DEFAULT_MDTS (128 * 1024)
#define MPI3MR_DEFAULT_PGSZEXP (12)
#define MPI3MR_MAX_IOCTL_TRANSFER_SIZE (1024 * 1024)
#define MPI3MR_DEVRMHS_RETRYCOUNT 3
#define MPI3MR_PELCMDS_RETRYCOUNT 3
#define MPI3MR_PERIODIC_DELAY 1 /* 1 second heartbeat/watchdog check */
struct completion {
unsigned int done;
struct mtx lock;
};
typedef union {
volatile unsigned int val;
unsigned int val_rdonly;
} mpi3mr_atomic_t;
#define mpi3mr_atomic_read(v) atomic_load_acq_int(&(v)->val)
#define mpi3mr_atomic_set(v,i) atomic_store_rel_int(&(v)->val, i)
#define mpi3mr_atomic_dec(v) atomic_subtract_int(&(v)->val, 1)
#define mpi3mr_atomic_inc(v) atomic_add_int(&(v)->val, 1)
#define mpi3mr_atomic_add(v, u) atomic_add_int(&(v)->val, u)
#define mpi3mr_atomic_sub(v, u) atomic_subtract_int(&(v)->val, u)
/* IOCTL data transfer sge*/
#define MPI3MR_NUM_IOCTL_SGE 256
#define MPI3MR_IOCTL_SGE_SIZE (8 * 1024)
struct dma_memory_desc {
U32 size;
void *addr;
bus_dma_tag_t tag;
bus_dmamap_t dmamap;
bus_addr_t dma_addr;
};
enum mpi3mr_iocstate {
MRIOC_STATE_READY = 1,
MRIOC_STATE_RESET,
MRIOC_STATE_FAULT,
MRIOC_STATE_BECOMING_READY,
MRIOC_STATE_RESET_REQUESTED,
MRIOC_STATE_UNRECOVERABLE,
MRIOC_STATE_COUNT,
};
/* Init type definitions */
enum mpi3mr_init_type {
MPI3MR_INIT_TYPE_INIT = 0,
MPI3MR_INIT_TYPE_RESET,
MPI3MR_INIT_TYPE_RESUME,
};
/* Reset reason code definitions*/
enum mpi3mr_reset_reason {
MPI3MR_RESET_FROM_BRINGUP = 1,
MPI3MR_RESET_FROM_FAULT_WATCH = 2,
MPI3MR_RESET_FROM_IOCTL = 3,
MPI3MR_RESET_FROM_EH_HOS = 4,
MPI3MR_RESET_FROM_TM_TIMEOUT = 5,
MPI3MR_RESET_FROM_IOCTL_TIMEOUT = 6,
MPI3MR_RESET_FROM_MUR_FAILURE = 7,
MPI3MR_RESET_FROM_CTLR_CLEANUP = 8,
MPI3MR_RESET_FROM_CIACTIV_FAULT = 9,
MPI3MR_RESET_FROM_PE_TIMEOUT = 10,
MPI3MR_RESET_FROM_TSU_TIMEOUT = 11,
MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12,
MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13,
MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14,
MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15,
MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16,
MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17,
MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18,
MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19,
MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20,
MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21,
MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22,
MPI3MR_RESET_FROM_SYSFS = 23,
MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24,
MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT = 25,
MPI3MR_RESET_FROM_SCSIIO_TIMEOUT = 26,
MPI3MR_RESET_FROM_FIRMWARE = 27,
MPI3MR_DEFAULT_RESET_REASON = 28,
MPI3MR_RESET_REASON_COUNT,
};
struct mpi3mr_compimg_ver
{
U16 build_num;
U16 cust_id;
U8 ph_minor;
U8 ph_major;
U8 gen_minor;
U8 gen_major;
};
struct mpi3mr_ioc_facts
{
U32 ioc_capabilities;
struct mpi3mr_compimg_ver fw_ver;
U32 mpi_version;
U16 max_reqs;
U16 product_id;
U16 op_req_sz;
U16 reply_sz;
U16 exceptions;
U16 max_perids;
U16 max_pds;
U16 max_sasexpanders;
U16 max_sasinitiators;
U16 max_enclosures;
U16 max_pcieswitches;
U16 max_nvme;
U16 max_vds;
U16 max_hpds;
U16 max_advhpds;
U16 max_raidpds;
U16 min_devhandle;
U16 max_devhandle;
U16 max_op_req_q;
U16 max_op_reply_q;
U16 shutdown_timeout;
U8 ioc_num;
U8 who_init;
U16 max_msix_vectors;
U8 personality;
U8 dma_mask;
U8 protocol_flags;
U8 sge_mod_mask;
U8 sge_mod_value;
U8 sge_mod_shift;
U8 max_dev_per_tg;
U16 max_io_throttle_group;
U16 io_throttle_data_length;
U16 io_throttle_low;
U16 io_throttle_high;
};
struct mpi3mr_op_req_queue {
U16 ci;
U16 pi;
U16 num_reqs;
U8 qid;
U8 reply_qid;
U32 qsz;
void *q_base;
bus_dma_tag_t q_base_tag;
bus_dmamap_t q_base_dmamap;
bus_addr_t q_base_phys;
struct mtx q_lock;
};
struct mpi3mr_op_reply_queue {
U16 ci;
U8 ephase;
U8 qid;
U16 num_replies;
U32 qsz;
bus_dma_tag_t q_base_tag;
bus_dmamap_t q_base_dmamap;
void *q_base;
bus_addr_t q_base_phys;
mpi3mr_atomic_t pend_ios;
bool in_use;
struct mtx q_lock;
};
struct irq_info {
MPI3_REPLY_DESCRIPTORS_UNION *post_queue;
bus_dma_tag_t buffer_dmat;
struct resource *irq;
void *intrhand;
int irq_rid;
};
struct mpi3mr_irq_context {
struct mpi3mr_softc *sc;
U16 msix_index;
struct mpi3mr_op_reply_queue *op_reply_q;
char name[MPI3MR_NAME_LENGTH];
struct irq_info irq_info;
};
MALLOC_DECLARE(M_MPI3MR);
SYSCTL_DECL(_hw_mpi3mr);
typedef struct mpi3mr_drvr_cmd DRVR_CMD;
typedef void (*DRVR_CMD_CALLBACK)(struct mpi3mr_softc *mrioc, DRVR_CMD *drvrcmd);
struct mpi3mr_drvr_cmd {
struct mtx lock;
struct completion completion;
void *reply;
U8 *sensebuf;
U8 iou_rc;
U16 state;
U16 dev_handle;
U16 ioc_status;
U32 ioc_loginfo;
U8 is_waiting;
U8 is_senseprst;
U8 retry_count;
U16 host_tag;
DRVR_CMD_CALLBACK callback;
};
struct mpi3mr_cmd;
typedef void mpi3mr_evt_callback_t(struct mpi3mr_softc *, uintptr_t,
Mpi3EventNotificationReply_t *reply);
typedef void mpi3mr_cmd_callback_t(struct mpi3mr_softc *,
struct mpi3mr_cmd *cmd);
#define MPI3MR_IOVEC_COUNT 2
enum mpi3mr_data_xfer_direction {
MPI3MR_READ = 1,
MPI3MR_WRITE,
};
enum mpi3mr_cmd_state {
MPI3MR_CMD_STATE_FREE = 1,
MPI3MR_CMD_STATE_BUSY,
MPI3MR_CMD_STATE_IN_QUEUE,
MPI3MR_CMD_STATE_IN_TM,
};
enum mpi3mr_target_state {
MPI3MR_DEV_CREATED = 1,
MPI3MR_DEV_REMOVE_HS_STARTED = 2,
MPI3MR_DEV_DELETED = 3,
};
struct mpi3mr_cmd {
TAILQ_ENTRY(mpi3mr_cmd) next;
struct mpi3mr_softc *sc;
union ccb *ccb;
void *data;
u_int length;
u_int out_len;
struct uio uio;
struct iovec iovec[MPI3MR_IOVEC_COUNT];
u_int max_segs;
struct mpi3mr_target *targ;
u_int lun;
u_int data_dir;
u_int state;
bus_dmamap_t dmamap;
struct scsi_sense_data *sense;
struct callout callout;
bool callout_owner;
mpi3mr_cmd_callback_t *timeout_handler;
U16 hosttag;
U8 req_qidx;
Mpi3SCSIIORequest_t io_request;
int error_code;
};
struct mpi3mr_chain {
bus_dmamap_t buf_dmamap;
void *buf;
bus_addr_t buf_phys;
};
struct mpi3mr_event_handle {
TAILQ_ENTRY(mpi3mr_event_handle) eh_list;
mpi3mr_evt_callback_t *callback;
void *data;
uint8_t mask[16];
};
struct mpi3mr_fw_event_work {
U16 event;
void *event_data;
TAILQ_ENTRY(mpi3mr_fw_event_work) ev_link;
U8 send_ack;
U8 process_event;
U32 event_context;
U16 event_data_size;
};
/**
* struct delayed_dev_rmhs_node - Delayed device removal node
*
* @list: list head
* @handle: Device handle
* @iou_rc: IO Unit Control Reason Code
*/
struct delayed_dev_rmhs_node {
TAILQ_ENTRY(delayed_dev_rmhs_node) list;
U16 handle;
U8 iou_rc;
};
/**
* struct delayed_evtack_node - Delayed event ack node
*
* @list: list head
* @event: MPI3 event ID
* @event_ctx: Event context
*/
struct delayed_evtack_node {
TAILQ_ENTRY(delayed_evtack_node) list;
U8 event;
U32 event_ctx;
};
/* Reset types */
enum reset_type {
MPI3MR_NO_RESET,
MPI3MR_TRIGGER_SOFT_RESET,
};
struct mpi3mr_reset {
u_int type;
U32 reason;
int status;
bool ioctl_reset_snapdump;
};
struct mpi3mr_softc {
device_t mpi3mr_dev;
struct cdev *mpi3mr_cdev;
u_int mpi3mr_flags;
#define MPI3MR_FLAGS_SHUTDOWN (1 << 0)
#define MPI3MR_FLAGS_DIAGRESET (1 << 1)
#define MPI3MR_FLAGS_ATTACH_DONE (1 << 2)
#define MPI3MR_FLAGS_PORT_ENABLE_DONE (1 << 3)
U8 id;
int cpu_count;
char name[MPI3MR_NAME_LENGTH];
char driver_name[MPI3MR_NAME_LENGTH];
int bars;
int dma_mask;
u_int mpi3mr_debug;
struct mpi3mr_reset reset;
int max_msix_vectors;
int msix_count;
bool msix_enable;
int io_cmds_highwater;
int max_chains;
uint32_t chain_frame_size;
struct sysctl_ctx_list sysctl_ctx;
struct sysctl_oid *sysctl_tree;
char fw_version[16];
char msg_version[8];
struct mpi3mr_chain *chains;
struct callout periodic;
struct callout device_check_callout;
struct mpi3mr_cam_softc *cam_sc;
struct mpi3mr_cmd **cmd_list;
TAILQ_HEAD(, mpi3mr_cmd) cmd_list_head;
struct mtx cmd_pool_lock;
struct resource *mpi3mr_regs_resource;
bus_space_handle_t mpi3mr_bhandle;
bus_space_tag_t mpi3mr_btag;
int mpi3mr_regs_rid;
bus_dma_tag_t mpi3mr_parent_dmat;
bus_dma_tag_t buffer_dmat;
int num_reqs;
int num_replies;
int num_chains;
TAILQ_HEAD(, mpi3mr_event_handle) event_list;
struct mpi3mr_event_handle *mpi3mr_log_eh;
struct intr_config_hook mpi3mr_ich;
struct mtx mpi3mr_mtx;
struct mtx io_lock;
U8 intr_enabled;
TAILQ_HEAD(, delayed_dev_rmhs_node) delayed_rmhs_list;
TAILQ_HEAD(, delayed_evtack_node) delayed_evtack_cmds_list;
U16 num_admin_reqs;
U32 admin_req_q_sz;
U16 admin_req_pi;
U16 admin_req_ci;
bus_dma_tag_t admin_req_tag;
bus_dmamap_t admin_req_dmamap;
bus_addr_t admin_req_phys;
U8 *admin_req;
struct mtx admin_req_lock;
U16 num_admin_replies;
U32 admin_reply_q_sz;
U16 admin_reply_ci;
U8 admin_reply_ephase;
bus_dma_tag_t admin_reply_tag;
bus_dmamap_t admin_reply_dmamap;
bus_addr_t admin_reply_phys;
U8 *admin_reply;
struct mtx admin_reply_lock;
bool admin_in_use;
U32 num_reply_bufs;
bus_dma_tag_t reply_buf_tag;
bus_dmamap_t reply_buf_dmamap;
bus_addr_t reply_buf_phys;
U8 *reply_buf;
bus_addr_t reply_buf_dma_max_address;
bus_addr_t reply_buf_dma_min_address;
U16 reply_free_q_sz;
bus_dma_tag_t reply_free_q_tag;
bus_dmamap_t reply_free_q_dmamap;
bus_addr_t reply_free_q_phys;
U64 *reply_free_q;
struct mtx reply_free_q_lock;
U32 reply_free_q_host_index;
U32 num_sense_bufs;
bus_dma_tag_t sense_buf_tag;
bus_dmamap_t sense_buf_dmamap;
bus_addr_t sense_buf_phys;
U8 *sense_buf;
U16 sense_buf_q_sz;
bus_dma_tag_t sense_buf_q_tag;
bus_dmamap_t sense_buf_q_dmamap;
bus_addr_t sense_buf_q_phys;
U64 *sense_buf_q;
struct mtx sense_buf_q_lock;
U32 sense_buf_q_host_index;
void *nvme_encap_prp_list;
bus_addr_t nvme_encap_prp_list_dma;
bus_dma_tag_t nvme_encap_prp_list_dmatag;
bus_dmamap_t nvme_encap_prp_list_dma_dmamap;
U32 nvme_encap_prp_sz;
U32 ready_timeout;
struct mpi3mr_irq_context *irq_ctx;
U16 num_queues; /* Number of request/reply queues */
struct mpi3mr_op_req_queue *op_req_q;
struct mpi3mr_op_reply_queue *op_reply_q;
U16 num_hosttag_op_req_q;
struct mpi3mr_drvr_cmd init_cmds;
struct mpi3mr_ioc_facts facts;
U16 reply_sz;
U16 op_reply_sz;
U32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS];
char fwevt_worker_name[MPI3MR_NAME_LENGTH];
struct workqueue_struct *fwevt_worker_thread;
struct mtx fwevt_lock;
struct mtx target_lock;
U16 max_host_ios;
bus_dma_tag_t chain_sgl_list_tag;
struct mpi3mr_chain *chain_sgl_list;
U16 chain_bitmap_sz;
void *chain_bitmap;
struct mtx chain_buf_lock;
U16 chain_buf_count;
struct mpi3mr_drvr_cmd ioctl_cmds;
struct mpi3mr_drvr_cmd host_tm_cmds;
struct mpi3mr_drvr_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD];
struct mpi3mr_drvr_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD];
U16 devrem_bitmap_sz;
void *devrem_bitmap;
U16 dev_handle_bitmap_sz;
void *removepend_bitmap;
U16 evtack_cmds_bitmap_sz;
void *evtack_cmds_bitmap;
U32 ts_update_counter;
U8 reset_in_progress;
U8 unrecoverable;
U8 block_ioctls;
U8 in_prep_ciactv_rst;
U16 prep_ciactv_rst_counter;
struct mtx reset_mutex;
U8 prepare_for_reset;
U16 prepare_for_reset_timeout_counter;
U16 diagsave_timeout;
int logging_level;
U16 flush_io_count;
Mpi3DriverInfoLayout_t driver_info;
U16 change_count;
U8 *log_data_buffer;
U16 log_data_buffer_index;
U16 log_data_entry_size;
U8 pel_wait_pend;
U8 pel_abort_requested;
U8 pel_class;
U16 pel_locale;
struct mpi3mr_drvr_cmd pel_cmds;
struct mpi3mr_drvr_cmd pel_abort_cmd;
U32 newest_seqnum;
void *pel_seq_number;
bus_addr_t pel_seq_number_dma;
bus_dma_tag_t pel_seq_num_dmatag;
bus_dmamap_t pel_seq_num_dmamap;
U32 pel_seq_number_sz;
struct selinfo mpi3mr_select;
U32 mpi3mr_poll_waiting;
U32 mpi3mr_aen_triggered;
U16 wait_for_port_enable;
U16 track_mapping_events;
U16 pending_map_events;
mpi3mr_atomic_t fw_outstanding;
mpi3mr_atomic_t pend_ioctls;
struct proc *watchdog_thread;
void *watchdog_chan;
void *tm_chan;
u_int8_t remove_in_progress;
u_int8_t watchdog_thread_active;
u_int8_t do_timedout_reset;
bool allow_ios;
bool secure_ctrl;
mpi3mr_atomic_t pend_large_data_sz;
u_int32_t io_throttle_data_length;
u_int32_t io_throttle_high;
u_int32_t io_throttle_low;
u_int16_t num_io_throttle_group;
u_int iot_enable;
struct mpi3mr_throttle_group_info *throttle_groups;
struct dma_memory_desc ioctl_sge[MPI3MR_NUM_IOCTL_SGE];
struct dma_memory_desc ioctl_chain_sge;
struct dma_memory_desc ioctl_resp_sge;
bool ioctl_sges_allocated;
};
static __inline uint64_t
mpi3mr_regread64(struct mpi3mr_softc *sc, uint32_t offset)
{
return bus_space_read_8(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset);
}
static __inline void
mpi3mr_regwrite64(struct mpi3mr_softc *sc, uint32_t offset, uint64_t val)
{
bus_space_write_8(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset, val);
}
static __inline uint32_t
mpi3mr_regread(struct mpi3mr_softc *sc, uint32_t offset)
{
return bus_space_read_4(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset);
}
static __inline void
mpi3mr_regwrite(struct mpi3mr_softc *sc, uint32_t offset, uint32_t val)
{
bus_space_write_4(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset, val);
}
#define MPI3MR_INFO (1 << 0) /* Basic info */
#define MPI3MR_FAULT (1 << 1) /* Hardware faults */
#define MPI3MR_EVENT (1 << 2) /* Event data from the controller */
#define MPI3MR_LOG (1 << 3) /* Log data from the controller */
#define MPI3MR_RECOVERY (1 << 4) /* Command error recovery tracing */
#define MPI3MR_ERROR (1 << 5) /* Fatal driver/OS APIs failure */
#define MPI3MR_XINFO (1 << 6) /* Additional info logs*/
#define MPI3MR_TRACE (1 << 7) /* Trace functions */
#define MPI3MR_IOT (1 << 8) /* IO throttling related debugs */
#define MPI3MR_DEBUG_TM (1 << 9) /* Task management related debugs */
#define MPI3MR_DEBUG_IOCTL (1 << 10) /* IOCTL related debugs */
#define mpi3mr_printf(sc, args...) \
device_printf((sc)->mpi3mr_dev, ##args)
#define mpi3mr_print_field(sc, msg, args...) \
printf("\t" msg, ##args)
#define mpi3mr_vprintf(sc, args...) \
do { \
if (bootverbose) \
mpi3mr_printf(sc, ##args); \
} while (0)
#define mpi3mr_dprint(sc, level, msg, args...) \
do { \
if ((sc)->mpi3mr_debug & (level)) \
device_printf((sc)->mpi3mr_dev, msg, ##args); \
} while (0)
#define MPI3MR_PRINTFIELD_START(sc, tag...) \
mpi3mr_printf((sc), ##tag); \
mpi3mr_print_field((sc), ":\n")
#define MPI3MR_PRINTFIELD_END(sc, tag) \
mpi3mr_printf((sc), tag "\n")
#define MPI3MR_PRINTFIELD(sc, facts, attr, fmt) \
mpi3mr_print_field((sc), #attr ": " #fmt "\n", (facts)->attr)
#define mpi3mr_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
#define mpi3mr_kproc_exit(arg) kproc_exit(arg)
#if defined(CAM_PRIORITY_XPT)
#define MPI3MR_PRIORITY_XPT CAM_PRIORITY_XPT
#else
#define MPI3MR_PRIORITY_XPT 5
#endif
static __inline void
mpi3mr_clear_bit(int b, volatile void *p)
{
atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
}
static __inline void
mpi3mr_set_bit(int b, volatile void *p)
{
atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
}
static __inline int
mpi3mr_test_bit(int b, volatile void *p)
{
return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f));
}
static __inline int
mpi3mr_test_and_set_bit(int b, volatile void *p)
{
int ret = ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f));
atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
return ret;
}
static __inline int
mpi3mr_find_first_zero_bit(void *p, int bit_count)
{
int i, sz, j=0;
U8 *loc;
sz = bit_count % 8 ? (bit_count / 8 + 1) : (bit_count / 8);
loc = malloc(sz, M_MPI3MR, M_NOWAIT | M_ZERO);
memcpy(loc, p, sz);
for (i = 0; i < sz; i++) {
j = 0;
while (j < 8) {
if (!((loc[i] >> j) & 0x1))
goto out;
j++;
}
}
out:
free(loc, M_MPI3MR);
return (i + j);
}
#define MPI3MR_DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
void
init_completion(struct completion *completion);
void
complete(struct completion *completion);
void wait_for_completion_timeout(struct completion *completion,
U32 timeout);
void wait_for_completion_timeout_tm(struct completion *completion,
U32 timeout, struct mpi3mr_softc *sc);
void mpi3mr_add_sg_single(void *paddr, U8 flags, U32 length,
bus_addr_t dma_addr);
void mpi3mr_enable_interrupts(struct mpi3mr_softc *sc);
void mpi3mr_disable_interrupts(struct mpi3mr_softc *sc);
void mpi3mr_memaddr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
int mpi3mr_submit_admin_cmd(struct mpi3mr_softc *mrioc, void *admin_req,
U16 admin_req_sz);
int mpi3mr_submit_io(struct mpi3mr_softc *mrioc,
struct mpi3mr_op_req_queue *op_req_q, U8 *req);
int
mpi3mr_alloc_interrupts(struct mpi3mr_softc *sc, U16 setup_one);
void mpi3mr_cleanup_ioc(struct mpi3mr_softc *sc);
int mpi3mr_initialize_ioc(struct mpi3mr_softc *sc, U8 reason);
void mpi3mr_build_zero_len_sge(void *paddr);
int mpi3mr_issue_event_notification(struct mpi3mr_softc *sc);
int
mpi3mr_register_events(struct mpi3mr_softc *sc);
void mpi3mr_process_op_reply_desc(struct mpi3mr_softc *sc,
Mpi3DefaultReplyDescriptor_t *reply_desc, U64 *reply_dma);
struct mpi3mr_cmd *
mpi3mr_get_command(struct mpi3mr_softc *sc);
void
mpi3mr_release_command(struct mpi3mr_cmd *cmd);
int
mpi3mr_complete_io_cmd(struct mpi3mr_softc *sc,
struct mpi3mr_irq_context *irq_context);
int
mpi3mr_cam_detach(struct mpi3mr_softc *sc);
int
mpi3mr_cam_attach(struct mpi3mr_softc *sc);
struct mpi3mr_target *
mpi3mr_find_target_by_per_id(struct mpi3mr_cam_softc *cam_sc,
uint16_t per_id);
struct mpi3mr_target *
mpi3mr_find_target_by_dev_handle(struct mpi3mr_cam_softc *cam_sc,
uint16_t dev_handle);
int mpi3mr_create_device(struct mpi3mr_softc *sc,
Mpi3DevicePage0_t *dev_pg0);
void
mpi3mr_unmap_request(struct mpi3mr_softc *sc, struct mpi3mr_cmd *cmd);
void
init_completion(struct completion *completion);
void
complete(struct completion *completion);
void wait_for_completion_timeout(struct completion *completion,
U32 timeout);
void
poll_for_command_completion(struct mpi3mr_softc *sc,
struct mpi3mr_drvr_cmd *cmd, U16 wait);
int
mpi3mr_alloc_requests(struct mpi3mr_softc *sc);
void
mpi3mr_watchdog(void *arg);
int mpi3mr_issue_port_enable(struct mpi3mr_softc *mrioc, U8 async);
void
mpi3mr_isr(void *privdata);
int
mpi3mr_alloc_msix_queues(struct mpi3mr_softc *sc);
void
mpi3mr_destory_mtx(struct mpi3mr_softc *sc);
void
mpi3mr_free_mem(struct mpi3mr_softc *sc);
void
mpi3mr_cleanup_interrupts(struct mpi3mr_softc *sc);
int mpi3mr_setup_irqs(struct mpi3mr_softc *sc);
void mpi3mr_cleanup_event_taskq(struct mpi3mr_softc *sc);
void
mpi3mr_hexdump(void *buf, int sz, int format);
int mpi3mr_soft_reset_handler(struct mpi3mr_softc *sc,
U32 reset_reason, bool snapdump);
void
mpi3mrsas_release_simq_reinit(struct mpi3mr_cam_softc *cam_sc);
void
mpi3mr_watchdog_thread(void *arg);
void mpi3mr_add_device(struct mpi3mr_softc *sc, U16 per_id);
int mpi3mr_remove_device(struct mpi3mr_softc *sc, U16 handle);
int
mpi3mrsas_register_events(struct mpi3mr_softc *sc);
int mpi3mr_process_event_ack(struct mpi3mr_softc *sc, U8 event,
U32 event_ctx);
int mpi3mr_remove_device_from_os(struct mpi3mr_softc *sc, U16 handle);
void mpi3mr_remove_device_from_list(struct mpi3mr_softc *sc, struct mpi3mr_target *target,
bool must_delete);
void mpi3mr_update_device(struct mpi3mr_softc *mrioc,
struct mpi3mr_target *tgtdev, Mpi3DevicePage0_t *dev_pg0, bool is_added);
void mpi3mr_app_save_logdata(struct mpi3mr_softc *sc, char *event_data, U16 event_data_size);
void mpi3mr_set_io_divert_for_all_vd_in_tg(struct mpi3mr_softc *sc,
struct mpi3mr_throttle_group_info *tg, U8 divert_value);
enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_softc *sc);
void mpi3mr_poll_pend_io_completions(struct mpi3mr_softc *sc);
void int_to_lun(unsigned int lun, U8 *req_lun);
void trigger_reset_from_watchdog(struct mpi3mr_softc *sc, U8 reset_type, U32 reset_reason);
void mpi3mr_alloc_ioctl_dma_memory(struct mpi3mr_softc *sc);
#endif /*MPI3MR_H_INCLUDED*/

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/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2020-2023, Broadcom Inc. All rights reserved.
* Support: <fbsd-storage-driver.pdl@broadcom.com>
*
* Authors: Sumit Saxena <sumit.saxena@broadcom.com>
* Chandrakanth Patil <chandrakanth.patil@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
* 3. Neither the name of the Broadcom Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are
* those of the authors and should not be interpreted as representing
* official policies,either expressed or implied, of the FreeBSD Project.
*
* Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131
*
* Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD
*/
#include "mpi3mr.h"
#ifndef _MPI3MR_APP_H_
#define _MPI3MR_APP_H_
#define MPI3MR_IOCTL_ADPTYPE_AVGFAMILY 1
#define MPI3MR_IOCTL_VERSION 0x06
#define MPI3MRDRVCMD _IOWR('B', 1, struct mpi3mr_ioctl_drvcmd)
#define MPI3MRMPTCMD _IOWR('B', 2, struct mpi3mr_ioctl_mptcmd)
#define MPI3MR_IOCTL_DEFAULT_TIMEOUT (10)
#define PEND_IOCTLS_COMP_WAIT_TIME (10)
#define MPI3MR_IOCTL_LOGDATA_MAX_ENTRIES 400
#define MPI3MR_IOCTL_LOGDATA_ENTRY_HEADER_SZ 0x5
#define GET_IOC_STATUS(ioc_status) \
ioc_status & MPI3_IOCSTATUS_STATUS_MASK
/* Encapsulated NVMe command definitions */
#define MPI3MR_NVME_PRP_SIZE 8
#define MPI3MR_NVME_CMD_PRP1_OFFSET 24
#define MPI3MR_NVME_CMD_PRP2_OFFSET 32
#define MPI3MR_NVME_CMD_SGL_OFFSET 24
#define MPI3MR_NVME_DATA_FORMAT_PRP 0
#define MPI3MR_NVME_DATA_FORMAT_SGL1 1
#define MPI3MR_NVME_DATA_FORMAT_SGL2 2
#define MPI3MR_NVMESGL_DATA_SEGMENT 0x00
#define MPI3MR_NVMESGL_LAST_SEGMENT 0x03
int mpi3mr_app_attach(struct mpi3mr_softc *);
void mpi3mr_app_detach(struct mpi3mr_softc *);
static struct mpi3mr_mgmt_info mpi3mr_mgmt_info;
enum mpi3mr_ioctl_adp_state {
MPI3MR_IOCTL_ADP_STATE_UNKNOWN = 0,
MPI3MR_IOCTL_ADP_STATE_OPERATIONAL = 1,
MPI3MR_IOCTL_ADP_STATE_FAULT = 2,
MPI3MR_IOCTL_ADP_STATE_IN_RESET = 3,
MPI3MR_IOCTL_ADP_STATE_UNRECOVERABLE = 4,
};
enum mpi3mr_ioctl_data_dir {
MPI3MR_APP_DDN,
MPI3MR_APP_DDI,
MPI3MR_APP_DDO,
};
enum mpi3mr_ioctl_drvcmds_opcode {
MPI3MR_DRVRIOCTL_OPCODE_UNKNOWN = 0,
MPI3MR_DRVRIOCTL_OPCODE_ADPINFO = 1,
MPI3MR_DRVRIOCTL_OPCODE_ADPRESET = 2,
MPI3MR_DRVRIOCTL_OPCODE_TGTDEVINFO = 3,
MPI3MR_DRVRIOCTL_OPCODE_ALLTGTDEVINFO = 4,
MPI3MR_DRVRIOCTL_OPCODE_GETCHGCNT = 5,
MPI3MR_DRVRIOCTL_OPCODE_LOGDATAENABLE = 6,
MPI3MR_DRVRIOCTL_OPCODE_PELENABLE = 7,
MPI3MR_DRVRIOCTL_OPCODE_GETLOGDATA = 8,
MPI3MR_DRVRIOCTL_OPCODE_GETPCIINFO = 100,
};
enum mpi3mr_ioctl_mpibuffer_type {
MPI3MR_IOCTL_BUFTYPE_UNKNOWN,
MPI3MR_IOCTL_BUFTYPE_RAIDMGMT_CMD,
MPI3MR_IOCTL_BUFTYPE_RAIDMGMT_RESP,
MPI3MR_IOCTL_BUFTYPE_DATA_IN,
MPI3MR_IOCTL_BUFTYPE_DATA_OUT,
MPI3MR_IOCTL_BUFTYPE_MPI_REPLY,
MPI3MR_IOCTL_BUFTYPE_ERR_RESPONSE,
};
enum mpi3mr_ioctl_mpireply_type {
MPI3MR_IOCTL_MPI_REPLY_BUFTYPE_UNKNOWN,
MPI3MR_IOCTL_MPI_REPLY_BUFTYPE_STATUS,
MPI3MR_IOCTL_MPI_REPLY_BUFTYPE_ADDRESS,
};
enum mpi3mr_ioctl_reset_type {
MPI3MR_IOCTL_ADPRESET_UNKNOWN,
MPI3MR_IOCTL_ADPRESET_SOFT,
MPI3MR_IOCTL_ADPRESET_DIAG_FAULT,
};
struct mpi3mr_ioctl_drvcmd {
U8 mrioc_id;
U8 opcode;
U16 rsvd1;
U32 rsvd2;
void *data_in_buf;
void *data_out_buf;
U32 data_in_size;
U32 data_out_size;
};
struct mpi3mr_ioctl_adpinfo {
U32 adp_type;
U32 rsvd1;
U32 pci_dev_id;
U32 pci_dev_hw_rev;
U32 pci_subsys_dev_id;
U32 pci_subsys_ven_id;
U32 pci_dev:5;
U32 pci_func:3;
U32 pci_bus:8;
U32 rsvd2:16;
U32 pci_seg_id;
U32 ioctl_ver;
U8 adp_state;
U8 rsvd3;
U16 rsvd4;
U32 rsvd5[2];
Mpi3DriverInfoLayout_t driver_info;
};
struct mpi3mr_ioctl_pciinfo {
U32 config_space[64];
};
struct mpi3mr_ioctl_tgtinfo {
U32 target_id;
U8 bus_id;
U8 rsvd1;
U16 rsvd2;
U16 dev_handle;
U16 persistent_id;
U32 seq_num;
};
struct mpi3mr_device_map_info {
U16 handle;
U16 per_id;
U32 target_id;
U8 bus_id;
U8 rsvd1;
U16 rsvd2;
};
struct mpi3mr_ioctl_all_tgtinfo {
U16 num_devices;
U16 rsvd1;
U32 rsvd2;
struct mpi3mr_device_map_info dmi[1];
};
struct mpi3mr_ioctl_chgcnt {
U16 change_count;
U16 rsvd;
};
struct mpi3mr_ioctl_adpreset {
U8 reset_type;
U8 rsvd1;
U16 rsvd2;
};
struct mpi3mr_ioctl_mptcmd {
U8 mrioc_id;
U8 rsvd1;
U16 timeout;
U16 rsvd2;
U16 mpi_msg_size;
void *mpi_msg_buf;
void *buf_entry_list;
U32 buf_entry_list_size;
};
struct mpi3mr_buf_entry {
U8 buf_type;
U8 rsvd1;
U16 rsvd2;
U32 buf_len;
void *buffer;
};
struct mpi3mr_ioctl_buf_entry_list {
U8 num_of_buf_entries;
U8 rsvd1;
U16 rsvd2;
U32 rsvd3;
struct mpi3mr_buf_entry buf_entry[1];
};
struct mpi3mr_ioctl_mpt_dma_buffer {
void *user_buf;
void *kern_buf;
U32 user_buf_len;
U32 kern_buf_len;
bus_addr_t kern_buf_dma;
bus_dma_tag_t kern_buf_dmatag;
bus_dmamap_t kern_buf_dmamap;
U8 data_dir;
U16 num_dma_desc;
struct dma_memory_desc *dma_desc;
};
struct mpi3mr_ioctl_mpirepbuf {
U8 mpirep_type;
U8 rsvd1;
U16 rsvd2;
U8 repbuf[1];
};
struct mpi3mr_nvme_pt_sge {
U64 base_addr;
U32 length;
U16 rsvd;
U8 rsvd1;
U8 sub_type:4;
U8 type:4;
};
struct mpi3mr_log_data_entry {
U8 valid_entry;
U8 rsvd1;
U16 rsvd2;
U8 data[1];
};
struct mpi3mr_ioctl_logdata_enable {
U16 max_entries;
U16 rsvd;
};
struct mpi3mr_ioctl_pel_enable {
U16 pel_locale;
U8 pel_class;
U8 rsvd;
};
int
mpi3mr_pel_abort(struct mpi3mr_softc *sc);
void
mpi3mr_pel_getseq_complete(struct mpi3mr_softc *sc,
struct mpi3mr_drvr_cmd *drvr_cmd);
void
mpi3mr_issue_pel_wait(struct mpi3mr_softc *sc,
struct mpi3mr_drvr_cmd *drvr_cmd);
void
mpi3mr_pel_wait_complete(struct mpi3mr_softc *sc,
struct mpi3mr_drvr_cmd *drvr_cmd);
void
mpi3mr_send_pel_getseq(struct mpi3mr_softc *sc,
struct mpi3mr_drvr_cmd *drvr_cmd);
void
mpi3mr_app_send_aen(struct mpi3mr_softc *sc);
#endif /* !_MPI3MR_API_H_ */

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/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2020-2023, Broadcom Inc. All rights reserved.
* Support: <fbsd-storage-driver.pdl@broadcom.com>
*
* Authors: Sumit Saxena <sumit.saxena@broadcom.com>
* Chandrakanth Patil <chandrakanth.patil@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
* 3. Neither the name of the Broadcom Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are
* those of the authors and should not be interpreted as representing
* official policies,either expressed or implied, of the FreeBSD Project.
*
* Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131
*
* Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD
*/
#include "mpi3mr.h"
struct mpi3mr_fw_event_work;
struct mpi3mr_throttle_group_info {
U8 io_divert;
U16 fw_qd;
U16 modified_qd;
U16 id;
U32 high;
U32 low;
mpi3mr_atomic_t pend_large_data_sz;
};
struct mpi3mr_tgt_dev_sassata {
U64 sas_address;
U16 dev_info;
};
struct mpi3mr_tgt_dev_pcie {
U32 mdts;
U16 capb;
U8 pgsz;
U8 abort_to;
U8 reset_to;
U16 dev_info;
};
struct mpi3mr_tgt_dev_volume {
U8 state;
U16 tg_id;
U32 tg_high;
U32 tg_low;
struct mpi3mr_throttle_group_info *tg;
};
typedef union _mpi3mr_form_spec_inf {
struct mpi3mr_tgt_dev_sassata sassata_inf;
struct mpi3mr_tgt_dev_pcie pcie_inf;
struct mpi3mr_tgt_dev_volume vol_inf;
} mpi3mr_form_spec_inf;
struct mpi3mr_target {
uint16_t dev_handle;
uint16_t slot;
uint16_t per_id;
uint8_t dev_type;
volatile uint8_t is_hidden;
volatile uint8_t dev_removed;
U8 dev_removedelay;
mpi3mr_atomic_t block_io;
uint8_t exposed_to_os;
uint16_t qdepth;
uint64_t wwid;
mpi3mr_form_spec_inf dev_spec;
uint16_t tid;
uint16_t exp_dev_handle;
uint16_t phy_num;
uint64_t sasaddr;
uint16_t parent_handle;
uint64_t parent_sasaddr;
uint32_t parent_devinfo;
mpi3mr_atomic_t outstanding;
uint8_t scsi_req_desc_type;
TAILQ_ENTRY(mpi3mr_target) tgt_next;
uint16_t handle;
uint8_t link_rate;
uint8_t encl_level_valid;
uint8_t encl_level;
char connector_name[4];
uint64_t devname;
uint32_t devinfo;
uint16_t encl_handle;
uint16_t encl_slot;
uint8_t flags;
#define MPI3MRSAS_TARGET_INREMOVAL (1 << 3)
uint8_t io_throttle_enabled;
uint8_t io_divert;
struct mpi3mr_throttle_group_info *throttle_group;
uint64_t q_depth;
enum mpi3mr_target_state state;
};
struct mpi3mr_cam_softc {
struct mpi3mr_softc *sc;
u_int flags;
#define MPI3MRSAS_IN_DISCOVERY (1 << 0)
#define MPI3MRSAS_IN_STARTUP (1 << 1)
#define MPI3MRSAS_DISCOVERY_TIMEOUT_PENDING (1 << 2)
#define MPI3MRSAS_QUEUE_FROZEN (1 << 3)
#define MPI3MRSAS_SHUTDOWN (1 << 4)
u_int maxtargets;
struct cam_devq *devq;
struct cam_sim *sim;
struct cam_path *path;
struct intr_config_hook sas_ich;
struct callout discovery_callout;
struct mpi3mr_event_handle *mpi3mr_eh;
u_int startup_refcount;
struct proc *sysctl_proc;
struct taskqueue *ev_tq;
struct task ev_task;
TAILQ_HEAD(, mpi3mr_fw_event_work) ev_queue;
TAILQ_HEAD(, mpi3mr_target) tgt_list;
};
MALLOC_DECLARE(M_MPI3MRSAS);
static __inline void
mpi3mr_set_ccbstatus(union ccb *ccb, int status)
{
ccb->ccb_h.status &= ~CAM_STATUS_MASK;
ccb->ccb_h.status |= status;
}
static __inline int
mpi3mr_get_ccbstatus(union ccb *ccb)
{
return (ccb->ccb_h.status & CAM_STATUS_MASK);
}
static __inline void mpi3mr_print_cdb(union ccb *ccb)
{
struct ccb_scsiio *csio;
struct mpi3mr_cam_softc *cam_sc;
struct cam_sim *sim;
int i;
sim = xpt_path_sim(ccb->ccb_h.path);
cam_sc = cam_sim_softc(sim);
csio = &ccb->csio;
mpi3mr_dprint(cam_sc->sc, MPI3MR_INFO, "tgtID: %d CDB: ", csio->ccb_h.target_id);
for (i = 0; i < csio->cdb_len; i++)
printf("%x ", csio->cdb_io.cdb_bytes[i]);
printf("\n");
}
void mpi3mr_rescan_target(struct mpi3mr_softc *sc, struct mpi3mr_target *targ);
void mpi3mr_discovery_end(struct mpi3mr_cam_softc *sassc);
void mpi3mr_prepare_for_tm(struct mpi3mr_softc *sc, struct mpi3mr_cmd *tm,
struct mpi3mr_target *target, lun_id_t lun_id);
void mpi3mr_startup_increment(struct mpi3mr_cam_softc *sassc);
void mpi3mr_startup_decrement(struct mpi3mr_cam_softc *sassc);
void mpi3mr_firmware_event_work(void *arg, int pending);
int mpi3mr_check_id(struct mpi3mr_cam_softc *sassc, int id);
int
mpi3mr_cam_attach(struct mpi3mr_softc *sc);
int
mpi3mr_cam_detach(struct mpi3mr_softc *sc);
void
mpi3mr_evt_handler(struct mpi3mr_softc *sc, uintptr_t data,
MPI3_EVENT_NOTIFICATION_REPLY *event);

698
sys/dev/mpi3mr/mpi3mr_pci.c Normal file
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@ -0,0 +1,698 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2020-2023, Broadcom Inc. All rights reserved.
* Support: <fbsd-storage-driver.pdl@broadcom.com>
*
* Authors: Sumit Saxena <sumit.saxena@broadcom.com>
* Chandrakanth Patil <chandrakanth.patil@broadcom.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
* 3. Neither the name of the Broadcom Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are
* those of the authors and should not be interpreted as representing
* official policies,either expressed or implied, of the FreeBSD Project.
*
* Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131
*
* Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD
*/
#include "mpi3mr.h"
#include "mpi3mr_cam.h"
#include "mpi3mr_app.h"
static int sc_ids;
static int mpi3mr_pci_probe(device_t);
static int mpi3mr_pci_attach(device_t);
static int mpi3mr_pci_detach(device_t);
static int mpi3mr_pci_suspend(device_t);
static int mpi3mr_pci_resume(device_t);
static int mpi3mr_setup_resources(struct mpi3mr_softc *sc);
static void mpi3mr_release_resources(struct mpi3mr_softc *);
static void mpi3mr_teardown_irqs(struct mpi3mr_softc *sc);
extern void mpi3mr_watchdog_thread(void *arg);
static device_method_t mpi3mr_methods[] = {
DEVMETHOD(device_probe, mpi3mr_pci_probe),
DEVMETHOD(device_attach, mpi3mr_pci_attach),
DEVMETHOD(device_detach, mpi3mr_pci_detach),
DEVMETHOD(device_suspend, mpi3mr_pci_suspend),
DEVMETHOD(device_resume, mpi3mr_pci_resume),
DEVMETHOD(bus_print_child, bus_generic_print_child),
DEVMETHOD(bus_driver_added, bus_generic_driver_added),
{ 0, 0 }
};
char fmt_os_ver[16];
SYSCTL_NODE(_hw, OID_AUTO, mpi3mr, CTLFLAG_RD, 0, "MPI3MR Driver Parameters");
MALLOC_DEFINE(M_MPI3MR, "mpi3mrbuf", "Buffers for the MPI3MR driver");
static driver_t mpi3mr_pci_driver = {
"mpi3mr",
mpi3mr_methods,
sizeof(struct mpi3mr_softc)
};
struct mpi3mr_ident {
uint16_t vendor;
uint16_t device;
uint16_t subvendor;
uint16_t subdevice;
u_int flags;
const char *desc;
} mpi3mr_identifiers[] = {
{ MPI3_MFGPAGE_VENDORID_BROADCOM, MPI3_MFGPAGE_DEVID_SAS4116,
0xffff, 0xffff, 0, "Broadcom MPIMR 3.0 controller" },
};
DRIVER_MODULE(mpi3mr, pci, mpi3mr_pci_driver, 0, 0);
MODULE_PNP_INFO("U16:vendor;U16:device;U16:subvendor;U16:subdevice;D:#", pci,
mpi3mr, mpi3mr_identifiers, nitems(mpi3mr_identifiers) - 1);
MODULE_DEPEND(mpi3mr, cam, 1, 1, 1);
/*
* mpi3mr_setup_sysctl: setup sysctl values for mpi3mr
* input: Adapter instance soft state
*
* Setup sysctl entries for mpi3mr driver.
*/
static void
mpi3mr_setup_sysctl(struct mpi3mr_softc *sc)
{
struct sysctl_ctx_list *sysctl_ctx = NULL;
struct sysctl_oid *sysctl_tree = NULL;
char tmpstr[80], tmpstr2[80];
/*
* Setup the sysctl variable so the user can change the debug level
* on the fly.
*/
snprintf(tmpstr, sizeof(tmpstr), "MPI3MR controller %d",
device_get_unit(sc->mpi3mr_dev));
snprintf(tmpstr2, sizeof(tmpstr2), "%d", device_get_unit(sc->mpi3mr_dev));
sysctl_ctx = device_get_sysctl_ctx(sc->mpi3mr_dev);
if (sysctl_ctx != NULL)
sysctl_tree = device_get_sysctl_tree(sc->mpi3mr_dev);
if (sysctl_tree == NULL) {
sysctl_ctx_init(&sc->sysctl_ctx);
sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
SYSCTL_STATIC_CHILDREN(_hw_mpi3mr), OID_AUTO, tmpstr2,
CTLFLAG_RD, 0, tmpstr);
if (sc->sysctl_tree == NULL)
return;
sysctl_ctx = &sc->sysctl_ctx;
sysctl_tree = sc->sysctl_tree;
}
SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
OID_AUTO, "driver_version", CTLFLAG_RD, MPI3MR_DRIVER_VERSION,
strlen(MPI3MR_DRIVER_VERSION), "driver version");
SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
OID_AUTO, "fw_outstanding", CTLFLAG_RD,
&sc->fw_outstanding.val_rdonly, 0, "FW outstanding commands");
SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
OID_AUTO, "io_cmds_highwater", CTLFLAG_RD,
&sc->io_cmds_highwater, 0, "Max FW outstanding commands");
SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
OID_AUTO, "mpi3mr_debug", CTLFLAG_RW, &sc->mpi3mr_debug, 0,
"Driver debug level");
SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
OID_AUTO, "reset", CTLFLAG_RW, &sc->reset.type, 0,
"Soft reset(1)/Diag reset(2)");
SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
OID_AUTO, "iot_enable", CTLFLAG_RW, &sc->iot_enable, 0,
"IO throttling enable at driver level(for debug purpose)");
}
/*
* mpi3mr_get_tunables: get tunable parameters.
* input: Adapter instance soft state
*
* Get tunable parameters. This will help to debug driver at boot time.
*/
static void
mpi3mr_get_tunables(struct mpi3mr_softc *sc)
{
char tmpstr[80];
sc->mpi3mr_debug =
(MPI3MR_ERROR | MPI3MR_INFO | MPI3MR_FAULT);
sc->reset_in_progress = 0;
sc->reset.type = 0;
sc->iot_enable = 1;
/*
* Grab the global variables.
*/
TUNABLE_INT_FETCH("hw.mpi3mr.debug_level", &sc->mpi3mr_debug);
TUNABLE_INT_FETCH("hw.mpi3mr.ctrl_reset", &sc->reset.type);
TUNABLE_INT_FETCH("hw.mpi3mr.iot_enable", &sc->iot_enable);
/* Grab the unit-instance variables */
snprintf(tmpstr, sizeof(tmpstr), "dev.mpi3mr.%d.debug_level",
device_get_unit(sc->mpi3mr_dev));
TUNABLE_INT_FETCH(tmpstr, &sc->mpi3mr_debug);
snprintf(tmpstr, sizeof(tmpstr), "dev.mpi3mr.%d.reset",
device_get_unit(sc->mpi3mr_dev));
TUNABLE_INT_FETCH(tmpstr, &sc->reset.type);
snprintf(tmpstr, sizeof(tmpstr), "dev.mpi3mr.%d.iot_enable",
device_get_unit(sc->mpi3mr_dev));
TUNABLE_INT_FETCH(tmpstr, &sc->iot_enable);
}
static struct mpi3mr_ident *
mpi3mr_find_ident(device_t dev)
{
struct mpi3mr_ident *m;
for (m = mpi3mr_identifiers; m->vendor != 0; m++) {
if (m->vendor != pci_get_vendor(dev))
continue;
if (m->device != pci_get_device(dev))
continue;
if ((m->subvendor != 0xffff) &&
(m->subvendor != pci_get_subvendor(dev)))
continue;
if ((m->subdevice != 0xffff) &&
(m->subdevice != pci_get_subdevice(dev)))
continue;
return (m);
}
return (NULL);
}
static int
mpi3mr_pci_probe(device_t dev)
{
static u_int8_t first_ctrl = 1;
struct mpi3mr_ident *id;
char raw_os_ver[16];
if ((id = mpi3mr_find_ident(dev)) != NULL) {
if (first_ctrl) {
first_ctrl = 0;
MPI3MR_OS_VERSION(raw_os_ver, fmt_os_ver);
printf("mpi3mr: Loading Broadcom mpi3mr driver version: %s OS version: %s\n",
MPI3MR_DRIVER_VERSION, fmt_os_ver);
}
device_set_desc(dev, id->desc);
device_set_desc(dev, id->desc);
return (BUS_PROBE_DEFAULT);
}
return (ENXIO);
}
static void
mpi3mr_release_resources(struct mpi3mr_softc *sc)
{
if (sc->mpi3mr_parent_dmat != NULL) {
bus_dma_tag_destroy(sc->mpi3mr_parent_dmat);
}
if (sc->mpi3mr_regs_resource != NULL) {
bus_release_resource(sc->mpi3mr_dev, SYS_RES_MEMORY,
sc->mpi3mr_regs_rid, sc->mpi3mr_regs_resource);
}
}
static int mpi3mr_setup_resources(struct mpi3mr_softc *sc)
{
int i;
device_t dev = sc->mpi3mr_dev;
pci_enable_busmaster(dev);
for (i = 0; i < PCI_MAXMAPS_0; i++) {
sc->mpi3mr_regs_rid = PCIR_BAR(i);
if ((sc->mpi3mr_regs_resource = bus_alloc_resource_any(dev,
SYS_RES_MEMORY, &sc->mpi3mr_regs_rid, RF_ACTIVE)) != NULL)
break;
}
if (sc->mpi3mr_regs_resource == NULL) {
mpi3mr_printf(sc, "Cannot allocate PCI registers\n");
return (ENXIO);
}
sc->mpi3mr_btag = rman_get_bustag(sc->mpi3mr_regs_resource);
sc->mpi3mr_bhandle = rman_get_bushandle(sc->mpi3mr_regs_resource);
/* Allocate the parent DMA tag */
if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1, 0, /* algnmnt, boundary */
BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
BUS_SPACE_UNRESTRICTED, /* nsegments */
BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
0, /* flags */
NULL, NULL, /* lockfunc, lockarg */
&sc->mpi3mr_parent_dmat)) {
mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate parent DMA tag\n");
return (ENOMEM);
}
sc->max_msix_vectors = pci_msix_count(dev);
return 0;
}
static int
mpi3mr_startup(struct mpi3mr_softc *sc)
{
sc->mpi3mr_flags &= ~MPI3MR_FLAGS_PORT_ENABLE_DONE;
mpi3mr_issue_port_enable(sc, 1);
return (0);
}
/* Run through any late-start handlers. */
static void
mpi3mr_ich_startup(void *arg)
{
struct mpi3mr_softc *sc;
sc = (struct mpi3mr_softc *)arg;
mpi3mr_dprint(sc, MPI3MR_XINFO, "%s entry\n", __func__);
mtx_lock(&sc->mpi3mr_mtx);
mpi3mr_startup(sc);
mtx_unlock(&sc->mpi3mr_mtx);
mpi3mr_dprint(sc, MPI3MR_XINFO, "disestablish config intrhook\n");
config_intrhook_disestablish(&sc->mpi3mr_ich);
sc->mpi3mr_ich.ich_arg = NULL;
mpi3mr_dprint(sc, MPI3MR_XINFO, "%s exit\n", __func__);
}
/**
* mpi3mr_ctrl_security_status -Check controller secure status
* @pdev: PCI device instance
*
* Read the Device Serial Number capability from PCI config
* space and decide whether the controller is secure or not.
*
* Return: 0 on success, non-zero on failure.
*/
static int
mpi3mr_ctrl_security_status(device_t dev)
{
int dev_serial_num, retval = 0;
uint32_t cap_data, ctrl_status, debug_status;
/* Check if Device serial number extended capability is supported */
if (pci_find_extcap(dev, PCIZ_SERNUM, &dev_serial_num) != 0) {
device_printf(dev,
"PCIZ_SERNUM is not supported\n");
return -1;
}
cap_data = pci_read_config(dev, dev_serial_num + 4, 4);
debug_status = cap_data & MPI3MR_CTLR_SECURE_DBG_STATUS_MASK;
ctrl_status = cap_data & MPI3MR_CTLR_SECURITY_STATUS_MASK;
switch (ctrl_status) {
case MPI3MR_INVALID_DEVICE:
device_printf(dev,
"Invalid (Non secure) controller is detected: DID: 0x%x: SVID: 0x%x: SDID: 0x%x\n",
pci_get_device(dev), pci_get_subvendor(dev),
pci_get_subdevice(dev));
retval = -1;
break;
case MPI3MR_CONFIG_SECURE_DEVICE:
if (!debug_status)
device_printf(dev, "Config secure controller is detected\n");
break;
case MPI3MR_HARD_SECURE_DEVICE:
device_printf(dev, "Hard secure controller is detected\n");
break;
case MPI3MR_TAMPERED_DEVICE:
device_printf(dev,
"Tampered (Non secure) controller is detected: DID: 0x%x: SVID: 0x%x: SDID: 0x%x\n",
pci_get_device(dev), pci_get_subvendor(dev),
pci_get_subdevice(dev));
retval = -1;
break;
default:
retval = -1;
break;
}
if (!retval && debug_status) {
device_printf(dev,
"Secure Debug (Non secure) controller is detected: DID: 0x%x: SVID: 0x%x: SDID: 0x%x\n",
pci_get_device(dev), pci_get_subvendor(dev),
pci_get_subdevice(dev));
retval = -1;
}
return retval;
}
/*
* mpi3mr_pci_attach - PCI entry point
* @dev: pointer to device struct
*
* This function does the setup of PCI and registers, allocates controller resources,
* initializes mutexes, linked lists and registers interrupts, CAM and initializes
* the controller.
*
* Return: 0 on success and proper error codes on failure
*/
static int
mpi3mr_pci_attach(device_t dev)
{
struct mpi3mr_softc *sc;
int error;
sc = device_get_softc(dev);
bzero(sc, sizeof(*sc));
sc->mpi3mr_dev = dev;
/* Don't load driver for Non-Secure controllers */
if (mpi3mr_ctrl_security_status(dev)) {
sc->secure_ctrl = false;
return 0;
}
sc->secure_ctrl = true;
if ((error = mpi3mr_setup_resources(sc)) != 0)
goto load_failed;
sc->id = sc_ids++;
mpi3mr_atomic_set(&sc->fw_outstanding, 0);
mpi3mr_atomic_set(&sc->pend_ioctls, 0);
sc->admin_req = NULL;
sc->admin_reply = NULL;
sprintf(sc->driver_name, "%s", MPI3MR_DRIVER_NAME);
sprintf(sc->name, "%s%d", sc->driver_name, sc->id);
sc->mpi3mr_dev = dev;
mpi3mr_get_tunables(sc);
if ((error = mpi3mr_initialize_ioc(sc, MPI3MR_INIT_TYPE_INIT)) != 0) {
mpi3mr_dprint(sc, MPI3MR_ERROR, "FW initialization failed\n");
goto load_failed;
}
if ((error = mpi3mr_alloc_requests(sc)) != 0) {
mpi3mr_dprint(sc, MPI3MR_ERROR, "Command frames allocation failed\n");
goto load_failed;
}
if ((error = mpi3mr_cam_attach(sc)) != 0) {
mpi3mr_dprint(sc, MPI3MR_ERROR, "CAM attach failed\n");
goto load_failed;
}
error = mpi3mr_kproc_create(mpi3mr_watchdog_thread, sc,
&sc->watchdog_thread, 0, 0, "mpi3mr_watchdog%d",
device_get_unit(sc->mpi3mr_dev));
if (error) {
device_printf(sc->mpi3mr_dev, "Error %d starting OCR thread\n", error);
goto load_failed;
}
sc->mpi3mr_ich.ich_func = mpi3mr_ich_startup;
sc->mpi3mr_ich.ich_arg = sc;
if (config_intrhook_establish(&sc->mpi3mr_ich) != 0) {
mpi3mr_dprint(sc, MPI3MR_ERROR,
"Cannot establish MPI3MR ICH config hook\n");
error = EINVAL;
}
mpi3mr_dprint(sc, MPI3MR_INFO, "allocating ioctl dma buffers\n");
mpi3mr_alloc_ioctl_dma_memory(sc);
if ((error = mpi3mr_app_attach(sc)) != 0) {
mpi3mr_dprint(sc, MPI3MR_ERROR, "APP/IOCTL attach failed\n");
goto load_failed;
}
mpi3mr_setup_sysctl(sc);
return 0;
load_failed:
mpi3mr_cleanup_interrupts(sc);
mpi3mr_free_mem(sc);
mpi3mr_app_detach(sc);
mpi3mr_cam_detach(sc);
mpi3mr_destory_mtx(sc);
mpi3mr_release_resources(sc);
return error;
}
void mpi3mr_cleanup_interrupts(struct mpi3mr_softc *sc)
{
mpi3mr_disable_interrupts(sc);
mpi3mr_teardown_irqs(sc);
if (sc->irq_ctx) {
free(sc->irq_ctx, M_MPI3MR);
sc->irq_ctx = NULL;
}
if (sc->msix_enable)
pci_release_msi(sc->mpi3mr_dev);
sc->msix_count = 0;
}
int mpi3mr_setup_irqs(struct mpi3mr_softc *sc)
{
device_t dev;
int error;
int i, rid, initial_rid;
struct mpi3mr_irq_context *irq_ctx;
struct irq_info *irq_info;
dev = sc->mpi3mr_dev;
error = -1;
if (sc->msix_enable)
initial_rid = 1;
else
initial_rid = 0;
for (i = 0; i < sc->msix_count; i++) {
irq_ctx = &sc->irq_ctx[i];
irq_ctx->msix_index = i;
irq_ctx->sc = sc;
irq_info = &irq_ctx->irq_info;
rid = i + initial_rid;
irq_info->irq_rid = rid;
irq_info->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&irq_info->irq_rid, RF_ACTIVE);
if (irq_info->irq == NULL) {
mpi3mr_dprint(sc, MPI3MR_ERROR,
"Cannot allocate interrupt RID %d\n", rid);
sc->msix_count = i;
break;
}
error = bus_setup_intr(dev, irq_info->irq,
INTR_MPSAFE | INTR_TYPE_CAM, NULL, mpi3mr_isr,
irq_ctx, &irq_info->intrhand);
if (error) {
mpi3mr_dprint(sc, MPI3MR_ERROR,
"Cannot setup interrupt RID %d\n", rid);
sc->msix_count = i;
break;
}
}
mpi3mr_dprint(sc, MPI3MR_INFO, "Set up %d MSI-x interrupts\n", sc->msix_count);
return (error);
}
static void
mpi3mr_teardown_irqs(struct mpi3mr_softc *sc)
{
struct irq_info *irq_info;
int i;
for (i = 0; i < sc->msix_count; i++) {
irq_info = &sc->irq_ctx[i].irq_info;
if (irq_info->irq != NULL) {
bus_teardown_intr(sc->mpi3mr_dev, irq_info->irq,
irq_info->intrhand);
bus_release_resource(sc->mpi3mr_dev, SYS_RES_IRQ,
irq_info->irq_rid, irq_info->irq);
}
}
}
/*
* Allocate, but don't assign interrupts early. Doing it before requesting
* the IOCFacts message informs the firmware that we want to do MSI-X
* multiqueue. We might not use all of the available messages, but there's
* no reason to re-alloc if we don't.
*/
int
mpi3mr_alloc_interrupts(struct mpi3mr_softc *sc, U16 setup_one)
{
int error, msgs;
U16 num_queues;
error = 0;
msgs = 0;
mpi3mr_cleanup_interrupts(sc);
if (setup_one) {
msgs = 1;
} else {
msgs = min(sc->max_msix_vectors, sc->cpu_count);
num_queues = min(sc->facts.max_op_reply_q, sc->facts.max_op_req_q);
msgs = min(msgs, num_queues);
mpi3mr_dprint(sc, MPI3MR_INFO, "Supported MSI-x count: %d "
" CPU count: %d Requested MSI-x count: %d\n",
sc->max_msix_vectors,
sc->cpu_count, msgs);
}
if (msgs != 0) {
error = pci_alloc_msix(sc->mpi3mr_dev, &msgs);
if (error) {
mpi3mr_dprint(sc, MPI3MR_ERROR,
"Could not allocate MSI-x interrupts Error: %x\n", error);
goto out_failed;
} else
sc->msix_enable = 1;
}
sc->msix_count = msgs;
sc->irq_ctx = malloc(sizeof(struct mpi3mr_irq_context) * msgs,
M_MPI3MR, M_NOWAIT | M_ZERO);
if (!sc->irq_ctx) {
mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot alloc memory for interrupt info\n");
error = -1;
goto out_failed;
}
mpi3mr_dprint(sc, MPI3MR_XINFO, "Allocated %d MSI-x interrupts\n", msgs);
return error;
out_failed:
mpi3mr_cleanup_interrupts(sc);
return (error);
}
static int
mpi3mr_pci_detach(device_t dev)
{
struct mpi3mr_softc *sc;
int i = 0;
sc = device_get_softc(dev);
if (!sc->secure_ctrl)
return 0;
sc->mpi3mr_flags |= MPI3MR_FLAGS_SHUTDOWN;
if (sc->sysctl_tree != NULL)
sysctl_ctx_free(&sc->sysctl_ctx);
if (sc->watchdog_thread_active)
wakeup(&sc->watchdog_chan);
while (sc->reset_in_progress && (i < PEND_IOCTLS_COMP_WAIT_TIME)) {
i++;
if (!(i % 5)) {
mpi3mr_dprint(sc, MPI3MR_INFO,
"[%2d]waiting for reset to be finished from %s\n", i, __func__);
}
pause("mpi3mr_shutdown", hz);
}
i = 0;
while (sc->watchdog_thread_active && (i < 180)) {
i++;
if (!(i % 5)) {
mpi3mr_dprint(sc, MPI3MR_INFO,
"[%2d]waiting for "
"mpi3mr_reset thread to quit reset %d\n", i,
sc->watchdog_thread_active);
}
pause("mpi3mr_shutdown", hz);
}
i = 0;
while (mpi3mr_atomic_read(&sc->pend_ioctls) && (i < 180)) {
i++;
if (!(i % 5)) {
mpi3mr_dprint(sc, MPI3MR_INFO,
"[%2d]waiting for IOCTL to be finished from %s\n", i, __func__);
}
pause("mpi3mr_shutdown", hz);
}
mpi3mr_cleanup_ioc(sc);
mpi3mr_cleanup_event_taskq(sc);
mpi3mr_app_detach(sc);
mpi3mr_cam_detach(sc);
mpi3mr_cleanup_interrupts(sc);
mpi3mr_destory_mtx(sc);
mpi3mr_free_mem(sc);
mpi3mr_release_resources(sc);
sc_ids--;
return (0);
}
static int
mpi3mr_pci_suspend(device_t dev)
{
return (EINVAL);
}
static int
mpi3mr_pci_resume(device_t dev)
{
return (EINVAL);
}

6
sys/modules/Makefile
View File

@ -259,6 +259,7 @@ SUBDIR= \
${_mlx5ib} \
mmc \
mmcsd \
${_mpi3mr} \
${_mpr} \
${_mps} \
mpt \
@ -629,6 +630,11 @@ _rtwnfw= rtwnfw
_cxgbe= cxgbe
.endif
# This has only been tested on amd64 and arm64
.if ${MACHINE_ARCH} == "amd64" || ${MACHINE_ARCH} == "arm64"
_mpi3mr=mpi3mr
.endif
.if ${MACHINE_ARCH} == "amd64" || ${MACHINE_ARCH} == "arm64" || ${MACHINE_ARCH:Mpowerpc64*}
_ice= ice
.if ${MK_SOURCELESS_UCODE} != "no"

13
sys/modules/mpi3mr/Makefile Normal file
View File

@ -0,0 +1,13 @@
# $FreeBSD$
.PATH: ${SRCTOP}/sys/dev/mpi3mr
KMOD= mpi3mr
SRCS= mpi3mr_pci.c mpi3mr.c mpi3mr_cam.c mpi3mr_app.c
SRCS+= opt_cam.h
SRCS+= device_if.h bus_if.h pci_if.h
.include <bsd.kmod.mk>
CWARNFLAGS.mpi3mr_sas.c= ${NO_WUNNEEDED_INTERNAL_DECL}
CWARNFLAGS.mpi3mr_mapping.c= ${NO_WSOMETIMES_UNINITIALIZED}