if_awg: Use syscon prop if it exists
The emac bindings that are landing in Linux 4.15 specify a syscon property on the emac node that point to /soc/syscon. Use this property if it's specified, but maintain backwards compatibility with the old method. The older method is still used for boards that we get .dtb from u-boot, such as pine64, that did not yet have stable emac bindings. Tested on: Banana Pi-M3 (a83t) Tested on: Pine64 (a64) Reviewed by: manu Differential Revision: https://reviews.freebsd.org/D13296
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2defb358ea
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=327563
@ -20,7 +20,7 @@ arm/allwinner/aw_usbphy.c optional ehci | ohci
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arm/allwinner/aw_wdog.c standard
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arm/allwinner/axp209.c optional axp209
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arm/allwinner/axp81x.c optional axp81x
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arm/allwinner/if_awg.c optional awg
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arm/allwinner/if_awg.c optional awg ext_resources syscon
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arm/allwinner/if_emac.c optional emac
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arm/allwinner/sunxi_dma_if.m standard
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dev/iicbus/twsi/a10_twsi.c optional twsi
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@ -69,7 +69,9 @@ __FBSDID("$FreeBSD$");
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/extres/regulator/regulator.h>
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#include <dev/extres/syscon/syscon.h>
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#include "syscon_if.h"
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#include "miibus_if.h"
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#include "gpio_if.h"
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@ -105,6 +107,7 @@ __FBSDID("$FreeBSD$");
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#define RX_BATCH_DEFAULT 64
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/* syscon EMAC clock register */
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#define EMAC_CLK_REG 0x30
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#define EMAC_CLK_EPHY_ADDR (0x1f << 20) /* H3 */
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#define EMAC_CLK_EPHY_ADDR_SHIFT 20
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#define EMAC_CLK_EPHY_LED_POL (1 << 17) /* H3 */
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@ -203,6 +206,7 @@ struct awg_softc {
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int link;
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int if_flags;
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enum awg_type type;
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struct syscon *syscon;
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struct awg_txring tx;
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struct awg_rxring rx;
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@ -217,6 +221,9 @@ static struct resource_spec awg_spec[] = {
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static void awg_txeof(struct awg_softc *sc);
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static uint32_t syscon_read_emac_clk_reg(device_t dev);
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static void syscon_write_emac_clk_reg(device_t dev, uint32_t val);
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static int
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awg_miibus_readreg(device_t dev, int phy, int reg)
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{
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@ -1153,6 +1160,32 @@ awg_ioctl(if_t ifp, u_long cmd, caddr_t data)
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return (error);
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}
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static uint32_t
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syscon_read_emac_clk_reg(device_t dev)
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{
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struct awg_softc *sc;
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sc = device_get_softc(dev);
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if (sc->syscon != NULL)
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return (SYSCON_READ_4(sc->syscon, EMAC_CLK_REG));
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else if (sc->res[_RES_SYSCON] != NULL)
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return (bus_read_4(sc->res[_RES_SYSCON], 0));
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return (0);
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}
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static void
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syscon_write_emac_clk_reg(device_t dev, uint32_t val)
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{
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struct awg_softc *sc;
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sc = device_get_softc(dev);
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if (sc->syscon != NULL)
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SYSCON_WRITE_4(sc->syscon, EMAC_CLK_REG, val);
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else if (sc->res[_RES_SYSCON] != NULL)
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bus_write_4(sc->res[_RES_SYSCON], 0, val);
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}
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static int
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awg_setup_phy(device_t dev)
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{
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@ -1163,19 +1196,31 @@ awg_setup_phy(device_t dev)
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phandle_t node;
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uint32_t reg, tx_delay, rx_delay;
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int error;
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bool use_syscon;
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sc = device_get_softc(dev);
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node = ofw_bus_get_node(dev);
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use_syscon = false;
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if (OF_getprop_alloc(node, "phy-mode", 1, (void **)&phy_type) == 0)
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return (0);
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if (sc->syscon != NULL || sc->res[_RES_SYSCON] != NULL)
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use_syscon = true;
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if (bootverbose)
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device_printf(dev, "PHY type: %s, conf mode: %s\n", phy_type,
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sc->res[_RES_SYSCON] != NULL ? "reg" : "clk");
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use_syscon ? "reg" : "clk");
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if (sc->res[_RES_SYSCON] != NULL) {
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reg = bus_read_4(sc->res[_RES_SYSCON], 0);
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if (use_syscon) {
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/*
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* Abstract away writing to syscon for devices like the pine64.
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* For the pine64, we get dtb from U-Boot and it still uses the
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* legacy setup of specifying syscon register in emac node
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* rather than as its own node and using an xref in emac.
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* These abstractions can go away once U-Boot dts is up-to-date.
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*/
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reg = syscon_read_emac_clk_reg(dev);
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reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN);
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if (strncmp(phy_type, "rgmii", 5) == 0)
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reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII;
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@ -1215,7 +1260,7 @@ awg_setup_phy(device_t dev)
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if (bootverbose)
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device_printf(dev, "EMAC clock: 0x%08x\n", reg);
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bus_write_4(sc->res[_RES_SYSCON], 0, reg);
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syscon_write_emac_clk_reg(dev, reg);
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} else {
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if (strncmp(phy_type, "rgmii", 5) == 0)
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tx_parent_name = "emac_int_tx";
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@ -1263,6 +1308,7 @@ static int
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awg_setup_extres(device_t dev)
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{
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struct awg_softc *sc;
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phandle_t node;
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hwreset_t rst_ahb, rst_ephy;
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clk_t clk_ahb, clk_ephy;
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regulator_t reg;
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@ -1273,6 +1319,7 @@ awg_setup_extres(device_t dev)
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rst_ahb = rst_ephy = NULL;
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clk_ahb = clk_ephy = NULL;
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reg = NULL;
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node = ofw_bus_get_node(dev);
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/* Get AHB clock and reset resources */
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error = hwreset_get_by_ofw_name(dev, 0, "ahb", &rst_ahb);
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@ -1289,7 +1336,13 @@ awg_setup_extres(device_t dev)
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}
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if (clk_get_by_ofw_name(dev, 0, "ephy", &clk_ephy) != 0)
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clk_ephy = NULL;
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if (OF_hasprop(node, "syscon") && syscon_get_by_ofw_property(dev, node,
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"syscon", &sc->syscon) != 0) {
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device_printf(dev, "cannot get syscon driver handle\n");
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goto fail;
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}
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/* Configure PHY for MII or RGMII mode */
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if (awg_setup_phy(dev) != 0)
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goto fail;
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@ -69,6 +69,7 @@ device clk
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device phy
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device hwreset
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device regulator
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device syscon
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# CPU frequency control
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device cpufreq
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@ -235,6 +235,7 @@ device clk
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device phy
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device hwreset
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device regulator
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device syscon
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# The `bpf' device enables the Berkeley Packet Filter.
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# Be aware of the administrative consequences of enabling this!
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@ -59,7 +59,7 @@ arm/allwinner/clkng/ccu_a64.c optional aw_ccu fdt
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arm/allwinner/clkng/ccu_h3.c optional aw_ccu fdt
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arm/allwinner/clkng/ccu_sun8i_r.c optional aw_ccu fdt
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arm/allwinner/if_awg.c optional awg fdt
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arm/allwinner/if_awg.c optional awg ext_resources syscon fdt
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arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt
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arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt
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arm/annapurna/alpine/alpine_pci.c optional al_pci fdt
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