cxgbe(4): Make sure that the egress queue's cidx is updated periodically
when the driver is writing WRs using start_wrq_wr/commit_wrq_wr all the time. Sponsored by: Chelsio Communications
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parent
357405d985
commit
2e09fe9116
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=334132
@ -2367,9 +2367,29 @@ commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
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next = TAILQ_NEXT(cookie, link);
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if (prev == NULL) {
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MPASS(pidx == eq->dbidx);
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if (next == NULL || ndesc >= 16)
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if (next == NULL || ndesc >= 16) {
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int available;
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struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
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/*
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* Note that the WR via which we'll request tx updates
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* is at pidx and not eq->pidx, which has moved on
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* already.
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*/
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dst = (void *)&eq->desc[pidx];
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available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
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if (available < eq->sidx / 4 &&
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atomic_cmpset_int(&eq->equiq, 0, 1)) {
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dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
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F_FW_WR_EQUEQ);
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eq->equeqidx = pidx;
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} else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
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dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
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eq->equeqidx = pidx;
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}
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ring_eq_db(wrq->adapter, eq, ndesc);
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else {
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} else {
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MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
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next->pidx = pidx;
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next->ndesc += ndesc;
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