Add proper __sync_*() intrinsics for MIPS.
To make <stdatomic.h> work on MIPS (and ARM) using GCC, we need to provide implementations of the __sync_*() functions. I already added these functions for 4 and 8 byte types to libcompiler-rt some time ago, based on top of <machine/atomic.h>. Unfortunately, <machine/atomic.h> only provides a subset of the features needed to implement <stdatomic.h>. This means that in some cases we had to do compare-and-exchange calls in loops, where a simple ll/sc would suffice. Also implement these functions for 1 and 2 byte types. MIPS only provides ll/sc instructions for 4 and 8 byte types, but this is of course no limitation. We can simply load 4 bytes and use some bitmask tricks to modify only the bytes affected. Discussed on: mips, arch Tested with: QEMU
This commit is contained in:
Ed Schouten
parent
995d706909
commit
2e5d5dc936
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=251524
@ -35,6 +35,8 @@ mips/mips/pmap.c standard
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mips/mips/ptrace_machdep.c standard
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mips/mips/sc_machdep.c standard
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mips/mips/stack_machdep.c optional ddb | stack
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mips/mips/stdatomic.c standard \
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compile-with "${NORMAL_C:N-Wmissing-prototypes}"
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mips/mips/support.S standard
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mips/mips/swtch.S standard
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mips/mips/sys_machdep.c standard
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436
sys/mips/mips/stdatomic.c
Normal file
436
sys/mips/mips/stdatomic.c
Normal file
@ -0,0 +1,436 @@
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/*-
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* Copyright (c) 2013 Ed Schouten <ed@FreeBSD.org>
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* All rights reserved.
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*
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#ifdef _KERNEL
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#include "opt_global.h"
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#endif
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/*
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* Memory barriers.
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*
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* It turns out __sync_synchronize() does not emit any code when used
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* with GCC 4.2. Implement our own version that does work reliably.
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*
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* Although __sync_lock_test_and_set() should only perform an acquire
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* barrier, make it do a full barrier like the other functions. This
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* should make <stdatomic.h>'s atomic_exchange_explicit() work reliably.
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*/
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static inline void
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mips_sync(void)
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{
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__asm volatile (
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#if !defined(_KERNEL) || defined(SMP)
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".set noreorder\n"
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"\tsync\n"
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"\tnop\n"
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"\tnop\n"
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"\tnop\n"
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"\tnop\n"
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"\tnop\n"
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"\tnop\n"
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"\tnop\n"
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"\tnop\n"
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".set reorder\n"
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#else /* _KERNEL && !SMP */
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""
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#endif /* !KERNEL || SMP */
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: : : "memory");
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}
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typedef union {
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uint8_t v8[4];
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uint16_t v16[2];
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uint32_t v32;
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} reg_t;
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/*
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* 8-bit routines.
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*/
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uint8_t
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__sync_lock_test_and_set_1(uint8_t *mem8, uint8_t val8)
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{
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uint32_t *mem32;
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reg_t val32, negmask32, old;
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uint32_t temp;
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mem32 = (uint32_t *)((intptr_t)mem8 & ~3);
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val32.v32 = 0x00000000;
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val32.v8[(intptr_t)mem8 & 3] = val8;
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negmask32.v32 = 0xffffffff;
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negmask32.v8[(intptr_t)mem8 & 3] = 0x00;
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mips_sync();
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__asm volatile (
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"1:"
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"\tll %0, %5\n" /* Load old value. */
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"\tand %2, %4, %0\n" /* Trim out affected part. */
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"\tor %2, %3\n" /* Put in the new value. */
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"\tsc %2, %1\n" /* Attempt to store. */
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"\tbeqz %2, 1b\n" /* Spin if failed. */
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: "=&r" (old.v32), "=m" (*mem32), "=&r" (temp)
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: "r" (val32.v32), "r" (negmask32.v32), "m" (*mem32));
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return (old.v8[(intptr_t)mem8 & 3]);
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}
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uint8_t
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__sync_val_compare_and_swap_1(uint8_t *mem8, uint8_t expected, uint8_t desired)
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{
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uint32_t *mem32;
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reg_t expected32, desired32, posmask32, negmask32, old;
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uint32_t temp;
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mem32 = (uint32_t *)((intptr_t)mem8 & ~3);
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expected32.v32 = 0x00000000;
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expected32.v8[(intptr_t)mem8 & 3] = expected;
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desired32.v32 = 0x00000000;
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desired32.v8[(intptr_t)mem8 & 3] = desired;
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posmask32.v32 = 0x00000000;
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posmask32.v8[(intptr_t)mem8 & 3] = 0xff;
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negmask32.v32 = ~posmask32.v32;
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mips_sync();
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__asm volatile (
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"1:"
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"\tll %0, %7\n" /* Load old value. */
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"\tand %2, %5, %0\n" /* Isolate affected part. */
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"\tbne %2, %3, 2f\n" /* Compare to expected value. */
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"\tand %2, %6, %0\n" /* Trim out affected part. */
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"\tor %2, %4\n" /* Put in the new value. */
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"\tsc %2, %1\n" /* Attempt to store. */
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"\tbeqz %2, 1b\n" /* Spin if failed. */
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"2:"
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: "=&r" (old), "=m" (*mem32), "=&r" (temp)
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: "r" (expected32.v32), "r" (desired32.v32),
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"r" (posmask32.v32), "r" (negmask32.v32), "m" (*mem32));
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return (old.v8[(intptr_t)mem8 & 3]);
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}
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#define EMIT_ARITHMETIC_FETCH_AND_OP_1(name, op) \
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uint8_t \
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__sync_##name##_1(uint8_t *mem8, uint8_t val8) \
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{ \
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uint32_t *mem32; \
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reg_t val32, posmask32, negmask32, old; \
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uint32_t temp1, temp2; \
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\
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mem32 = (uint32_t *)((intptr_t)mem8 & ~3); \
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val32.v32 = 0x00000000; \
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val32.v8[(intptr_t)mem8 & 3] = val8; \
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posmask32.v32 = 0x00000000; \
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posmask32.v8[(intptr_t)mem8 & 3] = 0xff; \
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negmask32.v32 = ~posmask32.v32; \
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\
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mips_sync(); \
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__asm volatile ( \
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"1:" \
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"\tll %0, %7\n" /* Load old value. */ \
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"\t"op" %2, %0, %4\n" /* Calculate new value. */ \
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"\tand %2, %5\n" /* Isolate affected part. */ \
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"\tand %3, %6, %0\n" /* Trim out affected part. */ \
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"\tor %2, %3\n" /* Put in the new value. */ \
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"\tsc %2, %1\n" /* Attempt to store. */ \
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"\tbeqz %2, 1b\n" /* Spin if failed. */ \
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: "=&r" (old.v32), "=m" (*mem32), "=&r" (temp1), \
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"=&r" (temp2) \
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: "r" (val32.v32), "r" (posmask32.v32), \
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"r" (negmask32.v32), "m" (*mem32)); \
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return (old.v8[(intptr_t)mem8 & 3]); \
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}
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EMIT_ARITHMETIC_FETCH_AND_OP_1(fetch_and_add, "addu")
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EMIT_ARITHMETIC_FETCH_AND_OP_1(fetch_and_sub, "subu")
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#define EMIT_BITWISE_FETCH_AND_OP_1(name, op, idempotence) \
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uint8_t \
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__sync_##name##_1(uint8_t *mem8, uint8_t val8) \
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{ \
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uint32_t *mem32; \
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reg_t val32, old; \
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uint32_t temp; \
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\
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mem32 = (uint32_t *)((intptr_t)mem8 & ~3); \
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val32.v32 = idempotence ? 0xffffffff : 0x00000000; \
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val32.v8[(intptr_t)mem8 & 3] = val8; \
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\
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mips_sync(); \
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__asm volatile ( \
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"1:" \
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"\tll %0, %4\n" /* Load old value. */ \
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"\t"op" %2, %3, %0\n" /* Calculate new value. */ \
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"\tsc %2, %1\n" /* Attempt to store. */ \
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"\tbeqz %2, 1b\n" /* Spin if failed. */ \
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: "=&r" (old.v32), "=m" (*mem32), "=&r" (temp) \
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: "r" (val32.v32), "m" (*mem32)); \
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return (old.v8[(intptr_t)mem8 & 3]); \
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}
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EMIT_BITWISE_FETCH_AND_OP_1(fetch_and_and, "and", 1)
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EMIT_BITWISE_FETCH_AND_OP_1(fetch_and_or, "or", 0)
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EMIT_BITWISE_FETCH_AND_OP_1(fetch_and_xor, "xor", 0)
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/*
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* 16-bit routines.
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*/
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uint16_t
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__sync_lock_test_and_set_2(uint16_t *mem16, uint16_t val16)
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{
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uint32_t *mem32;
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reg_t val32, negmask32, old;
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uint32_t temp;
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mem32 = (uint32_t *)((intptr_t)mem16 & ~1);
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val32.v32 = 0x00000000;
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val32.v16[(intptr_t)mem16 & 1] = val16;
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negmask32.v32 = 0xffffffff;
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negmask32.v16[(intptr_t)mem16 & 1] = 0x0000;
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mips_sync();
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__asm volatile (
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"1:"
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"\tll %0, %5\n" /* Load old value. */
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"\tand %2, %4, %0\n" /* Trim out affected part. */
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"\tor %2, %3\n" /* Combine to new value. */
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"\tsc %2, %1\n" /* Attempt to store. */
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"\tbeqz %2, 1b\n" /* Spin if failed. */
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: "=&r" (old.v32), "=m" (*mem32), "=&r" (temp)
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: "r" (val32.v32), "r" (negmask32.v32), "m" (*mem32));
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return (old.v16[(intptr_t)mem16 & 1]);
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}
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uint16_t
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__sync_val_compare_and_swap_2(uint16_t *mem16, uint16_t expected,
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uint16_t desired)
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{
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uint32_t *mem32;
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reg_t expected32, desired32, posmask32, negmask32, old;
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uint32_t temp;
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mem32 = (uint32_t *)((intptr_t)mem16 & ~1);
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expected32.v32 = 0x00000000;
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expected32.v16[(intptr_t)mem16 & 1] = expected;
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desired32.v32 = 0x00000000;
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desired32.v16[(intptr_t)mem16 & 1] = desired;
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posmask32.v32 = 0x00000000;
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posmask32.v16[(intptr_t)mem16 & 1] = 0xffff;
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negmask32.v32 = ~posmask32.v32;
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mips_sync();
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__asm volatile (
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"1:"
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"\tll %0, %7\n" /* Load old value. */
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"\tand %2, %5, %0\n" /* Isolate affected part. */
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"\tbne %2, %3, 2f\n" /* Compare to expected value. */
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"\tand %2, %6, %0\n" /* Trim out affected part. */
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"\tor %2, %4\n" /* Put in the new value. */
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"\tsc %2, %1\n" /* Attempt to store. */
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"\tbeqz %2, 1b\n" /* Spin if failed. */
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"2:"
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: "=&r" (old), "=m" (*mem32), "=&r" (temp)
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: "r" (expected32.v32), "r" (desired32.v32),
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"r" (posmask32.v32), "r" (negmask32.v32), "m" (*mem32));
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return (old.v16[(intptr_t)mem16 & 1]);
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}
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#define EMIT_ARITHMETIC_FETCH_AND_OP_2(name, op) \
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uint16_t \
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__sync_##name##_2(uint16_t *mem16, uint16_t val16) \
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{ \
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uint32_t *mem32; \
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reg_t val32, posmask32, negmask32, old; \
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uint32_t temp1, temp2; \
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\
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mem32 = (uint32_t *)((intptr_t)mem16 & ~3); \
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val32.v32 = 0x00000000; \
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val32.v16[(intptr_t)mem16 & 1] = val16; \
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posmask32.v32 = 0x00000000; \
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posmask32.v16[(intptr_t)mem16 & 1] = 0xffff; \
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negmask32.v32 = ~posmask32.v32; \
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\
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mips_sync(); \
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__asm volatile ( \
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"1:" \
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"\tll %0, %7\n" /* Load old value. */ \
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"\t"op" %2, %0, %4\n" /* Calculate new value. */ \
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"\tand %2, %5\n" /* Isolate affected part. */ \
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"\tand %3, %6, %0\n" /* Trim out affected part. */ \
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"\tor %2, %3\n" /* Combine to new value. */ \
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"\tsc %2, %1\n" /* Attempt to store. */ \
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"\tbeqz %2, 1b\n" /* Spin if failed. */ \
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: "=&r" (old.v32), "=m" (*mem32), "=&r" (temp1), \
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"=&r" (temp2) \
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: "r" (val32.v32), "r" (posmask32.v32), \
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"r" (negmask32.v32), "m" (*mem32)); \
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return (old.v16[(intptr_t)mem16 & 1]); \
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}
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EMIT_ARITHMETIC_FETCH_AND_OP_2(fetch_and_add, "addu")
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EMIT_ARITHMETIC_FETCH_AND_OP_2(fetch_and_sub, "subu")
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#define EMIT_BITWISE_FETCH_AND_OP_2(name, op, idempotence) \
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uint16_t \
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__sync_##name##_2(uint16_t *mem16, uint16_t val16) \
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{ \
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uint32_t *mem32; \
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reg_t val32, old; \
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uint32_t temp; \
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\
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mem32 = (uint32_t *)((intptr_t)mem16 & ~1); \
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val32.v32 = idempotence ? 0xffffffff : 0x00000000; \
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val32.v16[(intptr_t)mem16 & 1] = val16; \
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\
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mips_sync(); \
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__asm volatile ( \
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"1:" \
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"\tll %0, %4\n" /* Load old value. */ \
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"\t"op" %2, %3, %0\n" /* Calculate new value. */ \
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"\tsc %2, %1\n" /* Attempt to store. */ \
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"\tbeqz %2, 1b\n" /* Spin if failed. */ \
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: "=&r" (old.v32), "=m" (*mem32), "=&r" (temp) \
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: "r" (val32.v32), "m" (*mem32)); \
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return (old.v16[(intptr_t)mem16 & 1]); \
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}
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EMIT_BITWISE_FETCH_AND_OP_2(fetch_and_and, "and", 1)
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EMIT_BITWISE_FETCH_AND_OP_2(fetch_and_or, "or", 0)
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EMIT_BITWISE_FETCH_AND_OP_2(fetch_and_xor, "xor", 0)
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/*
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* 32-bit routines.
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*/
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uint32_t
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__sync_val_compare_and_swap_4(uint32_t *mem, uint32_t expected,
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uint32_t desired)
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{
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uint32_t old, temp;
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mips_sync();
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__asm volatile (
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"1:"
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"\tll %0, %5\n" /* Load old value. */
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"\tbne %0, %3, 2f\n" /* Compare to expected value. */
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"\tmove %2, %4\n" /* Value to store. */
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"\tsc %2, %1\n" /* Attempt to store. */
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"\tbeqz %2, 1b\n" /* Spin if failed. */
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"2:"
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: "=&r" (old), "=m" (*mem), "=&r" (temp)
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: "r" (expected), "r" (desired), "m" (*mem));
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return (old);
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}
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#define EMIT_FETCH_AND_OP_4(name, op) \
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uint32_t \
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__sync_##name##_4(uint32_t *mem, uint32_t val) \
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{ \
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uint32_t old, temp; \
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\
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mips_sync(); \
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__asm volatile ( \
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"1:" \
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"\tll %0, %4\n" /* Load old value. */ \
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"\t"op"\n" /* Calculate new value. */ \
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"\tsc %2, %1\n" /* Attempt to store. */ \
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"\tbeqz %2, 1b\n" /* Spin if failed. */ \
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: "=&r" (old), "=m" (*mem), "=&r" (temp) \
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: "r" (val), "m" (*mem)); \
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return (old); \
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}
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|
||||
EMIT_FETCH_AND_OP_4(lock_test_and_set, "move %2, %3")
|
||||
EMIT_FETCH_AND_OP_4(fetch_and_add, "addu %2, %0, %3")
|
||||
EMIT_FETCH_AND_OP_4(fetch_and_and, "and %2, %0, %3")
|
||||
EMIT_FETCH_AND_OP_4(fetch_and_or, "or %2, %0, %3")
|
||||
EMIT_FETCH_AND_OP_4(fetch_and_sub, "subu %2, %0, %3")
|
||||
EMIT_FETCH_AND_OP_4(fetch_and_xor, "xor %2, %0, %3")
|
||||
|
||||
/*
|
||||
* 64-bit routines.
|
||||
*
|
||||
* Note: All the 64-bit atomic operations are only atomic when running
|
||||
* in 64-bit mode. It is assumed that code compiled for n32 and n64 fits
|
||||
* into this definition and no further safeties are needed.
|
||||
*/
|
||||
|
||||
#if defined(__mips_n32) || defined(__mips_n64)
|
||||
|
||||
uint64_t
|
||||
__sync_val_compare_and_swap_8(uint64_t *mem, uint64_t expected,
|
||||
uint64_t desired)
|
||||
{
|
||||
uint64_t old, temp;
|
||||
|
||||
mips_sync();
|
||||
__asm volatile (
|
||||
"1:"
|
||||
"\tlld %0, %5\n" /* Load old value. */
|
||||
"\tbne %0, %3, 2f\n" /* Compare to expected value. */
|
||||
"\tmove %2, %4\n" /* Value to store. */
|
||||
"\tscd %2, %1\n" /* Attempt to store. */
|
||||
"\tbeqz %2, 1b\n" /* Spin if failed. */
|
||||
"2:"
|
||||
: "=&r" (old), "=m" (*mem), "=&r" (temp)
|
||||
: "r" (expected), "r" (desired), "m" (*mem));
|
||||
return (old);
|
||||
}
|
||||
|
||||
#define EMIT_FETCH_AND_OP_8(name, op) \
|
||||
uint64_t \
|
||||
__sync_##name##_8(uint64_t *mem, uint64_t val) \
|
||||
{ \
|
||||
uint64_t old, temp; \
|
||||
\
|
||||
mips_sync(); \
|
||||
__asm volatile ( \
|
||||
"1:" \
|
||||
"\tlld %0, %4\n" /* Load old value. */ \
|
||||
"\t"op"\n" /* Calculate new value. */ \
|
||||
"\tscd %2, %1\n" /* Attempt to store. */ \
|
||||
"\tbeqz %2, 1b\n" /* Spin if failed. */ \
|
||||
: "=&r" (old), "=m" (*mem), "=&r" (temp) \
|
||||
: "r" (val), "m" (*mem)); \
|
||||
return (old); \
|
||||
}
|
||||
|
||||
EMIT_FETCH_AND_OP_8(lock_test_and_set, "move %2, %3")
|
||||
EMIT_FETCH_AND_OP_8(fetch_and_add, "daddu %2, %0, %3")
|
||||
EMIT_FETCH_AND_OP_8(fetch_and_and, "and %2, %0, %3")
|
||||
EMIT_FETCH_AND_OP_8(fetch_and_or, "or %2, %0, %3")
|
||||
EMIT_FETCH_AND_OP_8(fetch_and_sub, "dsubu %2, %0, %3")
|
||||
EMIT_FETCH_AND_OP_8(fetch_and_xor, "xor %2, %0, %3")
|
||||
|
||||
#endif /* __mips_n32 || __mips_n64 */
|
||||
Loading…
Reference in New Issue
Block a user