Add the driver for the SPI controller on ARMADA38X.
Tested on Clearfog (Pro) and SG-3100. Sponsored by: Rubicon Communications, LLC (Netgate)
This commit is contained in:
Luiz Otavio O Souza
parent
1c4ca77890
commit
2e82757c64
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=340432
@ -76,6 +76,11 @@ device iic
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device iicbus
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device twsi
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# SPI
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device spibus
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device spigen
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device mv_spi
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# Wireless NIC cards
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device wlan # 802.11 support
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device ath # Atheros NIC's
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@ -169,6 +169,7 @@ device aw_cir
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device spibus
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device spigen
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device bcm2835_spi
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device mv_spi
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device ti_spi
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# ADC support
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@ -18,6 +18,7 @@ arm/mv/armada38x/armada38x_mp.c optional smp
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arm/mv/armada38x/pmsu.c standard
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arm/mv/armada38x/armada38x_rtc.c standard
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arm/mv/armada38x/armada38x_pl310.c optional pl310
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arm/mv/mv_spi.c optional mv_spi spibus
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dev/sdhci/sdhci_fdt.c optional sdhci
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arm/mv/rtc.c standard
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351
sys/arm/mv/mv_spi.c
Normal file
351
sys/arm/mv/mv_spi.c
Normal file
@ -0,0 +1,351 @@
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/*-
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* Copyright (c) 2017-2018, Rubicon Communications, LLC (Netgate)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/intr.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/spibus/spi.h>
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#include <dev/spibus/spibusvar.h>
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#include "spibus_if.h"
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struct mv_spi_softc {
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device_t sc_dev;
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struct mtx sc_mtx;
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struct resource *sc_mem_res;
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struct resource *sc_irq_res;
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struct spi_command *sc_cmd;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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uint32_t sc_len;
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uint32_t sc_read;
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uint32_t sc_flags;
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uint32_t sc_written;
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void *sc_intrhand;
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};
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#define MV_SPI_BUSY 0x1
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#define MV_SPI_WRITE(_sc, _off, _val) \
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bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off), (_val))
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#define MV_SPI_READ(_sc, _off) \
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bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off))
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#define MV_SPI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define MV_SPI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define MV_SPI_CONTROL 0
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#define MV_SPI_CTRL_CS_SHIFT 2
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#define MV_SPI_CTRL_SMEMREADY (1 << 1)
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#define MV_SPI_CTRL_CS_ACTIVE (1 << 0)
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#define MV_SPI_CONF 0x4
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#define MV_SPI_CONF_BYTELEN (1 << 5)
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#define MV_SPI_DATAOUT 0x8
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#define MV_SPI_DATAIN 0xc
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#define MV_SPI_INTR_STAT 0x10
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#define MV_SPI_INTR_MASK 0x14
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#define MV_SPI_INTR_SMEMREADY (1 << 0)
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static struct ofw_compat_data compat_data[] = {
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{"marvell,armada-380-spi", 1},
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{NULL, 0}
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};
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static void mv_spi_intr(void *);
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static int
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mv_spi_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Marvell SPI controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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mv_spi_attach(device_t dev)
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{
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struct mv_spi_softc *sc;
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int rid;
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uint32_t reg;
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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rid = 0;
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sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (!sc->sc_mem_res) {
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device_printf(dev, "cannot allocate memory window\n");
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return (ENXIO);
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}
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sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
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sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
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rid = 0;
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sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE);
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if (!sc->sc_irq_res) {
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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device_printf(dev, "cannot allocate interrupt\n");
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return (ENXIO);
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}
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/* Deactivate the bus - just in case... */
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reg = MV_SPI_READ(sc, MV_SPI_CONTROL);
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MV_SPI_WRITE(sc, MV_SPI_CONTROL, reg & ~MV_SPI_CTRL_CS_ACTIVE);
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/* Disable the two bytes FIFO. */
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reg = MV_SPI_READ(sc, MV_SPI_CONF);
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MV_SPI_WRITE(sc, MV_SPI_CONF, reg & ~MV_SPI_CONF_BYTELEN);
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/* Clear and disable interrupts. */
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MV_SPI_WRITE(sc, MV_SPI_INTR_MASK, 0);
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MV_SPI_WRITE(sc, MV_SPI_INTR_STAT, 0);
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/* Hook up our interrupt handler. */
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if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, mv_spi_intr, sc, &sc->sc_intrhand)) {
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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device_printf(dev, "cannot setup the interrupt handler\n");
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return (ENXIO);
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}
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mtx_init(&sc->sc_mtx, "mv_spi", NULL, MTX_DEF);
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device_add_child(dev, "spibus", -1);
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/* Probe and attach the spibus when interrupts are available. */
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config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev);
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return (0);
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}
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static int
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mv_spi_detach(device_t dev)
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{
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struct mv_spi_softc *sc;
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bus_generic_detach(dev);
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sc = device_get_softc(dev);
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mtx_destroy(&sc->sc_mtx);
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if (sc->sc_intrhand)
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bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
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if (sc->sc_irq_res)
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
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if (sc->sc_mem_res)
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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return (0);
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}
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static __inline void
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mv_spi_rx_byte(struct mv_spi_softc *sc)
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{
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struct spi_command *cmd;
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uint32_t read;
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uint8_t *p;
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cmd = sc->sc_cmd;
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p = (uint8_t *)cmd->rx_cmd;
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read = sc->sc_read++;
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if (read >= cmd->rx_cmd_sz) {
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p = (uint8_t *)cmd->rx_data;
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read -= cmd->rx_cmd_sz;
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}
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p[read] = MV_SPI_READ(sc, MV_SPI_DATAIN) & 0xff;
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}
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static __inline void
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mv_spi_tx_byte(struct mv_spi_softc *sc)
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{
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struct spi_command *cmd;
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uint32_t written;
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uint8_t *p;
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cmd = sc->sc_cmd;
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p = (uint8_t *)cmd->tx_cmd;
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written = sc->sc_written++;
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if (written >= cmd->tx_cmd_sz) {
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p = (uint8_t *)cmd->tx_data;
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written -= cmd->tx_cmd_sz;
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}
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MV_SPI_WRITE(sc, MV_SPI_DATAOUT, p[written]);
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}
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static void
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mv_spi_intr(void *arg)
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{
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struct mv_spi_softc *sc;
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sc = (struct mv_spi_softc *)arg;
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MV_SPI_LOCK(sc);
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/* Filter stray interrupts. */
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if ((sc->sc_flags & MV_SPI_BUSY) == 0) {
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MV_SPI_UNLOCK(sc);
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return;
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}
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/* RX */
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mv_spi_rx_byte(sc);
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/* TX */
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mv_spi_tx_byte(sc);
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/* Check for end of transfer. */
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if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len)
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wakeup(sc->sc_dev);
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MV_SPI_UNLOCK(sc);
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}
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static int
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mv_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
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{
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struct mv_spi_softc *sc;
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uint32_t cs, reg;
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int resid, timeout;
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KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
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("TX/RX command sizes should be equal"));
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KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
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("TX/RX data sizes should be equal"));
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/* Get the proper chip select for this child. */
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spibus_get_cs(child, &cs);
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cs &= ~SPIBUS_CS_HIGH;
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sc = device_get_softc(dev);
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MV_SPI_LOCK(sc);
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/* Wait until the controller is free. */
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while (sc->sc_flags & MV_SPI_BUSY)
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mtx_sleep(dev, &sc->sc_mtx, 0, "mv_spi", 0);
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/* Now we have control over SPI controller. */
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sc->sc_flags = MV_SPI_BUSY;
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/* Save a pointer to the SPI command. */
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sc->sc_cmd = cmd;
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sc->sc_read = 0;
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sc->sc_written = 0;
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sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz;
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MV_SPI_WRITE(sc, MV_SPI_CONTROL, cs << MV_SPI_CTRL_CS_SHIFT);
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reg = MV_SPI_READ(sc, MV_SPI_CONTROL);
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MV_SPI_WRITE(sc, MV_SPI_CONTROL, reg | MV_SPI_CTRL_CS_ACTIVE);
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while ((resid = sc->sc_len - sc->sc_written) > 0) {
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MV_SPI_WRITE(sc, MV_SPI_INTR_STAT, 0);
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/*
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* Write to start the transmission and read the byte
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* back when ready.
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*/
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mv_spi_tx_byte(sc);
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timeout = 1000;
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while (--timeout > 0) {
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reg = MV_SPI_READ(sc, MV_SPI_CONTROL);
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if (reg & MV_SPI_CTRL_SMEMREADY)
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break;
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DELAY(1);
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}
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if (timeout == 0)
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break;
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mv_spi_rx_byte(sc);
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}
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/* Stop the controller. */
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reg = MV_SPI_READ(sc, MV_SPI_CONTROL);
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MV_SPI_WRITE(sc, MV_SPI_CONTROL, reg & ~MV_SPI_CTRL_CS_ACTIVE);
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MV_SPI_WRITE(sc, MV_SPI_INTR_MASK, 0);
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MV_SPI_WRITE(sc, MV_SPI_INTR_STAT, 0);
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/* Release the controller and wakeup the next thread waiting for it. */
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sc->sc_flags = 0;
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wakeup_one(dev);
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MV_SPI_UNLOCK(sc);
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/*
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* Check for transfer timeout. The SPI controller doesn't
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* return errors.
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*/
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return ((timeout == 0) ? EIO : 0);
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}
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static phandle_t
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mv_spi_get_node(device_t bus, device_t dev)
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{
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return (ofw_bus_get_node(bus));
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}
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static device_method_t mv_spi_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, mv_spi_probe),
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DEVMETHOD(device_attach, mv_spi_attach),
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DEVMETHOD(device_detach, mv_spi_detach),
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/* SPI interface */
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DEVMETHOD(spibus_transfer, mv_spi_transfer),
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/* ofw_bus interface */
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DEVMETHOD(ofw_bus_get_node, mv_spi_get_node),
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DEVMETHOD_END
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};
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static devclass_t mv_spi_devclass;
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static driver_t mv_spi_driver = {
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"spi",
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mv_spi_methods,
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sizeof(struct mv_spi_softc),
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};
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DRIVER_MODULE(mv_spi, simplebus, mv_spi_driver, mv_spi_devclass, 0, 0);
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