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[ar71xx] undo read-after-write to flush; some bus devices dislike this.

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This broke the PCI fixup on at least the AR7240 + AR9280 reference design
board that I have.

Tested:

* Atheros AP93 reference design - AR7240 + AR9280
This commit is contained in:
Adrian Chadd 2017-05-28 07:44:55 +00:00
parent ae442ee64a
commit 2e986d170b
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=319055
1 changed files with 7 additions and 6 deletions
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13
sys/mips/atheros/ar71xxreg.h
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@ -528,13 +528,14 @@ typedef enum {
#define AR71XX_SPI_RDS 0x0C
#define ATH_READ_REG(reg) \
*((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg)))
*((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg)))
/*
* Note: Don't put a flush read here; some users (eg the AR724x PCI fixup code)
* requires write-only space to certain registers. Doing the read afterwards
* causes things to break.
*/
#define ATH_WRITE_REG(reg, val) \
do { \
*((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) = (val); \
(void) ATH_READ_REG(reg); \
} while (0)
*((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) = (val)
static inline void
ar71xx_ddr_flush(uint32_t reg)