[ar71xx] undo read-after-write to flush; some bus devices dislike this.
This broke the PCI fixup on at least the AR7240 + AR9280 reference design board that I have. Tested: * Atheros AP93 reference design - AR7240 + AR9280
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=319055
@ -528,13 +528,14 @@ typedef enum {
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#define AR71XX_SPI_RDS 0x0C
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#define ATH_READ_REG(reg) \
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*((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg)))
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*((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg)))
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/*
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* Note: Don't put a flush read here; some users (eg the AR724x PCI fixup code)
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* requires write-only space to certain registers. Doing the read afterwards
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* causes things to break.
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*/
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#define ATH_WRITE_REG(reg, val) \
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do { \
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*((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) = (val); \
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(void) ATH_READ_REG(reg); \
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} while (0)
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*((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) = (val)
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static inline void
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ar71xx_ddr_flush(uint32_t reg)
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