Add a driver for Emulex OneConnect ethernet cards (10 Gbit PCIe)
A manpage will come in a future commit. Submitted by: Naresh Raju Gottumukkala (emulex)
This commit is contained in:
parent
9b4f251484
commit
2f345d8ed5
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=231437
@ -1972,6 +1972,7 @@ device xmphy # XaQti XMAC II
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# SMC EZ Card 1000 (SMC9462TX), D-Link DGE-500T, Asante FriendlyNet
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# GigaNIX 1000TA and 1000TPC, the Addtron AEG320T, the Surecom
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# EP-320G-TX and the Netgear GA622T.
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# oce: Emulex 10 Gbit adapters (OneConnect Ethernet)
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# pcn: Support for PCI fast ethernet adapters based on the AMD Am79c97x
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# PCnet-FAST, PCnet-FAST+, PCnet-FAST III, PCnet-PRO and PCnet-Home
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# chipsets. These can also be handled by the le(4) driver if the
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@ -2112,6 +2113,7 @@ device ixgbe # Intel Pro/10Gbe PCIE Ethernet
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device le # AMD Am7900 LANCE and Am79C9xx PCnet
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device mxge # Myricom Myri-10G 10GbE NIC
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device nxge # Neterion Xframe 10GbE Server/Storage Adapter
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device oce # Emulex 10 GbE (OneConnect Ethernet)
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device ti # Alteon Networks Tigon I/II gigabit Ethernet
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device txp # 3Com 3cR990 (``Typhoon'')
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device vx # 3Com 3c590, 3c595 (``Vortex'')
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@ -1068,6 +1068,12 @@ dev/e1000/e1000_mbx.c optional em | igb \
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compile-with "${NORMAL_C} -I$S/dev/e1000"
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dev/e1000/e1000_osdep.c optional em | igb \
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compile-with "${NORMAL_C} -I$S/dev/e1000"
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dev/oce/oce_hw.c optional oce pci
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dev/oce/oce_if.c optional oce pci
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dev/oce/oce_mbox.c optional oce pci
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dev/oce/oce_queue.c optional oce pci
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dev/oce/oce_sysctl.c optional oce pci
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dev/oce/oce_util.c optional oce pci
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dev/et/if_et.c optional et
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dev/en/if_en_pci.c optional en pci
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dev/en/midway.c optional en
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588
sys/dev/oce/oce_hw.c
Normal file
588
sys/dev/oce/oce_hw.c
Normal file
@ -0,0 +1,588 @@
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/*-
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* Copyright (C) 2012 Emulex
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the Emulex Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Contact Information:
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* freebsd-drivers@emulex.com
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*
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* Emulex
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* 3333 Susan Street
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* Costa Mesa, CA 92626
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*/
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/* $FreeBSD$ */
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#include "oce_if.h"
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static int oce_POST(POCE_SOFTC sc);
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/**
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* @brief Function to post status
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* @param sc software handle to the device
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*/
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static int
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oce_POST(POCE_SOFTC sc)
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{
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mpu_ep_semaphore_t post_status;
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int tmo = 60000;
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/* read semaphore CSR */
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post_status.dw0 = OCE_READ_REG32(sc, csr, MPU_EP_SEMAPHORE(sc));
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/* if host is ready then wait for fw ready else send POST */
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if (post_status.bits.stage <= POST_STAGE_AWAITING_HOST_RDY) {
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post_status.bits.stage = POST_STAGE_CHIP_RESET;
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OCE_WRITE_REG32(sc, csr, MPU_EP_SEMAPHORE(sc), post_status.dw0);
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}
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/* wait for FW ready */
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for (;;) {
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if (--tmo == 0)
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break;
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DELAY(1000);
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post_status.dw0 = OCE_READ_REG32(sc, csr, MPU_EP_SEMAPHORE(sc));
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if (post_status.bits.error) {
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device_printf(sc->dev,
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"POST failed: %x\n", post_status.dw0);
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return ENXIO;
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}
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if (post_status.bits.stage == POST_STAGE_ARMFW_READY)
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return 0;
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}
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device_printf(sc->dev, "POST timed out: %x\n", post_status.dw0);
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return ENXIO;
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}
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/**
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* @brief Function for hardware initialization
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* @param sc software handle to the device
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*/
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int
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oce_hw_init(POCE_SOFTC sc)
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{
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int rc = 0;
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rc = oce_POST(sc);
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if (rc)
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return rc;
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/* create the bootstrap mailbox */
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rc = oce_dma_alloc(sc, sizeof(struct oce_bmbx), &sc->bsmbx, 0);
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if (rc) {
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device_printf(sc->dev, "Mailbox alloc failed\n");
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return rc;
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}
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rc = oce_reset_fun(sc);
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if (rc)
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goto error;
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rc = oce_mbox_init(sc);
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if (rc)
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goto error;
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rc = oce_get_fw_version(sc);
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if (rc)
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goto error;
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rc = oce_get_fw_config(sc);
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if (rc)
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goto error;
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sc->macaddr.size_of_struct = 6;
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rc = oce_read_mac_addr(sc, 0, 1, MAC_ADDRESS_TYPE_NETWORK,
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&sc->macaddr);
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if (rc)
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goto error;
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if (IS_BE(sc) && (sc->flags & OCE_FLAGS_BE3)) {
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rc = oce_mbox_check_native_mode(sc);
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if (rc)
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goto error;
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} else
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sc->be3_native = 0;
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return rc;
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error:
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oce_dma_free(sc, &sc->bsmbx);
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device_printf(sc->dev, "Hardware initialisation failed\n");
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return rc;
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}
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/**
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* @brief Releases the obtained pci resources
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* @param sc software handle to the device
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*/
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void
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oce_hw_pci_free(POCE_SOFTC sc)
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{
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int pci_cfg_barnum = 0;
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if (IS_BE(sc) && (sc->flags & OCE_FLAGS_BE2))
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pci_cfg_barnum = OCE_DEV_BE2_CFG_BAR;
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else
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pci_cfg_barnum = OCE_DEV_CFG_BAR;
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if (sc->devcfg_res != NULL) {
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bus_release_resource(sc->dev,
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SYS_RES_MEMORY,
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PCIR_BAR(pci_cfg_barnum), sc->devcfg_res);
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sc->devcfg_res = (struct resource *)NULL;
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sc->devcfg_btag = (bus_space_tag_t) 0;
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sc->devcfg_bhandle = (bus_space_handle_t)0;
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sc->devcfg_vhandle = (void *)NULL;
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}
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if (sc->csr_res != NULL) {
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bus_release_resource(sc->dev,
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SYS_RES_MEMORY,
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PCIR_BAR(OCE_PCI_CSR_BAR), sc->csr_res);
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sc->csr_res = (struct resource *)NULL;
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sc->csr_btag = (bus_space_tag_t)0;
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sc->csr_bhandle = (bus_space_handle_t)0;
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sc->csr_vhandle = (void *)NULL;
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}
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if (sc->db_res != NULL) {
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bus_release_resource(sc->dev,
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SYS_RES_MEMORY,
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PCIR_BAR(OCE_PCI_DB_BAR), sc->db_res);
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sc->db_res = (struct resource *)NULL;
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sc->db_btag = (bus_space_tag_t)0;
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sc->db_bhandle = (bus_space_handle_t)0;
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sc->db_vhandle = (void *)NULL;
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}
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}
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/**
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* @brief Function to get the PCI capabilities
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* @param sc software handle to the device
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*/
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static
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void oce_get_pci_capabilities(POCE_SOFTC sc)
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{
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uint32_t val;
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if (pci_find_extcap(sc->dev, PCIY_PCIX, &val) == 0) {
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if (val != 0)
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sc->flags |= OCE_FLAGS_PCIX;
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}
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if (pci_find_extcap(sc->dev, PCIY_EXPRESS, &val) == 0) {
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if (val != 0) {
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uint16_t link_status =
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pci_read_config(sc->dev, val + 0x12, 2);
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sc->flags |= OCE_FLAGS_PCIE;
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sc->pcie_link_speed = link_status & 0xf;
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sc->pcie_link_width = (link_status >> 4) & 0x3f;
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}
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}
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if (pci_find_extcap(sc->dev, PCIY_MSI, &val) == 0) {
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if (val != 0)
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sc->flags |= OCE_FLAGS_MSI_CAPABLE;
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}
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if (pci_find_extcap(sc->dev, PCIY_MSIX, &val) == 0) {
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if (val != 0) {
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val = pci_msix_count(sc->dev);
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sc->flags |= OCE_FLAGS_MSIX_CAPABLE;
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}
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}
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}
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/**
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* @brief Allocate PCI resources.
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*
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* @param sc software handle to the device
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* @returns 0 if successful, or error
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*/
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int
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oce_hw_pci_alloc(POCE_SOFTC sc)
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{
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int rr, pci_cfg_barnum = 0;
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pci_sli_intf_t intf;
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pci_enable_busmaster(sc->dev);
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oce_get_pci_capabilities(sc);
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sc->fn = pci_get_function(sc->dev);
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/* setup the device config region */
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if (IS_BE(sc) && (sc->flags & OCE_FLAGS_BE2))
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pci_cfg_barnum = OCE_DEV_BE2_CFG_BAR;
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else
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pci_cfg_barnum = OCE_DEV_CFG_BAR;
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rr = PCIR_BAR(pci_cfg_barnum);
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if (IS_BE(sc))
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sc->devcfg_res = bus_alloc_resource_any(sc->dev,
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SYS_RES_MEMORY, &rr,
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RF_ACTIVE|RF_SHAREABLE);
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else
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sc->devcfg_res = bus_alloc_resource(sc->dev,
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SYS_RES_MEMORY, &rr,
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0ul, ~0ul, 32768,
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RF_ACTIVE|RF_SHAREABLE);
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if (!sc->devcfg_res)
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goto error;
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sc->devcfg_btag = rman_get_bustag(sc->devcfg_res);
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sc->devcfg_bhandle = rman_get_bushandle(sc->devcfg_res);
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sc->devcfg_vhandle = rman_get_virtual(sc->devcfg_res);
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/* Read the SLI_INTF register and determine whether we
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* can use this port and its features
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*/
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intf.dw0 = pci_read_config((sc)->dev,OCE_INTF_REG_OFFSET,4);
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if (intf.bits.sli_valid != OCE_INTF_VALID_SIG)
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goto error;
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if (intf.bits.sli_rev != OCE_INTF_SLI_REV4) {
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device_printf(sc->dev, "Adapter doesnt support SLI4\n");
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goto error;
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}
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if (intf.bits.sli_if_type == OCE_INTF_IF_TYPE_1)
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sc->flags |= OCE_FLAGS_MBOX_ENDIAN_RQD;
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if (intf.bits.sli_hint1 == OCE_INTF_FUNC_RESET_REQD)
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sc->flags |= OCE_FLAGS_FUNCRESET_RQD;
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if (intf.bits.sli_func_type == OCE_INTF_VIRT_FUNC)
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sc->flags |= OCE_FLAGS_VIRTUAL_PORT;
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/* Lancer has one BAR (CFG) but BE3 has three (CFG, CSR, DB) */
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if (IS_BE(sc)) {
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/* set up CSR region */
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rr = PCIR_BAR(OCE_PCI_CSR_BAR);
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sc->csr_res = bus_alloc_resource_any(sc->dev,
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SYS_RES_MEMORY, &rr, RF_ACTIVE|RF_SHAREABLE);
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if (!sc->csr_res)
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goto error;
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sc->csr_btag = rman_get_bustag(sc->csr_res);
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sc->csr_bhandle = rman_get_bushandle(sc->csr_res);
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sc->csr_vhandle = rman_get_virtual(sc->csr_res);
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/* set up DB doorbell region */
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rr = PCIR_BAR(OCE_PCI_DB_BAR);
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sc->db_res = bus_alloc_resource_any(sc->dev,
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SYS_RES_MEMORY, &rr, RF_ACTIVE|RF_SHAREABLE);
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if (!sc->db_res)
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goto error;
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sc->db_btag = rman_get_bustag(sc->db_res);
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sc->db_bhandle = rman_get_bushandle(sc->db_res);
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sc->db_vhandle = rman_get_virtual(sc->db_res);
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}
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return 0;
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error:
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oce_hw_pci_free(sc);
|
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return ENXIO;
|
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}
|
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|
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|
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/**
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* @brief Function for device shutdown
|
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* @param sc software handle to the device
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* @returns 0 on success, error otherwise
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*/
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void
|
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oce_hw_shutdown(POCE_SOFTC sc)
|
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{
|
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oce_stats_free(sc);
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/* disable hardware interrupts */
|
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oce_hw_intr_disable(sc);
|
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/* Free LRO resources */
|
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oce_free_lro(sc);
|
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/* Release queue*/
|
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oce_queue_release_all(sc);
|
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/*Delete Network Interface*/
|
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oce_delete_nw_interface(sc);
|
||||
/* After fw clean we dont send any cmds to fw.*/
|
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oce_fw_clean(sc);
|
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/* release intr resources */
|
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oce_intr_free(sc);
|
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/* release PCI resources */
|
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oce_hw_pci_free(sc);
|
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/* free mbox specific resources */
|
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LOCK_DESTROY(&sc->bmbx_lock);
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LOCK_DESTROY(&sc->dev_lock);
|
||||
|
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oce_dma_free(sc, &sc->bsmbx);
|
||||
}
|
||||
|
||||
|
||||
/**
|
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* @brief Function for creating nw interface.
|
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* @param sc software handle to the device
|
||||
* @returns 0 on success, error otherwise
|
||||
*/
|
||||
int
|
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oce_create_nw_interface(POCE_SOFTC sc)
|
||||
{
|
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int rc;
|
||||
uint32_t capab_flags;
|
||||
uint32_t capab_en_flags;
|
||||
|
||||
/* interface capabilities to give device when creating interface */
|
||||
capab_flags = OCE_CAPAB_FLAGS;
|
||||
|
||||
/* capabilities to enable by default (others set dynamically) */
|
||||
capab_en_flags = OCE_CAPAB_ENABLE;
|
||||
|
||||
if (IS_XE201(sc)) {
|
||||
/* LANCER A0 workaround */
|
||||
capab_en_flags &= ~MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR;
|
||||
capab_flags &= ~MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR;
|
||||
}
|
||||
|
||||
/* enable capabilities controlled via driver startup parameters */
|
||||
if (sc->rss_enable)
|
||||
capab_en_flags |= MBX_RX_IFACE_FLAGS_RSS;
|
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else {
|
||||
capab_en_flags &= ~MBX_RX_IFACE_FLAGS_RSS;
|
||||
capab_flags &= ~MBX_RX_IFACE_FLAGS_RSS;
|
||||
}
|
||||
|
||||
rc = oce_if_create(sc,
|
||||
capab_flags,
|
||||
capab_en_flags,
|
||||
0, &sc->macaddr.mac_addr[0], &sc->if_id);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
atomic_inc_32(&sc->nifs);
|
||||
|
||||
sc->if_cap_flags = capab_en_flags;
|
||||
|
||||
/* Enable VLAN Promisc on HW */
|
||||
rc = oce_config_vlan(sc, (uint8_t) sc->if_id, NULL, 0, 1, 1);
|
||||
if (rc)
|
||||
goto error;
|
||||
|
||||
/* set default flow control */
|
||||
rc = oce_set_flow_control(sc, sc->flow_control);
|
||||
if (rc)
|
||||
goto error;
|
||||
|
||||
rc = oce_rxf_set_promiscuous(sc, sc->promisc);
|
||||
if (rc)
|
||||
goto error;
|
||||
|
||||
return rc;
|
||||
|
||||
error:
|
||||
oce_delete_nw_interface(sc);
|
||||
return rc;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function to delete a nw interface.
|
||||
* @param sc software handle to the device
|
||||
*/
|
||||
void
|
||||
oce_delete_nw_interface(POCE_SOFTC sc)
|
||||
{
|
||||
/* currently only single interface is implmeneted */
|
||||
if (sc->nifs > 0) {
|
||||
oce_if_del(sc, sc->if_id);
|
||||
atomic_dec_32(&sc->nifs);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Soft reset.
|
||||
* @param sc software handle to the device
|
||||
* @returns 0 on success, error otherwise
|
||||
*/
|
||||
int
|
||||
oce_pci_soft_reset(POCE_SOFTC sc)
|
||||
{
|
||||
int rc;
|
||||
mpu_ep_control_t ctrl;
|
||||
|
||||
ctrl.dw0 = OCE_READ_REG32(sc, csr, MPU_EP_CONTROL);
|
||||
ctrl.bits.cpu_reset = 1;
|
||||
OCE_WRITE_REG32(sc, csr, MPU_EP_CONTROL, ctrl.dw0);
|
||||
DELAY(50);
|
||||
rc=oce_POST(sc);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for hardware start
|
||||
* @param sc software handle to the device
|
||||
* @returns 0 on success, error otherwise
|
||||
*/
|
||||
int
|
||||
oce_hw_start(POCE_SOFTC sc)
|
||||
{
|
||||
struct link_status link = { 0 };
|
||||
int rc = 0;
|
||||
|
||||
rc = oce_get_link_status(sc, &link);
|
||||
if (rc)
|
||||
return 1;
|
||||
|
||||
if (link.logical_link_status == NTWK_LOGICAL_LINK_UP) {
|
||||
sc->ifp->if_drv_flags |= IFF_DRV_RUNNING;
|
||||
sc->link_status = NTWK_LOGICAL_LINK_UP;
|
||||
if_link_state_change(sc->ifp, LINK_STATE_UP);
|
||||
} else {
|
||||
sc->ifp->if_drv_flags &=
|
||||
~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
|
||||
sc->link_status = NTWK_LOGICAL_LINK_DOWN;
|
||||
if_link_state_change(sc->ifp, LINK_STATE_DOWN);
|
||||
}
|
||||
|
||||
if (link.mac_speed > 0 && link.mac_speed < 5)
|
||||
sc->link_speed = link.mac_speed;
|
||||
else
|
||||
sc->link_speed = 0;
|
||||
|
||||
sc->qos_link_speed = (uint32_t )link.qos_link_speed * 10;
|
||||
|
||||
rc = oce_start_mq(sc->mq);
|
||||
|
||||
/* we need to get MCC aync events.
|
||||
So enable intrs and also arm first EQ
|
||||
*/
|
||||
oce_hw_intr_enable(sc);
|
||||
oce_arm_eq(sc, sc->eq[0]->eq_id, 0, TRUE, FALSE);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for hardware enable interupts.
|
||||
* @param sc software handle to the device
|
||||
*/
|
||||
void
|
||||
oce_hw_intr_enable(POCE_SOFTC sc)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL);
|
||||
reg |= HOSTINTR_MASK;
|
||||
OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for hardware disable interupts
|
||||
* @param sc software handle to the device
|
||||
*/
|
||||
void
|
||||
oce_hw_intr_disable(POCE_SOFTC sc)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL);
|
||||
reg &= ~HOSTINTR_MASK;
|
||||
OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for hardware update multicast filter
|
||||
* @param sc software handle to the device
|
||||
*/
|
||||
int
|
||||
oce_hw_update_multicast(POCE_SOFTC sc)
|
||||
{
|
||||
struct ifnet *ifp = sc->ifp;
|
||||
struct ifmultiaddr *ifma;
|
||||
struct mbx_set_common_iface_multicast *req = NULL;
|
||||
OCE_DMA_MEM dma;
|
||||
int rc = 0;
|
||||
|
||||
/* Allocate DMA mem*/
|
||||
if (oce_dma_alloc(sc, sizeof(struct mbx_set_common_iface_multicast),
|
||||
&dma, 0))
|
||||
return ENOMEM;
|
||||
|
||||
req = OCE_DMAPTR(&dma, struct mbx_set_common_iface_multicast);
|
||||
bzero(req, sizeof(struct mbx_set_common_iface_multicast));
|
||||
|
||||
#if __FreeBSD_version > 800000
|
||||
IF_ADDR_LOCK(ifp);
|
||||
#endif
|
||||
TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
|
||||
if (ifma->ifma_addr->sa_family != AF_LINK)
|
||||
continue;
|
||||
|
||||
if (req->params.req.num_mac == OCE_MAX_MC_FILTER_SIZE) {
|
||||
/*More multicast addresses than our hardware table
|
||||
So Enable multicast promiscus in our hardware to
|
||||
accept all multicat packets
|
||||
*/
|
||||
req->params.req.promiscuous = 1;
|
||||
break;
|
||||
}
|
||||
bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
|
||||
&req->params.req.mac[req->params.req.num_mac],
|
||||
ETH_ADDR_LEN);
|
||||
req->params.req.num_mac = req->params.req.num_mac + 1;
|
||||
}
|
||||
#if __FreeBSD_version > 800000
|
||||
IF_ADDR_UNLOCK(ifp);
|
||||
#endif
|
||||
req->params.req.if_id = sc->if_id;
|
||||
rc = oce_update_multicast(sc, &dma);
|
||||
oce_dma_free(sc, &dma);
|
||||
return rc;
|
||||
}
|
||||
|
3381
sys/dev/oce/oce_hw.h
Normal file
3381
sys/dev/oce/oce_hw.h
Normal file
File diff suppressed because it is too large
Load Diff
2000
sys/dev/oce/oce_if.c
Normal file
2000
sys/dev/oce/oce_if.c
Normal file
File diff suppressed because it is too large
Load Diff
1071
sys/dev/oce/oce_if.h
Normal file
1071
sys/dev/oce/oce_if.h
Normal file
File diff suppressed because it is too large
Load Diff
1705
sys/dev/oce/oce_mbox.c
Normal file
1705
sys/dev/oce/oce_mbox.c
Normal file
File diff suppressed because it is too large
Load Diff
1213
sys/dev/oce/oce_queue.c
Normal file
1213
sys/dev/oce/oce_queue.c
Normal file
File diff suppressed because it is too large
Load Diff
1300
sys/dev/oce/oce_sysctl.c
Normal file
1300
sys/dev/oce/oce_sysctl.c
Normal file
File diff suppressed because it is too large
Load Diff
270
sys/dev/oce/oce_util.c
Normal file
270
sys/dev/oce/oce_util.c
Normal file
@ -0,0 +1,270 @@
|
||||
/*-
|
||||
* Copyright (C) 2012 Emulex
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the Emulex Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Contact Information:
|
||||
* freebsd-drivers@emulex.com
|
||||
*
|
||||
* Emulex
|
||||
* 3333 Susan Street
|
||||
* Costa Mesa, CA 92626
|
||||
*/
|
||||
|
||||
|
||||
/* $FreeBSD$ */
|
||||
|
||||
|
||||
#include "oce_if.h"
|
||||
|
||||
static void oce_dma_map_ring(void *arg,
|
||||
bus_dma_segment_t *segs,
|
||||
int nseg,
|
||||
int error);
|
||||
|
||||
/**
|
||||
* @brief Allocate DMA memory
|
||||
* @param sc software handle to the device
|
||||
* @param size bus size
|
||||
* @param dma dma memory area
|
||||
* @param flags creation flags
|
||||
* @returns 0 on success, error otherwize
|
||||
*/
|
||||
int
|
||||
oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags)
|
||||
{
|
||||
int rc;
|
||||
|
||||
|
||||
memset(dma, 0, sizeof(OCE_DMA_MEM));
|
||||
|
||||
rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev),
|
||||
8, 0,
|
||||
BUS_SPACE_MAXADDR,
|
||||
BUS_SPACE_MAXADDR,
|
||||
NULL, NULL,
|
||||
size, 1, size, 0, NULL, NULL, &dma->tag);
|
||||
|
||||
if (rc == 0) {
|
||||
rc = bus_dmamem_alloc(dma->tag,
|
||||
&dma->ptr,
|
||||
BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
|
||||
&dma->map);
|
||||
}
|
||||
|
||||
dma->paddr = 0;
|
||||
if (rc == 0) {
|
||||
rc = bus_dmamap_load(dma->tag,
|
||||
dma->map,
|
||||
dma->ptr,
|
||||
size,
|
||||
oce_dma_map_addr,
|
||||
&dma->paddr, flags | BUS_DMA_NOWAIT);
|
||||
if (dma->paddr == 0)
|
||||
rc = ENXIO;
|
||||
}
|
||||
|
||||
if (rc != 0)
|
||||
oce_dma_free(sc, dma);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Free DMA memory
|
||||
* @param sc software handle to the device
|
||||
* @param dma dma area to free
|
||||
*/
|
||||
void
|
||||
oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma)
|
||||
{
|
||||
if (dma->tag == NULL)
|
||||
return;
|
||||
|
||||
if (dma->map != NULL) {
|
||||
bus_dmamap_sync(dma->tag, dma->map,
|
||||
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
|
||||
bus_dmamap_unload(dma->tag, dma->map);
|
||||
}
|
||||
|
||||
if (dma->ptr != NULL) {
|
||||
bus_dmamem_free(dma->tag, dma->ptr, dma->map);
|
||||
dma->map = NULL;
|
||||
dma->ptr = NULL;
|
||||
}
|
||||
|
||||
bus_dma_tag_destroy(dma->tag);
|
||||
dma->tag = NULL;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Map DMA memory segment addresses
|
||||
* @param arg physical address pointer
|
||||
* @param segs dma memory segments
|
||||
* @param nseg number of dma memory segments
|
||||
* @param error if error, zeroes the physical address
|
||||
*/
|
||||
void
|
||||
oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error)
|
||||
{
|
||||
bus_addr_t *paddr = arg;
|
||||
|
||||
if (error)
|
||||
*paddr = 0;
|
||||
else
|
||||
*paddr = segs->ds_addr;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Destroy a ring buffer
|
||||
* @param sc software handle to the device
|
||||
* @param ring ring buffer
|
||||
*/
|
||||
|
||||
void
|
||||
oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring)
|
||||
{
|
||||
oce_dma_free(sc, &ring->dma);
|
||||
free(ring, M_DEVBUF);
|
||||
}
|
||||
|
||||
|
||||
|
||||
oce_ring_buffer_t *
|
||||
oce_create_ring_buffer(POCE_SOFTC sc,
|
||||
uint32_t q_len, uint32_t item_size)
|
||||
{
|
||||
uint32_t size = q_len * item_size;
|
||||
int rc;
|
||||
oce_ring_buffer_t *ring;
|
||||
|
||||
|
||||
ring = malloc(sizeof(oce_ring_buffer_t), M_DEVBUF, M_NOWAIT | M_ZERO);
|
||||
if (ring == NULL)
|
||||
return NULL;
|
||||
|
||||
ring->item_size = item_size;
|
||||
ring->num_items = q_len;
|
||||
|
||||
rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev),
|
||||
4096, 0,
|
||||
BUS_SPACE_MAXADDR,
|
||||
BUS_SPACE_MAXADDR,
|
||||
NULL, NULL,
|
||||
size, 8, 4096, 0, NULL, NULL, &ring->dma.tag);
|
||||
if (rc)
|
||||
goto fail;
|
||||
|
||||
|
||||
rc = bus_dmamem_alloc(ring->dma.tag,
|
||||
&ring->dma.ptr,
|
||||
BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
|
||||
&ring->dma.map);
|
||||
if (rc)
|
||||
goto fail;
|
||||
|
||||
bzero(ring->dma.ptr, size);
|
||||
bus_dmamap_sync(ring->dma.tag, ring->dma.map,
|
||||
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
|
||||
ring->dma.paddr = 0;
|
||||
|
||||
return ring;
|
||||
|
||||
fail:
|
||||
oce_dma_free(sc, &ring->dma);
|
||||
free(ring, M_DEVBUF);
|
||||
ring = NULL;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
||||
|
||||
struct _oce_dmamap_paddr_table {
|
||||
uint32_t max_entries;
|
||||
uint32_t num_entries;
|
||||
struct phys_addr *paddrs;
|
||||
};
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Map ring buffer
|
||||
* @param arg dma map phyical address table pointer
|
||||
* @param segs dma memory segments
|
||||
* @param nseg number of dma memory segments
|
||||
* @param error maps only if error is 0
|
||||
*/
|
||||
static void
|
||||
oce_dma_map_ring(void *arg, bus_dma_segment_t * segs, int nseg, int error)
|
||||
{
|
||||
int i;
|
||||
struct _oce_dmamap_paddr_table *dpt =
|
||||
(struct _oce_dmamap_paddr_table *)arg;
|
||||
|
||||
if (error == 0) {
|
||||
if (nseg <= dpt->max_entries) {
|
||||
for (i = 0; i < nseg; i++) {
|
||||
dpt->paddrs[i].lo = ADDR_LO(segs[i].ds_addr);
|
||||
dpt->paddrs[i].hi = ADDR_HI(segs[i].ds_addr);
|
||||
}
|
||||
dpt->num_entries = nseg;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Load bus dma map for a ring buffer
|
||||
* @param ring ring buffer pointer
|
||||
* @param pa_list physical address list
|
||||
* @returns number entries
|
||||
*/
|
||||
uint32_t
|
||||
oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list)
|
||||
{
|
||||
struct _oce_dmamap_paddr_table dpt;
|
||||
|
||||
dpt.max_entries = 8;
|
||||
dpt.num_entries = 0;
|
||||
dpt.paddrs = pa_list;
|
||||
|
||||
bus_dmamap_load(ring->dma.tag,
|
||||
ring->dma.map,
|
||||
ring->dma.ptr,
|
||||
ring->item_size * ring->num_items,
|
||||
oce_dma_map_ring, &dpt, BUS_DMA_NOWAIT);
|
||||
|
||||
return dpt.num_entries;
|
||||
}
|
@ -240,6 +240,7 @@ SUBDIR= ${_3dfx} \
|
||||
${_nwfs} \
|
||||
${_nxge} \
|
||||
${_opensolaris} \
|
||||
oce \
|
||||
${_padlock} \
|
||||
patm \
|
||||
${_pccard} \
|
||||
|
15
sys/modules/oce/Makefile
Normal file
15
sys/modules/oce/Makefile
Normal file
@ -0,0 +1,15 @@
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
.PATH: ${.CURDIR}/../../dev/oce
|
||||
KMOD = oce
|
||||
SRCS = oce_if.c oce_hw.c oce_mbox.c oce_util.c oce_queue.c oce_sysctl.c
|
||||
#SRCS += ${ofw_bus_if} bus_if.h device_if.h pci_if.h opt_inet.h opt_inet6.h
|
||||
|
||||
CFLAGS+= -I${.CURDIR}/../../dev/oce -DSMP
|
||||
|
||||
# uncomment for lock profiling statistics
|
||||
#CFLAGS += -DLOCK_PROFILING
|
||||
|
||||
.include <bsd.kmod.mk>
|
Loading…
Reference in New Issue
Block a user