Optimize Armada38x low-level MBUS settings
Add early init handler, which comprises various internal bus optimisations for Armada 38x SoC's. Magic values used due to undocumented registers. Submitted by: Marcin Wojtas <mw@semihalf.com>, Arnaud Ysmal <arnaud.ysmal@stormshield.eu> Obtained from: Semihalf, Stormshield Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D10219
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=317090
@ -41,6 +41,7 @@ __FBSDID("$FreeBSD$");
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int armada38x_open_bootrom_win(void);
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int armada38x_scu_enable(void);
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int armada38x_win_set_iosync_barrier(void);
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int armada38x_mbus_optimization(void);
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uint32_t
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get_tclk(void)
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@ -114,6 +115,50 @@ armada38x_open_bootrom_win(void)
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return (rv);
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}
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int
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armada38x_mbus_optimization(void)
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{
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bus_space_handle_t vaddr_iowind;
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int rv;
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rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_CTRL_BASE,
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MV_MBUS_CTRL_REGS_LEN, 0, &vaddr_iowind);
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if (rv != 0)
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return (rv);
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/*
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* MBUS Units Priority Control Register - Prioritize XOR,
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* PCIe and GbEs (ID=4,6,3,7,8) DRAM access
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* GbE is High and others are Medium.
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*/
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bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0, 0x19180);
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/*
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* Fabric Units Priority Control Register -
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* Prioritize CPUs requests.
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*/
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bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0x4, 0x3000A);
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/*
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* MBUS Units Prefetch Control Register -
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* Pre-fetch enable for all IO masters.
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*/
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bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0x8, 0xFFFF);
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/*
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* Fabric Units Prefetch Control Register -
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* Enable the CPUs Instruction and Data prefetch.
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*/
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bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0xc, 0x303);
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bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, MV_MBUS_CTRL_REGS_LEN,
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BUS_SPACE_BARRIER_WRITE);
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bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_MBUS_CTRL_REGS_LEN);
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return (rv);
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}
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int
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armada38x_scu_enable(void)
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{
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@ -77,6 +77,7 @@ void armadaxp_l2_init(void);
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int armada38x_win_set_iosync_barrier(void);
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int armada38x_scu_enable(void);
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int armada38x_open_bootrom_win(void);
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int armada38x_mbus_optimization(void);
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#endif
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#define MPP_PIN_MAX 68
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@ -259,6 +260,8 @@ platform_late_init(void)
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/* Set IO Sync Barrier bit for all Mbus devices */
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if (armada38x_win_set_iosync_barrier() != 0)
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printf("WARNING: could not map CPU Subsystem registers\n");
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if (armada38x_mbus_optimization() != 0)
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printf("WARNING: could not enable mbus optimization\n");
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if (armada38x_scu_enable() != 0)
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printf("WARNING: could not enable SCU\n");
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#ifdef SMP
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@ -447,4 +447,9 @@
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#define CPU_RESET_ASSERT 0x1
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#endif
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#if defined(SOC_MV_ARMADA38X)
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#define MV_MBUS_CTRL_BASE (MV_BASE + 0x20420)
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#define MV_MBUS_CTRL_REGS_LEN 0x10
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#endif
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#endif /* _MVREG_H_ */
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