Revert last commit, to remove added skeleton tree.
This commit is contained in:
parent
2533e32559
commit
3012653750
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=283882
File diff suppressed because it is too large
Load Diff
@ -43,7 +43,7 @@
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/*********************************************************************
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* Driver version
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*********************************************************************/
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char ixv_driver_version[] = "1.4.0";
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char ixv_driver_version[] = "1.2.5";
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/*********************************************************************
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* PCI Device ID Table
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@ -151,10 +151,6 @@ MODULE_DEPEND(ixv, ether, 1, 1, 1);
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** TUNEABLE PARAMETERS:
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*/
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/* Number of Queues - do not exceed MSIX vectors - 1 */
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static int ixv_num_queues = 1;
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TUNABLE_INT("hw.ixv.num_queues", &ixv_num_queues);
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/*
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** AIM: Adaptive Interrupt Moderation
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** which means that the interrupt rate
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@ -342,11 +338,6 @@ ixv_attach(device_t dev)
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ixgbe_reset_hw(hw);
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/* Get the Mailbox API version */
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device_printf(dev,"MBX API %d negotiation: %d\n",
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ixgbe_mbox_api_11,
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ixgbevf_negotiate_api_version(hw, ixgbe_mbox_api_11));
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error = ixgbe_init_hw(hw);
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if (error) {
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device_printf(dev,"Hardware Initialization Failure\n");
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@ -1322,13 +1313,10 @@ static int
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ixv_setup_msix(struct adapter *adapter)
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{
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device_t dev = adapter->dev;
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int rid, want, msgs;
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int rid, want;
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/* Must have at least 2 MSIX vectors */
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msgs = pci_msix_count(dev);
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if (msgs < 2)
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goto out;
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/* First try MSI/X */
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rid = PCIR_BAR(3);
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adapter->msix_mem = bus_alloc_resource_any(dev,
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SYS_RES_MEMORY, &rid, RF_ACTIVE);
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@ -1339,16 +1327,11 @@ ixv_setup_msix(struct adapter *adapter)
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}
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/*
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** Want vectors for the queues,
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** Want two vectors: one for a queue,
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** plus an additional for mailbox.
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*/
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want = adapter->num_queues + 1;
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if (want > msgs) {
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want = msgs;
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adapter->num_queues = msgs - 1;
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} else
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msgs = want;
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if ((pci_alloc_msix(dev, &msgs) == 0) && (msgs == want)) {
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want = 2;
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if ((pci_alloc_msix(dev, &want) == 0) && (want == 2)) {
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device_printf(adapter->dev,
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"Using MSIX interrupts with %d vectors\n", want);
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return (want);
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@ -1387,9 +1370,7 @@ ixv_allocate_pci_resources(struct adapter *adapter)
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rman_get_bushandle(adapter->pci_mem);
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adapter->hw.hw_addr = (u8 *) &adapter->osdep.mem_bus_space_handle;
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/* Pick up the tuneable queues */
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adapter->num_queues = ixv_num_queues;
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adapter->num_queues = 1;
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adapter->hw.back = &adapter->osdep;
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/*
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@ -1610,41 +1591,32 @@ ixv_initialize_receive_units(struct adapter *adapter)
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{
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struct rx_ring *rxr = adapter->rx_rings;
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struct ixgbe_hw *hw = &adapter->hw;
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struct ifnet *ifp = adapter->ifp;
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u32 bufsz, rxcsum, psrtype;
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int max_frame;
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struct ifnet *ifp = adapter->ifp;
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u32 bufsz, fctrl, rxcsum, hlreg;
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if (ifp->if_mtu > ETHERMTU)
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/* Enable broadcasts */
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fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
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fctrl |= IXGBE_FCTRL_BAM;
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fctrl |= IXGBE_FCTRL_DPF;
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fctrl |= IXGBE_FCTRL_PMCF;
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IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
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/* Set for Jumbo Frames? */
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hlreg = IXGBE_READ_REG(hw, IXGBE_HLREG0);
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if (ifp->if_mtu > ETHERMTU) {
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hlreg |= IXGBE_HLREG0_JUMBOEN;
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bufsz = 4096 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
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else
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} else {
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hlreg &= ~IXGBE_HLREG0_JUMBOEN;
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bufsz = 2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
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psrtype = IXGBE_PSRTYPE_TCPHDR | IXGBE_PSRTYPE_UDPHDR |
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IXGBE_PSRTYPE_IPV4HDR | IXGBE_PSRTYPE_IPV6HDR |
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IXGBE_PSRTYPE_L2HDR;
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IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
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/* Tell PF our expected packet-size */
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max_frame = ifp->if_mtu + IXGBE_MTU_HDR;
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ixgbevf_rlpml_set_vf(hw, max_frame);
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}
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IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg);
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for (int i = 0; i < adapter->num_queues; i++, rxr++) {
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u64 rdba = rxr->rxdma.dma_paddr;
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u32 reg, rxdctl;
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/* Disable the queue */
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rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
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rxdctl &= ~(IXGBE_RXDCTL_ENABLE | IXGBE_RXDCTL_VME);
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IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
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for (int j = 0; j < 10; j++) {
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if (IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i)) &
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IXGBE_RXDCTL_ENABLE)
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msec_delay(1);
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else
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break;
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}
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wmb();
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/* Setup the Base and Length of the Rx Descriptor Ring */
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IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
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(rdba & 0x00000000ffffffffULL));
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@ -1653,10 +1625,6 @@ ixv_initialize_receive_units(struct adapter *adapter)
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IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
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adapter->num_rx_desc * sizeof(union ixgbe_adv_rx_desc));
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/* Reset the ring indices */
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IXGBE_WRITE_REG(hw, IXGBE_VFRDH(rxr->me), 0);
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IXGBE_WRITE_REG(hw, IXGBE_VFRDT(rxr->me), 0);
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/* Set up the SRRCTL register */
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reg = IXGBE_READ_REG(hw, IXGBE_VFSRRCTL(i));
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reg &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
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@ -1665,14 +1633,14 @@ ixv_initialize_receive_units(struct adapter *adapter)
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reg |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
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IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), reg);
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/* Set the Tail Pointer */
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/* Setup the HW Rx Head and Tail Descriptor Pointers */
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IXGBE_WRITE_REG(hw, IXGBE_VFRDH(rxr->me), 0);
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IXGBE_WRITE_REG(hw, IXGBE_VFRDT(rxr->me),
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adapter->num_rx_desc - 1);
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/* Set the processing limit */
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rxr->process_limit = ixv_rx_process_limit;
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/* Capture Rx Tail index */
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/* Set Rx Tail register */
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rxr->tail = IXGBE_VFRDT(rxr->me);
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/* Do the queue enabling last */
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@ -2065,7 +2033,9 @@ ixv_add_stats_sysctls(struct adapter *adapter)
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SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_packets",
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CTLFLAG_RD, &(txr->total_packets),
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"TX Packets");
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SYSCTL_ADD_UINT(ctx, queue_list, OID_AUTO, "tx_bytes",
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CTLFLAG_RD, &(txr->bytes), 0,
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"TX Bytes");
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SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_no_desc",
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CTLFLAG_RD, &(txr->no_desc_avail),
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"# of times not enough descriptors were available during TX");
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@ -578,6 +578,7 @@ ixgbe_setup_transmit_ring(struct tx_ring *txr)
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{
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struct adapter *adapter = txr->adapter;
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struct ixgbe_tx_buf *txbuf;
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int i;
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#ifdef DEV_NETMAP
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struct netmap_adapter *na = NA(adapter->ifp);
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struct netmap_slot *slot;
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@ -600,7 +601,7 @@ ixgbe_setup_transmit_ring(struct tx_ring *txr)
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/* Free any existing tx buffers. */
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txbuf = txr->tx_buffers;
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for (int i = 0; i < txr->num_desc; i++, txbuf++) {
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for (i = 0; i < txr->num_desc; i++, txbuf++) {
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if (txbuf->m_head != NULL) {
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bus_dmamap_sync(txr->txtag, txbuf->map,
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BUS_DMASYNC_POSTWRITE);
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@ -621,8 +622,7 @@ ixgbe_setup_transmit_ring(struct tx_ring *txr)
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*/
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if (slot) {
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int si = netmap_idx_n2k(&na->tx_rings[txr->me], i);
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netmap_load_map(na, txr->txtag,
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txbuf->map, NMB(na, slot + si));
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netmap_load_map(na, txr->txtag, txbuf->map, NMB(na, slot + si));
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}
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#endif /* DEV_NETMAP */
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/* Clear the EOP descriptor pointer */
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@ -777,7 +777,8 @@ ixgbe_tx_ctx_setup(struct tx_ring *txr, struct mbuf *mp,
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if (mp->m_flags & M_VLANTAG) {
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vtag = htole16(mp->m_pkthdr.ether_vtag);
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vlan_macip_lens |= (vtag << IXGBE_ADVTXD_VLAN_SHIFT);
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} else if (!IXGBE_IS_X550VF(adapter) && (offload == FALSE))
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}
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else if (!IXGBE_IS_X550VF(adapter) && (offload == FALSE))
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return (0);
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/*
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@ -1378,7 +1379,7 @@ ixgbe_allocate_receive_buffers(struct rx_ring *rxr)
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struct adapter *adapter = rxr->adapter;
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device_t dev = adapter->dev;
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struct ixgbe_rx_buf *rxbuf;
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int bsize, error;
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int i, bsize, error;
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bsize = sizeof(struct ixgbe_rx_buf) * rxr->num_desc;
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if (!(rxr->rx_buffers =
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@ -1405,7 +1406,7 @@ ixgbe_allocate_receive_buffers(struct rx_ring *rxr)
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goto fail;
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}
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for (int i = 0; i < rxr->num_desc; i++, rxbuf++) {
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for (i = 0; i < rxr->num_desc; i++, rxbuf++) {
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rxbuf = &rxr->rx_buffers[i];
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error = bus_dmamap_create(rxr->ptag, 0, &rxbuf->pmap);
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if (error) {
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@ -1427,8 +1428,9 @@ static void
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ixgbe_free_receive_ring(struct rx_ring *rxr)
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{
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struct ixgbe_rx_buf *rxbuf;
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int i;
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for (int i = 0; i < rxr->num_desc; i++) {
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for (i = 0; i < rxr->num_desc; i++) {
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rxbuf = &rxr->rx_buffers[i];
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if (rxbuf->buf != NULL) {
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bus_dmamap_sync(rxr->ptag, rxbuf->pmap,
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@ -2138,9 +2140,6 @@ ixgbe_allocate_queues(struct adapter *adapter)
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struct rx_ring *rxr;
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int rsize, tsize, error = IXGBE_SUCCESS;
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int txconf = 0, rxconf = 0;
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#ifdef PCI_IOV
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enum ixgbe_iov_mode iov_mode;
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#endif
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/* First allocate the top level queue structs */
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if (!(adapter->queues =
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@ -2173,12 +2172,6 @@ ixgbe_allocate_queues(struct adapter *adapter)
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tsize = roundup2(adapter->num_tx_desc *
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sizeof(union ixgbe_adv_tx_desc), DBA_ALIGN);
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#ifdef PCI_IOV
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iov_mode = ixgbe_get_iov_mode(adapter);
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adapter->pool = ixgbe_max_vfs(iov_mode);
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#else
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adapter->pool = 0;
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#endif
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/*
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* Now set up the TX queues, txconf is needed to handle the
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* possibility that things fail midcourse and we need to
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@ -2188,11 +2181,7 @@ ixgbe_allocate_queues(struct adapter *adapter)
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/* Set up some basics */
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txr = &adapter->tx_rings[i];
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txr->adapter = adapter;
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#ifdef PCI_IOV
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txr->me = ixgbe_pf_que_index(iov_mode, i);
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#else
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txr->me = i;
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#endif
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txr->num_desc = adapter->num_tx_desc;
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/* Initialize the TX side lock */
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@ -2239,11 +2228,7 @@ ixgbe_allocate_queues(struct adapter *adapter)
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rxr = &adapter->rx_rings[i];
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/* Set up some basics */
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rxr->adapter = adapter;
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#ifdef PCI_IOV
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rxr->me = ixgbe_pf_que_index(iov_mode, i);
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#else
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rxr->me = i;
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#endif
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rxr->num_desc = adapter->num_rx_desc;
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/* Initialize the RX side lock */
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@ -92,21 +92,11 @@
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#include <machine/smp.h>
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#include <sys/sbuf.h>
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#ifdef PCI_IOV
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#include <sys/nv.h>
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#include <sys/iov_schema.h>
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#endif
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#include "ixgbe_api.h"
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#include "ixgbe_common.h"
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#include "ixgbe_phy.h"
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#include "ixgbe_vf.h"
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#ifdef PCI_IOV
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#include "ixgbe_common.h"
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#include "ixgbe_mbx.h"
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#endif
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/* Tunables */
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/*
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@ -254,29 +244,6 @@
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(_adapter->hw.mac.type == ixgbe_mac_X540_vf) || \
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(_adapter->hw.mac.type == ixgbe_mac_82599_vf))
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#ifdef PCI_IOV
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#define IXGBE_VF_INDEX(vmdq) ((vmdq) / 32)
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#define IXGBE_VF_BIT(vmdq) (1 << ((vmdq) % 32))
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#define IXGBE_VT_MSG_MASK 0xFFFF
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#define IXGBE_VT_MSGINFO(msg) \
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(((msg) & IXGBE_VT_MSGINFO_MASK) >> IXGBE_VT_MSGINFO_SHIFT)
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#define IXGBE_VF_GET_QUEUES_RESP_LEN 5
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#define IXGBE_API_VER_1_0 0
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#define IXGBE_API_VER_2_0 1 /* Solaris API. Not supported. */
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#define IXGBE_API_VER_1_1 2
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#define IXGBE_API_VER_UNKNOWN UINT16_MAX
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enum ixgbe_iov_mode {
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IXGBE_64_VM,
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IXGBE_32_VM,
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IXGBE_NO_VM
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};
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#endif /* PCI_IOV */
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/*
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*****************************************************************************
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@ -295,7 +262,6 @@ typedef struct _ixgbe_vendor_info_t {
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unsigned int index;
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} ixgbe_vendor_info_t;
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struct ixgbe_tx_buf {
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union ixgbe_adv_tx_desc *eop;
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struct mbuf *m_head;
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@ -324,11 +290,6 @@ struct ixgbe_dma_alloc {
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int dma_nseg;
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};
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struct ixgbe_mc_addr {
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u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
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u32 vmdq;
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};
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/*
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** Driver queue struct: this is the interrupt container
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** for the associated tx and rx ring.
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@ -426,28 +387,6 @@ struct rx_ring {
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#endif
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};
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#ifdef PCI_IOV
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#define IXGBE_VF_CTS (1 << 0) /* VF is clear to send. */
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#define IXGBE_VF_CAP_MAC (1 << 1) /* VF is permitted to change MAC. */
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#define IXGBE_VF_CAP_VLAN (1 << 2) /* VF is permitted to join vlans. */
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#define IXGBE_VF_ACTIVE (1 << 3) /* VF is active. */
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#define IXGBE_MAX_VF_MC 30 /* Max number of multicast entries */
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struct ixgbe_vf {
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u_int pool;
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u_int rar_index;
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u_int max_frame_size;
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uint32_t flags;
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uint8_t ether_addr[ETHER_ADDR_LEN];
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uint16_t mc_hash[IXGBE_MAX_VF_MC];
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uint16_t num_mc_hashes;
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uint16_t default_vlan;
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uint16_t vlan_tag;
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uint16_t api_ver;
|
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};
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#endif /* PCI_IOV */
|
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/* Our adapter structure */
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struct adapter {
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struct ifnet *ifp;
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@ -499,8 +438,8 @@ struct adapter {
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bool link_up;
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u32 vector;
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u16 dmac;
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bool eee_support;
|
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bool eee_enabled;
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u32 phy_layer;
|
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|
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/* Power management-related */
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bool wol_support;
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@ -514,9 +453,6 @@ struct adapter {
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struct task link_task; /* Link tasklet */
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struct task mod_task; /* SFP tasklet */
|
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struct task msf_task; /* Multispeed Fiber */
|
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#ifdef PCI_IOV
|
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struct task mbx_task; /* VF -> PF mailbox interrupt */
|
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#endif /* PCI_IOV */
|
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#ifdef IXGBE_FDIR
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int fdir_reinit;
|
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struct task fdir_task;
|
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@ -548,12 +484,8 @@ struct adapter {
|
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u32 num_rx_desc;
|
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|
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/* Multicast array memory */
|
||||
struct ixgbe_mc_addr *mta;
|
||||
int num_vfs;
|
||||
int pool;
|
||||
#ifdef PCI_IOV
|
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struct ixgbe_vf *vfs;
|
||||
#endif
|
||||
u8 *mta;
|
||||
|
||||
|
||||
/* Misc stats maintained by the driver */
|
||||
unsigned long dropped_pkts;
|
||||
@ -739,150 +671,4 @@ bool ixgbe_rxeof(struct ix_queue *);
|
||||
int ixgbe_dma_malloc(struct adapter *,
|
||||
bus_size_t, struct ixgbe_dma_alloc *, int);
|
||||
void ixgbe_dma_free(struct adapter *, struct ixgbe_dma_alloc *);
|
||||
|
||||
#ifdef PCI_IOV
|
||||
|
||||
static inline boolean_t
|
||||
ixgbe_vf_mac_changed(struct ixgbe_vf *vf, const uint8_t *mac)
|
||||
{
|
||||
return (bcmp(mac, vf->ether_addr, ETHER_ADDR_LEN) != 0);
|
||||
}
|
||||
|
||||
static inline void
|
||||
ixgbe_send_vf_msg(struct adapter *adapter, struct ixgbe_vf *vf, u32 msg)
|
||||
{
|
||||
|
||||
if (vf->flags & IXGBE_VF_CTS)
|
||||
msg |= IXGBE_VT_MSGTYPE_CTS;
|
||||
|
||||
ixgbe_write_mbx(&adapter->hw, &msg, 1, vf->pool);
|
||||
}
|
||||
|
||||
static inline void
|
||||
ixgbe_send_vf_ack(struct adapter *adapter, struct ixgbe_vf *vf, u32 msg)
|
||||
{
|
||||
msg &= IXGBE_VT_MSG_MASK;
|
||||
ixgbe_send_vf_msg(adapter, vf, msg | IXGBE_VT_MSGTYPE_ACK);
|
||||
}
|
||||
|
||||
static inline void
|
||||
ixgbe_send_vf_nack(struct adapter *adapter, struct ixgbe_vf *vf, u32 msg)
|
||||
{
|
||||
msg &= IXGBE_VT_MSG_MASK;
|
||||
ixgbe_send_vf_msg(adapter, vf, msg | IXGBE_VT_MSGTYPE_NACK);
|
||||
}
|
||||
|
||||
static inline void
|
||||
ixgbe_process_vf_ack(struct adapter *adapter, struct ixgbe_vf *vf)
|
||||
{
|
||||
if (!(vf->flags & IXGBE_VF_CTS))
|
||||
ixgbe_send_vf_nack(adapter, vf, 0);
|
||||
}
|
||||
|
||||
static inline enum ixgbe_iov_mode
|
||||
ixgbe_get_iov_mode(struct adapter *adapter)
|
||||
{
|
||||
if (adapter->num_vfs == 0)
|
||||
return (IXGBE_NO_VM);
|
||||
if (adapter->num_queues <= 2)
|
||||
return (IXGBE_64_VM);
|
||||
else if (adapter->num_queues <= 4)
|
||||
return (IXGBE_32_VM);
|
||||
else
|
||||
return (IXGBE_NO_VM);
|
||||
}
|
||||
|
||||
static inline u16
|
||||
ixgbe_max_vfs(enum ixgbe_iov_mode mode)
|
||||
{
|
||||
/*
|
||||
* We return odd numbers below because we
|
||||
* reserve 1 VM's worth of queues for the PF.
|
||||
*/
|
||||
switch (mode) {
|
||||
case IXGBE_64_VM:
|
||||
return (63);
|
||||
case IXGBE_32_VM:
|
||||
return (31);
|
||||
case IXGBE_NO_VM:
|
||||
default:
|
||||
return (0);
|
||||
}
|
||||
}
|
||||
|
||||
static inline int
|
||||
ixgbe_vf_queues(enum ixgbe_iov_mode mode)
|
||||
{
|
||||
switch (mode) {
|
||||
case IXGBE_64_VM:
|
||||
return (2);
|
||||
case IXGBE_32_VM:
|
||||
return (4);
|
||||
case IXGBE_NO_VM:
|
||||
default:
|
||||
return (0);
|
||||
}
|
||||
}
|
||||
|
||||
static inline int
|
||||
ixgbe_vf_que_index(enum ixgbe_iov_mode mode, u32 vfnum, int num)
|
||||
{
|
||||
return ((vfnum * ixgbe_vf_queues(mode)) + num);
|
||||
}
|
||||
|
||||
static inline int
|
||||
ixgbe_pf_que_index(enum ixgbe_iov_mode mode, int num)
|
||||
{
|
||||
return (ixgbe_vf_que_index(mode, ixgbe_max_vfs(mode), num));
|
||||
}
|
||||
|
||||
static inline void
|
||||
ixgbe_update_max_frame(struct adapter * adapter, int max_frame)
|
||||
{
|
||||
if (adapter->max_frame_size < max_frame)
|
||||
adapter->max_frame_size = max_frame;
|
||||
}
|
||||
|
||||
static inline u32
|
||||
ixgbe_get_mrqc(enum ixgbe_iov_mode mode)
|
||||
{
|
||||
u32 mrqc = 0;
|
||||
switch (mode) {
|
||||
case IXGBE_64_VM:
|
||||
mrqc = IXGBE_MRQC_VMDQRSS64EN;
|
||||
break;
|
||||
case IXGBE_32_VM:
|
||||
mrqc = IXGBE_MRQC_VMDQRSS32EN;
|
||||
break;
|
||||
case IXGBE_NO_VM:
|
||||
mrqc = 0;
|
||||
break;
|
||||
default:
|
||||
panic("Unexpected SR-IOV mode %d", mode);
|
||||
}
|
||||
return(mrqc);
|
||||
}
|
||||
|
||||
|
||||
static inline u32
|
||||
ixgbe_get_mtqc(enum ixgbe_iov_mode mode)
|
||||
{
|
||||
uint32_t mtqc = 0;
|
||||
switch (mode) {
|
||||
case IXGBE_64_VM:
|
||||
mtqc |= IXGBE_MTQC_64VF | IXGBE_MTQC_VT_ENA;
|
||||
break;
|
||||
case IXGBE_32_VM:
|
||||
mtqc |= IXGBE_MTQC_32VF | IXGBE_MTQC_VT_ENA;
|
||||
break;
|
||||
case IXGBE_NO_VM:
|
||||
mtqc = IXGBE_MTQC_64Q_1PB;
|
||||
break;
|
||||
default:
|
||||
panic("Unexpected SR-IOV mode %d", mode);
|
||||
}
|
||||
return(mtqc);
|
||||
}
|
||||
#endif /* PCI_IOV */
|
||||
|
||||
#endif /* _IXGBE_H_ */
|
||||
|
@ -80,21 +80,6 @@
|
||||
/* bits 23:16 are used for extra info for certain messages */
|
||||
#define IXGBE_VT_MSGINFO_MASK (0xFF << IXGBE_VT_MSGINFO_SHIFT)
|
||||
|
||||
/* definitions to support mailbox API version negotiation */
|
||||
|
||||
/*
|
||||
* each element denotes a version of the API; existing numbers may not
|
||||
* change; any additions must go at the end
|
||||
*/
|
||||
enum ixgbe_pfvf_api_rev {
|
||||
ixgbe_mbox_api_10, /* API version 1.0, linux/freebsd VF driver */
|
||||
ixgbe_mbox_api_20, /* API version 2.0, solaris Phase1 VF driver */
|
||||
ixgbe_mbox_api_11, /* API version 1.1, linux/freebsd VF driver */
|
||||
/* This value should always be last */
|
||||
ixgbe_mbox_api_unknown, /* indicates that API version is not known */
|
||||
};
|
||||
|
||||
/* mailbox API, legacy requests */
|
||||
#define IXGBE_VF_RESET 0x01 /* VF requests reset */
|
||||
#define IXGBE_VF_SET_MAC_ADDR 0x02 /* VF requests PF to set MAC addr */
|
||||
#define IXGBE_VF_SET_MULTICAST 0x03 /* VF requests PF to set MC addr */
|
||||
@ -121,18 +106,6 @@ enum ixgbe_pfvf_api_rev {
|
||||
|
||||
#define IXGBE_PF_CONTROL_MSG 0x0100 /* PF control message */
|
||||
|
||||
/* mailbox API, version 2.0 VF requests */
|
||||
#define IXGBE_VF_API_NEGOTIATE 0x08 /* negotiate API version */
|
||||
#define IXGBE_VF_GET_QUEUES 0x09 /* get queue configuration */
|
||||
#define IXGBE_VF_ENABLE_MACADDR 0x0A /* enable MAC address */
|
||||
#define IXGBE_VF_DISABLE_MACADDR 0x0B /* disable MAC address */
|
||||
#define IXGBE_VF_GET_MACADDRS 0x0C /* get all configured MAC addrs */
|
||||
#define IXGBE_VF_SET_MCAST_PROMISC 0x0D /* enable multicast promiscuous */
|
||||
#define IXGBE_VF_GET_MTU 0x0E /* get bounds on MTU */
|
||||
#define IXGBE_VF_SET_MTU 0x0F /* set a specific MTU */
|
||||
|
||||
/* mailbox API, version 2.0 PF requests */
|
||||
#define IXGBE_PF_TRANSPARENT_VLAN 0x0101 /* enable transparent vlan */
|
||||
|
||||
#define IXGBE_VF_MBX_INIT_TIMEOUT 2000 /* number of retries on mailbox */
|
||||
#define IXGBE_VF_MBX_INIT_DELAY 500 /* microseconds between retries */
|
||||
|
@ -185,8 +185,6 @@ s32 ixgbe_reset_hw_vf(struct ixgbe_hw *hw)
|
||||
/* Call adapter stop to disable tx/rx and clear interrupts */
|
||||
hw->mac.ops.stop_adapter(hw);
|
||||
|
||||
/* reset the api version */
|
||||
hw->api_version = ixgbe_mbox_api_10;
|
||||
|
||||
DEBUGOUT("Issuing a function level reset to MAC\n");
|
||||
|
||||
@ -668,57 +666,6 @@ int ixgbevf_negotiate_api_version(struct ixgbe_hw *hw, int api)
|
||||
int ixgbevf_get_queues(struct ixgbe_hw *hw, unsigned int *num_tcs,
|
||||
unsigned int *default_tc)
|
||||
{
|
||||
int err;
|
||||
u32 msg[5];
|
||||
|
||||
/* do nothing if API doesn't support ixgbevf_get_queues */
|
||||
switch (hw->api_version) {
|
||||
case ixgbe_mbox_api_11:
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Fetch queue configuration from the PF */
|
||||
msg[0] = IXGBE_VF_GET_QUEUES;
|
||||
msg[1] = msg[2] = msg[3] = msg[4] = 0;
|
||||
err = hw->mbx.ops.write_posted(hw, msg, 5, 0);
|
||||
|
||||
if (!err)
|
||||
err = hw->mbx.ops.read_posted(hw, msg, 5, 0);
|
||||
|
||||
if (!err) {
|
||||
msg[0] &= ~IXGBE_VT_MSGTYPE_CTS;
|
||||
|
||||
/*
|
||||
* if we we didn't get an ACK there must have been
|
||||
* some sort of mailbox error so we should treat it
|
||||
* as such
|
||||
*/
|
||||
if (msg[0] != (IXGBE_VF_GET_QUEUES | IXGBE_VT_MSGTYPE_ACK))
|
||||
return IXGBE_ERR_MBX;
|
||||
|
||||
/* record and validate values from message */
|
||||
hw->mac.max_tx_queues = msg[IXGBE_VF_TX_QUEUES];
|
||||
if (hw->mac.max_tx_queues == 0 ||
|
||||
hw->mac.max_tx_queues > IXGBE_VF_MAX_TX_QUEUES)
|
||||
hw->mac.max_tx_queues = IXGBE_VF_MAX_TX_QUEUES;
|
||||
|
||||
hw->mac.max_rx_queues = msg[IXGBE_VF_RX_QUEUES];
|
||||
if (hw->mac.max_rx_queues == 0 ||
|
||||
hw->mac.max_rx_queues > IXGBE_VF_MAX_RX_QUEUES)
|
||||
hw->mac.max_rx_queues = IXGBE_VF_MAX_RX_QUEUES;
|
||||
|
||||
*num_tcs = msg[IXGBE_VF_TRANS_VLAN];
|
||||
/* in case of unknown state assume we cannot tag frames */
|
||||
if (*num_tcs > hw->mac.max_rx_queues)
|
||||
*num_tcs = 1;
|
||||
|
||||
*default_tc = msg[IXGBE_VF_DEF_QUEUE];
|
||||
/* default to queue 0 on out-of-bounds queue number */
|
||||
if (*default_tc >= hw->mac.max_tx_queues)
|
||||
*default_tc = 0;
|
||||
}
|
||||
|
||||
return err;
|
||||
UNREFERENCED_3PARAMETER(hw, num_tcs, default_tc);
|
||||
return IXGBE_SUCCESS;
|
||||
}
|
||||
|
@ -7,8 +7,9 @@ SRCS = device_if.h bus_if.h pci_if.h
|
||||
SRCS += opt_inet.h opt_inet6.h opt_rss.h
|
||||
SRCS += if_ixv.c ix_txrx.c
|
||||
# Shared source
|
||||
SRCS += ixgbe_common.c ixgbe_api.c ixgbe_phy.c
|
||||
SRCS += ixgbe_dcb.c ixgbe_mbx.c ixgbe_vf.c
|
||||
SRCS += ixgbe_common.c ixgbe_api.c ixgbe_phy.c ixgbe_mbx.c ixgbe_vf.c
|
||||
SRCS += ixgbe_dcb.c ixgbe_dcb_82598.c ixgbe_dcb_82599.c
|
||||
SRCS += ixgbe_82598.c ixgbe_82599.c ixgbe_x540.c ixgbe_x550.c
|
||||
CFLAGS+= -I${.CURDIR}/../../dev/ixgbe -DSMP
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
|
Loading…
Reference in New Issue
Block a user