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ARM: Introduce new cpu-v4.h header and move all ARMv4 specific code

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from cpu-v6.h to it.
Remove unneeded cpu-v6.h includes.
This commit is contained in:
Michal Meloun 2016-02-05 09:46:24 +00:00
parent 3fd8cd9ce4
commit 3025d19dfc
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=295315
9 changed files with 181 additions and 66 deletions
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7
sys/arm/arm/cpuinfo.c
View File

@ -31,8 +31,8 @@ __FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <machine/cpu.h>
#include <machine/cpuinfo.h>
#include <machine/cpu-v6.h>
struct cpuinfo cpuinfo =
{
@ -83,14 +83,16 @@ cpuinfo_init(void)
/* CP15 c0,c0 regs 0-7 exist on all CPUs (although aliased with MIDR) */
cpuinfo.ctr = cp15_ctr_get();
cpuinfo.tcmtr = cp15_tcmtr_get();
#if __ARM_ARCH >= 6
cpuinfo.tlbtr = cp15_tlbtr_get();
cpuinfo.mpidr = cp15_mpidr_get();
cpuinfo.revidr = cp15_revidr_get();
#endif
/* if CPU is not v7 cpu id scheme */
if (cpuinfo.architecture != 0xF)
return;
#if __ARM_ARCH >= 6
cpuinfo.id_pfr0 = cp15_id_pfr0_get();
cpuinfo.id_pfr1 = cp15_id_pfr1_get();
cpuinfo.id_dfr0 = cp15_id_dfr0_get();
@ -144,6 +146,7 @@ cpuinfo_init(void)
}
cpuinfo.dcache_line_mask = cpuinfo.dcache_line_size - 1;
cpuinfo.icache_line_mask = cpuinfo.icache_line_size - 1;
#endif
}
/*

1
sys/arm/arm/genassym.c
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@ -45,7 +45,6 @@ __FBSDID("$FreeBSD$");
#include <machine/frame.h>
#include <machine/pcb.h>
#include <machine/cpu.h>
#include <machine/cpu-v6.h>
#include <machine/proc.h>
#include <machine/cpufunc.h>
#include <machine/cpuinfo.h>

1
sys/arm/arm/machdep.c
View File

@ -123,7 +123,6 @@ __FBSDID("$FreeBSD$");
#include <ddb/ddb.h>
#if __ARM_ARCH >= 6
#include <machine/cpu-v6.h>
DB_SHOW_COMMAND(cp15, db_show_cp15)
{

1
sys/arm/arm/pmap-v6.c
View File

@ -141,7 +141,6 @@ __FBSDID("$FreeBSD$");
#include <machine/md_var.h>
#include <machine/pmap_var.h>
#include <machine/cpu.h>
#include <machine/cpu-v6.h>
#include <machine/pcb.h>
#include <machine/sf_buf.h>
#ifdef SMP

2
sys/arm/arm/sys_machdep.c
View File

@ -45,7 +45,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm_extern.h>
#include <machine/acle-compat.h>
#include <machine/cpu-v6.h>
#include <machine/cpu.h>
#include <machine/sysarch.h>
#include <machine/vmparam.h>

1
sys/arm/arm/trap-v6.c
View File

@ -55,7 +55,6 @@ __FBSDID("$FreeBSD$");
#include <machine/acle-compat.h>
#include <machine/cpu.h>
#include <machine/cpu-v6.h>
#include <machine/frame.h>
#include <machine/machdep.h>
#include <machine/pcb.h>

154
sys/arm/include/cpu-v4.h Normal file
View File

@ -0,0 +1,154 @@
/*-
* Copyright 2016 Svatopluk Kraus <skra@FreeBSD.org>
* Copyright 2016 Michal Meloun <mmel@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef MACHINE_CPU_V4_H
#define MACHINE_CPU_V4_H
/* There are no user serviceable parts here, they may change without notice */
#ifndef _KERNEL
#error Only include this file in the kernel
#endif
#include <machine/acle-compat.h>
#include <machine/atomic.h>
#include <machine/cpufunc.h>
#include <machine/cpuinfo.h>
#include <machine/sysreg.h>
#if __ARM_ARCH >= 6
#error Newer include this file for ARMv6
#else
#define CPU_ASID_KERNEL 0
/*
* Macros to generate CP15 (system control processor) read/write functions.
*/
#define _FX(s...) #s
#define _RF0(fname, aname...) \
static __inline register_t \
fname(void) \
{ \
register_t reg; \
__asm __volatile("mrc\t" _FX(aname): "=r" (reg)); \
return(reg); \
}
#define _R64F0(fname, aname) \
static __inline uint64_t \
fname(void) \
{ \
uint64_t reg; \
__asm __volatile("mrrc\t" _FX(aname): "=r" (reg)); \
return(reg); \
}
#define _WF0(fname, aname...) \
static __inline void \
fname(void) \
{ \
__asm __volatile("mcr\t" _FX(aname)); \
}
#define _WF1(fname, aname...) \
static __inline void \
fname(register_t reg) \
{ \
__asm __volatile("mcr\t" _FX(aname):: "r" (reg)); \
}
/*
* Publicly accessible functions
*/
/* Various control registers */
_RF0(cp15_cpacr_get, CP15_CPACR(%0))
_WF1(cp15_cpacr_set, CP15_CPACR(%0))
_RF0(cp15_dfsr_get, CP15_DFSR(%0))
_RF0(cp15_ttbr_get, CP15_TTBR0(%0))
_RF0(cp15_dfar_get, CP15_DFAR(%0))
/* XScale */
_RF0(cp15_actlr_get, CP15_ACTLR(%0))
_WF1(cp15_actlr_set, CP15_ACTLR(%0))
/*CPU id registers */
_RF0(cp15_midr_get, CP15_MIDR(%0))
_RF0(cp15_ctr_get, CP15_CTR(%0))
_RF0(cp15_tcmtr_get, CP15_TCMTR(%0))
_RF0(cp15_tlbtr_get, CP15_TLBTR(%0))
#undef _FX
#undef _RF0
#undef _WF0
#undef _WF1
/*
* armv4/5 compatibility shims.
*
* These functions provide armv4 cache maintenance using the new armv6 names.
* Included here are just the functions actually used now in common code; it may
* be necessary to add things here over time.
*
* The callers of the dcache functions expect these routines to handle address
* and size values which are not aligned to cacheline boundaries; the armv4 and
* armv5 asm code handles that.
*/
static __inline void
dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
{
cpu_dcache_inv_range(va, size);
cpu_l2cache_inv_range(va, size);
}
static __inline void
dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
{
/* See armv6 code, above, for why we do L2 before L1 in this case. */
cpu_l2cache_inv_range(va, size);
cpu_dcache_inv_range(va, size);
}
static __inline void
dcache_wb_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
{
cpu_dcache_wb_range(va, size);
cpu_l2cache_wb_range(va, size);
}
#endif /* _KERNEL */
#endif /* MACHINE_CPU_V4_H */

72
sys/arm/include/cpu-v6.h
View File

@ -32,19 +32,33 @@
/* There are no user serviceable parts here, they may change without notice */
#ifndef _KERNEL
#error Only include this file in the kernel
#else
#endif
#include <machine/acle-compat.h>
#include "machine/atomic.h"
#include "machine/cpufunc.h"
#include "machine/cpuinfo.h"
#include "machine/sysreg.h"
#include <machine/atomic.h>
#include <machine/cpufunc.h>
#include <machine/cpuinfo.h>
#include <machine/sysreg.h>
#if __ARM_ARCH < 6
#error Only include this file for ARMv6
#else
#define CPU_ASID_KERNEL 0
vm_offset_t dcache_wb_pou_checked(vm_offset_t, vm_size_t);
vm_offset_t icache_inv_pou_checked(vm_offset_t, vm_size_t);
#ifdef DEV_PMU
#include <sys/pcpu.h>
#define PMU_OVSR_C 0x80000000 /* Cycle Counter */
extern uint32_t ccnt_hi[MAXCPU];
extern int pmu_attched;
#endif /* DEV_PMU */
/*
* Macros to generate CP15 (system control processor) read/write functions.
*/
@ -277,12 +291,6 @@ _W64F1(cp15_cnthp_cval_set, CP15_CNTHP_CVAL(%Q0, %R0))
#undef _WF0
#undef _WF1
#if __ARM_ARCH >= 6
/*
* Cache and TLB maintenance operations for armv6+ code. The #else block
* provides armv4/v5 implementations for a few of these used in common code.
*/
/*
* TLB maintenance operations.
*/
@ -577,48 +585,6 @@ cp15_ttbr_set(uint32_t reg)
isb();
tlb_flush_all_ng_local();
}
#else /* ! __ARM_ARCH >= 6 */
/*
* armv4/5 compatibility shims.
*
* These functions provide armv4 cache maintenance using the new armv6 names.
* Included here are just the functions actually used now in common code; it may
* be necessary to add things here over time.
*
* The callers of the dcache functions expect these routines to handle address
* and size values which are not aligned to cacheline boundaries; the armv4 and
* armv5 asm code handles that.
*/
static __inline void
dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
{
cpu_dcache_inv_range(va, size);
cpu_l2cache_inv_range(va, size);
}
static __inline void
dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
{
/* See armv6 code, above, for why we do L2 before L1 in this case. */
cpu_l2cache_inv_range(va, size);
cpu_dcache_inv_range(va, size);
}
static __inline void
dcache_wb_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
{
cpu_dcache_wb_range(va, size);
cpu_l2cache_wb_range(va, size);
}
#endif /* __ARM_ARCH >= 6 */
#endif /* _KERNEL */
#endif /* !MACHINE_CPU_V6_H */

8
sys/arm/include/cpu.h
View File

@ -14,12 +14,8 @@ void swi_vm(void *);
#ifdef _KERNEL
#if __ARM_ARCH >= 6
#include <machine/cpu-v6.h>
#ifdef DEV_PMU
#include <sys/pcpu.h>
#define PMU_OVSR_C 0x80000000 /* Cycle Counter */
extern uint32_t ccnt_hi[MAXCPU];
extern int pmu_attched;
#endif /* DEV_PMU */
#else
#include <machine/cpu-v4.h>
#endif /* __ARM_ARCH >= 6 */
static __inline uint64_t