Remove unused file. Replaced by tlb.c.
This commit is contained in:
Juli Mallett
parent
bfa39fa09f
commit
32272e3b0a
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=210317
@ -1,513 +0,0 @@
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/* $OpenBSD: locore.S,v 1.18 1998/09/15 10:58:53 pefo Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Digital Equipment Corporation and Ralph Campbell.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Copyright (C) 1989 Digital Equipment Corporation.
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* Permission to use, copy, modify, and distribute this software and
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* its documentation for any purpose and without fee is hereby granted,
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* provided that the above copyright notice appears in all copies.
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* Digital Equipment Corporation makes no representations about the
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* suitability of this software for any purpose. It is provided "as is"
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* without express or implied warranty.
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*
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* from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/loMem.s,
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* v 1.1 89/07/11 17:55:04 nelson Exp SPRITE (DECWRL)
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* from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsm.s,
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* v 9.2 90/01/29 18:00:39 shirriff Exp SPRITE (DECWRL)
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* from: Header: /sprite/src/kernel/vm/ds3100.md/vmPmaxAsm.s,
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* v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL)
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*
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* from: @(#)locore.s 8.5 (Berkeley) 1/4/94
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* JNPR: tlb.S,v 1.1.4.2 2007/09/10 09:02:05 girish
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* $FreeBSD$
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*/
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/*
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* Contains code that is the first executed at boot time plus
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* assembly language support routines.
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*/
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#include "opt_cputype.h"
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#include <machine/asm.h>
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#include <machine/cpu.h>
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#include <machine/cpuregs.h>
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#include <machine/regnum.h>
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#include <machine/pte.h>
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#include "assym.s"
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#if defined(ISA_MIPS32)
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#undef WITH_64BIT_CP0
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#elif defined(ISA_MIPS64)
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#define WITH_64BIT_CP0
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#elif defined(ISA_MIPS3)
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#define WITH_64BIT_CP0
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#else
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#error "Please write the code for this ISA"
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#endif
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#ifdef WITH_64BIT_CP0
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#define _SLL dsll
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#define _SRL dsrl
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#define _MFC0 dmfc0
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#define _MTC0 dmtc0
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#define WIRED_SHIFT 34
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#else
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#define _SLL sll
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#define _SRL srl
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#define _MFC0 mfc0
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#define _MTC0 mtc0
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#define WIRED_SHIFT 2
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#endif
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.set noreorder # Noreorder is default style!
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#if defined(ISA_MIPS32)
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.set mips32
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#elif defined(ISA_MIPS64)
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.set mips64
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#elif defined(ISA_MIPS3)
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.set mips3
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#endif
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/*--------------------------------------------------------------------------
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*
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* Mips_TLBWriteIndexed(unsigned index, tlb *tlb);
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*
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* Write the given entry into the TLB at the given index.
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*
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* Results:
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* None.
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*
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* Side effects:
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* TLB entry set.
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*
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*--------------------------------------------------------------------------
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*/
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LEAF(Mips_TLBWriteIndexed)
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mfc0 v1, COP_0_STATUS_REG # Save the status register.
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mtc0 zero, COP_0_STATUS_REG # Disable interrupts
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ITLBNOPFIX
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lw a2, 8(a1)
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lw a3, 12(a1)
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_MFC0 t0, COP_0_TLB_HI # Save the current PID.
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_MTC0 a2, COP_0_TLB_LO0 # Set up entry low0.
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_MTC0 a3, COP_0_TLB_LO1 # Set up entry low1.
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lw a2, 0(a1)
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lw a3, 4(a1)
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mtc0 a0, COP_0_TLB_INDEX # Set the index.
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_MTC0 a2, COP_0_TLB_PG_MASK # Set up entry mask.
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_MTC0 a3, COP_0_TLB_HI # Set up entry high.
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HAZARD_DELAY
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tlbwi # Write the TLB
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HAZARD_DELAY
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_MTC0 t0, COP_0_TLB_HI # Restore the PID.
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nop
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_MTC0 zero, COP_0_TLB_PG_MASK # Default mask value.
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mtc0 v1, COP_0_STATUS_REG # Restore the status register
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ITLBNOPFIX
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j ra
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nop
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END(Mips_TLBWriteIndexed)
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/*--------------------------------------------------------------------------
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*
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* Mips_SetPID(int pid);
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*
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* Write the given pid into the TLB pid reg.
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*
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* Results:
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* None.
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*
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* Side effects:
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* PID set in the entry hi register.
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*
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*--------------------------------------------------------------------------
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*/
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LEAF(Mips_SetPID)
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_MTC0 a0, COP_0_TLB_HI # Write the hi reg value
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nop # required for QED5230
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nop # required for QED5230
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j ra
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nop
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END(Mips_SetPID)
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/*--------------------------------------------------------------------------
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*
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* Mips_SetWIRED(int wired);
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*
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* Write the given value into the TLB wired reg.
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*
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* Results:
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* None.
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*
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* Side effects:
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* WIRED set in the wired register.
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*
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*--------------------------------------------------------------------------
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*/
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LEAF(Mips_SetWIRED)
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mtc0 a0, COP_0_TLB_WIRED
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j ra
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nop
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END(Mips_SetWIRED)
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/*--------------------------------------------------------------------------
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*
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* Mips_GetWIRED(void);
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*
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* Get the value from the TLB wired reg.
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*
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* Results:
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* Value of wired reg.
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*
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* Side effects:
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* None.
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*
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*--------------------------------------------------------------------------
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*/
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LEAF(Mips_GetWIRED)
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mfc0 v0, COP_0_TLB_WIRED
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j ra
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nop
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END(Mips_GetWIRED)
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/*--------------------------------------------------------------------------
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*
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* Mips_TLBFlush(tlbsize);
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*
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* Flush the "random" entries from the TLB.
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* Uses "wired" register to determine what register to start with.
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* Arg "tlbsize" is the number of entries to flush.
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*
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* Results:
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* None.
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*
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* Side effects:
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* The TLB is flushed.
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*
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*--------------------------------------------------------------------------
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*/
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LEAF(Mips_TLBFlush)
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mfc0 v1, COP_0_STATUS_REG # Save the status register.
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mtc0 zero, COP_0_STATUS_REG # Disable interrupts
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ITLBNOPFIX
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mfc0 t1, COP_0_TLB_WIRED
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_MFC0 t0, COP_0_TLB_HI # Save the PID
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_MTC0 zero, COP_0_TLB_LO0 # Zero out low entry0.
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_MTC0 zero, COP_0_TLB_LO1 # Zero out low entry1.
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mtc0 zero, COP_0_TLB_PG_MASK # Zero out mask entry.
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#
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# Load invalid entry, each TLB entry should have it's own bogus
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# address calculated by following expression:
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# MIPS_KSEG0_START + 2 * i * PAGE_SIZE;
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# One bogus value for every TLB entry might cause MCHECK exception
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#
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sll t3, t1, PAGE_SHIFT + 1
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li v0, MIPS_KSEG0_START # invalid address
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addu v0, t3
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/*
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* Align the starting value (t1) and the upper bound (a0).
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*/
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1:
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mtc0 t1, COP_0_TLB_INDEX # Set the index register.
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ITLBNOPFIX
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_MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid
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addu t1, t1, 1 # Increment index.
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addu v0, v0, 8 * 1024
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HAZARD_DELAY
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tlbwi # Write the TLB entry.
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HAZARD_DELAY
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bne t1, a0, 1b
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nop
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_MTC0 t0, COP_0_TLB_HI # Restore the PID
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mtc0 v1, COP_0_STATUS_REG # Restore the status register
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ITLBNOPFIX
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j ra
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nop
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END(Mips_TLBFlush)
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/*--------------------------------------------------------------------------
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*
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* Mips_TLBFlushAddr(unsigned TLBhi);
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*
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* Flush any TLB entries for the given address and TLB PID.
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*
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* Results:
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* None.
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*
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* Side effects:
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* The process's page is flushed from the TLB.
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*
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*--------------------------------------------------------------------------
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*/
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LEAF(Mips_TLBFlushAddr)
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mfc0 v1, COP_0_STATUS_REG # Save the status register.
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mtc0 zero, COP_0_STATUS_REG # Disable interrupts
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ITLBNOPFIX
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li v0, (PTE_HVPN | PTE_ASID)
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and a0, a0, v0 # Make shure valid hi value.
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_MFC0 t0, COP_0_TLB_HI # Get current PID
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mfc0 t3, COP_0_TLB_PG_MASK # Save current pgMask
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_MTC0 a0, COP_0_TLB_HI # look for addr & PID
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HAZARD_DELAY
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tlbp # Probe for the entry.
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HAZARD_DELAY
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mfc0 v0, COP_0_TLB_INDEX # See what we got
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li t1, MIPS_KSEG0_START
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bltz v0, 1f # index < 0 => !found
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nop
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# Load invalid entry, each TLB entry should have it's own bogus
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# address calculated by following expression:
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# MIPS_KSEG0_START + 2 * i * PAGE_SIZE;
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# One bogus value for every TLB entry might cause MCHECK exception
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sll v0, PAGE_SHIFT + 1
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addu t1, v0
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_MTC0 t1, COP_0_TLB_HI # Mark entry high as invalid
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_MTC0 zero, COP_0_TLB_LO0 # Zero out low entry.
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_MTC0 zero, COP_0_TLB_LO1 # Zero out low entry.
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HAZARD_DELAY
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tlbwi
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HAZARD_DELAY
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1:
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_MTC0 t0, COP_0_TLB_HI # restore PID
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mtc0 t3, COP_0_TLB_PG_MASK # Restore pgMask
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mtc0 v1, COP_0_STATUS_REG # Restore the status register
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ITLBNOPFIX
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j ra
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nop
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END(Mips_TLBFlushAddr)
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/*--------------------------------------------------------------------------
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*
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* Mips_TLBUpdate(unsigned virpageadr, lowregx);
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*
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* Update the TLB if highreg is found; otherwise, enter the data.
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*
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* Results:
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* < 0 if loaded >= 0 if updated.
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*
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* Side effects:
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* None.
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*
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*--------------------------------------------------------------------------
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*/
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LEAF(Mips_TLBUpdate)
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mfc0 v1, COP_0_STATUS_REG # Save the status register.
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mtc0 zero, COP_0_STATUS_REG # Disable interrupts
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ITLBNOPFIX
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and t1, a0, 0x1000 # t1 = Even/Odd flag
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li v0, (PTE_HVPN | PTE_ASID)
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and a0, a0, v0
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_MFC0 t0, COP_0_TLB_HI # Save current PID
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_MTC0 a0, COP_0_TLB_HI # Init high reg
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and a2, a1, PTE_G # Copy global bit
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HAZARD_DELAY
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tlbp # Probe for the entry.
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_SLL a1, a1, WIRED_SHIFT
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_SRL a1, a1, WIRED_SHIFT
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nop
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mfc0 v0, COP_0_TLB_INDEX # See what we got
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bne t1, zero, 2f # Decide even odd
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# EVEN
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nop
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bltz v0, 1f # index < 0 => !found
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HAZARD_DELAY
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tlbr # update, read entry first
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HAZARD_DELAY
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_MTC0 a1, COP_0_TLB_LO0 # init low reg0.
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HAZARD_DELAY
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tlbwi # update slot found
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b 4f
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nop
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||||||
1:
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mtc0 zero, COP_0_TLB_PG_MASK # init mask.
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_MTC0 a0, COP_0_TLB_HI # init high reg.
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|
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_MTC0 a1, COP_0_TLB_LO0 # init low reg0.
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_MTC0 a2, COP_0_TLB_LO1 # init low reg1.
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|
||||||
HAZARD_DELAY
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|
||||||
tlbwr # enter into a random slot
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HAZARD_DELAY
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b 4f
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nop
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# ODD
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2:
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||||||
nop
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||||||
bltz v0, 3f # index < 0 => !found
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|
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HAZARD_DELAY
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|
||||||
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|
||||||
tlbr # read the entry first
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||||||
HAZARD_DELAY
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|
||||||
_MTC0 a1, COP_0_TLB_LO1 # init low reg1.
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|
||||||
HAZARD_DELAY
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||||||
tlbwi # update slot found
|
|
||||||
HAZARD_DELAY
|
|
||||||
b 4f
|
|
||||||
nop
|
|
||||||
3:
|
|
||||||
mtc0 zero, COP_0_TLB_PG_MASK # init mask.
|
|
||||||
_MTC0 a0, COP_0_TLB_HI # init high reg.
|
|
||||||
_MTC0 a2, COP_0_TLB_LO0 # init low reg0.
|
|
||||||
_MTC0 a1, COP_0_TLB_LO1 # init low reg1.
|
|
||||||
HAZARD_DELAY
|
|
||||||
tlbwr # enter into a random slot
|
|
||||||
|
|
||||||
4: # Make shure pipeline
|
|
||||||
HAZARD_DELAY
|
|
||||||
_MTC0 t0, COP_0_TLB_HI # restore PID
|
|
||||||
mtc0 v1, COP_0_STATUS_REG # Restore the status register
|
|
||||||
ITLBNOPFIX
|
|
||||||
j ra
|
|
||||||
nop
|
|
||||||
END(Mips_TLBUpdate)
|
|
||||||
|
|
||||||
/*--------------------------------------------------------------------------
|
|
||||||
*
|
|
||||||
* Mips_TLBRead(unsigned entry, struct tlb *tlb);
|
|
||||||
*
|
|
||||||
* Read the TLB entry.
|
|
||||||
*
|
|
||||||
* Results:
|
|
||||||
* None.
|
|
||||||
*
|
|
||||||
* Side effects:
|
|
||||||
* tlb will contain the TLB entry found.
|
|
||||||
*
|
|
||||||
*--------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
LEAF(Mips_TLBRead)
|
|
||||||
mfc0 v1, COP_0_STATUS_REG # Save the status register.
|
|
||||||
mtc0 zero, COP_0_STATUS_REG # Disable interrupts
|
|
||||||
ITLBNOPFIX
|
|
||||||
_MFC0 t0, COP_0_TLB_HI # Get current PID
|
|
||||||
|
|
||||||
mtc0 a0, COP_0_TLB_INDEX # Set the index register
|
|
||||||
HAZARD_DELAY
|
|
||||||
tlbr # Read from the TLB
|
|
||||||
HAZARD_DELAY
|
|
||||||
mfc0 t2, COP_0_TLB_PG_MASK # fetch the hi entry
|
|
||||||
_MFC0 t3, COP_0_TLB_HI # fetch the hi entry
|
|
||||||
_MFC0 ta0, COP_0_TLB_LO0 # See what we got
|
|
||||||
_MFC0 ta1, COP_0_TLB_LO1 # See what we got
|
|
||||||
_MTC0 t0, COP_0_TLB_HI # restore PID
|
|
||||||
HAZARD_DELAY
|
|
||||||
mtc0 v1, COP_0_STATUS_REG # Restore the status register
|
|
||||||
ITLBNOPFIX
|
|
||||||
sw t2, 0(a1)
|
|
||||||
sw t3, 4(a1)
|
|
||||||
sw ta0, 8(a1)
|
|
||||||
j ra
|
|
||||||
sw ta1, 12(a1)
|
|
||||||
END(Mips_TLBRead)
|
|
||||||
|
|
||||||
/*--------------------------------------------------------------------------
|
|
||||||
*
|
|
||||||
* Mips_TLBGetPID(void);
|
|
||||||
*
|
|
||||||
* Results:
|
|
||||||
* Returns the current TLB pid reg.
|
|
||||||
*
|
|
||||||
* Side effects:
|
|
||||||
* None.
|
|
||||||
*
|
|
||||||
*--------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
LEAF(Mips_TLBGetPID)
|
|
||||||
_MFC0 v0, COP_0_TLB_HI # get PID
|
|
||||||
j ra
|
|
||||||
and v0, v0, VMTLB_PID # mask off PID
|
|
||||||
END(Mips_TLBGetPID)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/*--------------------------------------------------------------------------
|
|
||||||
*
|
|
||||||
* void mips_TBIAP(int sizeofTLB);
|
|
||||||
*
|
|
||||||
* Invalidate TLB entries belong to per process user spaces while
|
|
||||||
* leaving entries for kernel space marked global intact.
|
|
||||||
*
|
|
||||||
*--------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
LEAF(mips_TBIAP)
|
|
||||||
mfc0 v1, COP_0_STATUS_REG # save status register
|
|
||||||
mtc0 zero, COP_0_STATUS_REG # disable interrupts
|
|
||||||
|
|
||||||
_MFC0 ta0, COP_0_TLB_HI # Get current PID
|
|
||||||
move t2, a0
|
|
||||||
mfc0 t1, COP_0_TLB_WIRED
|
|
||||||
#
|
|
||||||
# Load invalid entry, each TLB entry should have it's own bogus
|
|
||||||
# address calculated by following expression:
|
|
||||||
# MIPS_KSEG0_START + 2 * i * PAGE_SIZE;
|
|
||||||
# One bogus value for every TLB entry might cause MCHECK exception
|
|
||||||
#
|
|
||||||
sll t3, t1, PAGE_SHIFT + 1
|
|
||||||
li v0, MIPS_KSEG0_START # invalid address
|
|
||||||
addu v0, t3
|
|
||||||
|
|
||||||
mfc0 t3, COP_0_TLB_PG_MASK # save current pgMask
|
|
||||||
|
|
||||||
# do {} while (t1 < t2)
|
|
||||||
1:
|
|
||||||
mtc0 t1, COP_0_TLB_INDEX # set index
|
|
||||||
HAZARD_DELAY
|
|
||||||
tlbr # obtain an entry
|
|
||||||
HAZARD_DELAY
|
|
||||||
_MFC0 a0, COP_0_TLB_LO1
|
|
||||||
and a0, a0, PTE_G # check to see it has G bit
|
|
||||||
bnez a0, 2f
|
|
||||||
nop
|
|
||||||
|
|
||||||
_MTC0 v0, COP_0_TLB_HI # make entryHi invalid
|
|
||||||
_MTC0 zero, COP_0_TLB_LO0 # zero out entryLo0
|
|
||||||
_MTC0 zero, COP_0_TLB_LO1 # zero out entryLo1
|
|
||||||
mtc0 zero, COP_0_TLB_PG_MASK # zero out mask entry
|
|
||||||
HAZARD_DELAY
|
|
||||||
tlbwi # invalidate the TLB entry
|
|
||||||
2:
|
|
||||||
addu t1, t1, 1
|
|
||||||
addu v0, 1 << (PAGE_SHIFT + 1)
|
|
||||||
bne t1, t2, 1b
|
|
||||||
nop
|
|
||||||
|
|
||||||
_MTC0 ta0, COP_0_TLB_HI # restore PID
|
|
||||||
mtc0 t3, COP_0_TLB_PG_MASK # restore pgMask
|
|
||||||
HAZARD_DELAY
|
|
||||||
mtc0 v1, COP_0_STATUS_REG # restore status register
|
|
||||||
j ra # new ASID will be set soon
|
|
||||||
nop
|
|
||||||
.set mips2
|
|
||||||
END(mips_TBIAP)
|
|
||||||
Loading…
Reference in New Issue
Block a user