Merge the amd64 and i386 identcpu.c into a single x86 implementation.
This brings the structured extended features mask and VT-x reporting to i386 and Intel cache and TLB info (under bootverbose) to amd64.
This commit is contained in:
parent
f5a76413fe
commit
33a50f1b0f
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=271098
@ -1,916 +0,0 @@
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/*-
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* Copyright (c) 1992 Terrence R. Lambert.
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* Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
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* Copyright (c) 1997 KATO Takenori.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_cpu.h"
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/eventhandler.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/sysctl.h>
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#include <sys/power.h>
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#include <machine/asmacros.h>
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#include <machine/clock.h>
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#include <machine/cputypes.h>
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#include <machine/frame.h>
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#include <machine/intr_machdep.h>
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#include <machine/segments.h>
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#include <machine/specialreg.h>
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#include <machine/md_var.h>
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#include <amd64/vmm/intel/vmx_controls.h>
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#include <x86/isa/icu.h>
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static u_int find_cpu_vendor_id(void);
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static void print_AMD_info(void);
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static void print_via_padlock_info(void);
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static void print_vmx_info(void);
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int cpu_class;
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char machine[] = "amd64";
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#ifdef SCTL_MASK32
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extern int adaptive_machine_arch;
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#endif
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static int
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sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
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{
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#ifdef SCTL_MASK32
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static const char machine32[] = "i386";
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#endif
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int error;
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#ifdef SCTL_MASK32
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if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
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error = SYSCTL_OUT(req, machine32, sizeof(machine32));
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else
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#endif
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error = SYSCTL_OUT(req, machine, sizeof(machine));
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return (error);
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}
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SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD,
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NULL, 0, sysctl_hw_machine, "A", "Machine class");
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static char cpu_model[128];
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SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
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cpu_model, 0, "Machine model");
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static int hw_clockrate;
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SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
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&hw_clockrate, 0, "CPU instruction clock rate");
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static eventhandler_tag tsc_post_tag;
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static char cpu_brand[48];
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static struct {
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char *cpu_name;
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int cpu_class;
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} amd64_cpus[] = {
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{ "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */
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{ "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */
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};
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static struct {
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char *vendor;
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u_int vendor_id;
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} cpu_vendors[] = {
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{ INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
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{ AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
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{ CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
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};
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void
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printcpuinfo(void)
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{
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u_int regs[4], i;
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char *brand;
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cpu_class = amd64_cpus[cpu].cpu_class;
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printf("CPU: ");
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strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model));
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/* Check for extended CPUID information and a processor name. */
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if (cpu_exthigh >= 0x80000004) {
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brand = cpu_brand;
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for (i = 0x80000002; i < 0x80000005; i++) {
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do_cpuid(i, regs);
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memcpy(brand, regs, sizeof(regs));
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brand += sizeof(regs);
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}
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}
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switch (cpu_vendor_id) {
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case CPU_VENDOR_INTEL:
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/* Please make up your mind folks! */
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strcat(cpu_model, "EM64T");
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break;
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case CPU_VENDOR_AMD:
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/*
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* Values taken from AMD Processor Recognition
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* http://www.amd.com/K6/k6docs/pdf/20734g.pdf
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* (also describes ``Features'' encodings.
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*/
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strcpy(cpu_model, "AMD ");
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if ((cpu_id & 0xf00) == 0xf00)
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strcat(cpu_model, "AMD64 Processor");
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else
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strcat(cpu_model, "Unknown");
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break;
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case CPU_VENDOR_CENTAUR:
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strcpy(cpu_model, "VIA ");
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if ((cpu_id & 0xff0) == 0x6f0)
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strcat(cpu_model, "Nano Processor");
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else
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strcat(cpu_model, "Unknown");
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break;
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default:
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strcat(cpu_model, "Unknown");
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break;
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}
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/*
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* Replace cpu_model with cpu_brand minus leading spaces if
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* we have one.
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*/
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brand = cpu_brand;
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while (*brand == ' ')
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++brand;
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if (*brand != '\0')
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strcpy(cpu_model, brand);
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printf("%s (", cpu_model);
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switch(cpu_class) {
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case CPUCLASS_K8:
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if (tsc_freq != 0) {
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hw_clockrate = (tsc_freq + 5000) / 1000000;
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printf("%jd.%02d-MHz ",
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(intmax_t)(tsc_freq + 4999) / 1000000,
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(u_int)((tsc_freq + 4999) / 10000) % 100);
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}
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printf("K8");
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break;
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default:
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printf("Unknown"); /* will panic below... */
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}
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printf("-class CPU)\n");
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if (*cpu_vendor)
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printf(" Origin=\"%s\"", cpu_vendor);
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if (cpu_id)
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printf(" Id=0x%x", cpu_id);
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if (cpu_vendor_id == CPU_VENDOR_INTEL ||
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cpu_vendor_id == CPU_VENDOR_AMD ||
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cpu_vendor_id == CPU_VENDOR_CENTAUR) {
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printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id));
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printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id));
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printf(" Stepping=%u", cpu_id & CPUID_STEPPING);
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/*
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* AMD CPUID Specification
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* http://support.amd.com/us/Embedded_TechDocs/25481.pdf
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*
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* Intel Processor Identification and CPUID Instruction
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* http://www.intel.com/assets/pdf/appnote/241618.pdf
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*/
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if (cpu_high > 0) {
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/*
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* Here we should probably set up flags indicating
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* whether or not various features are available.
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* The interesting ones are probably VME, PSE, PAE,
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* and PGE. The code already assumes without bothering
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* to check that all CPUs >= Pentium have a TSC and
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* MSRs.
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*/
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printf("\n Features=0x%b", cpu_feature,
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"\020"
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"\001FPU" /* Integral FPU */
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"\002VME" /* Extended VM86 mode support */
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"\003DE" /* Debugging Extensions (CR4.DE) */
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"\004PSE" /* 4MByte page tables */
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"\005TSC" /* Timestamp counter */
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"\006MSR" /* Machine specific registers */
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"\007PAE" /* Physical address extension */
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"\010MCE" /* Machine Check support */
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"\011CX8" /* CMPEXCH8 instruction */
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"\012APIC" /* SMP local APIC */
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"\013oldMTRR" /* Previous implementation of MTRR */
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"\014SEP" /* Fast System Call */
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"\015MTRR" /* Memory Type Range Registers */
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"\016PGE" /* PG_G (global bit) support */
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"\017MCA" /* Machine Check Architecture */
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"\020CMOV" /* CMOV instruction */
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"\021PAT" /* Page attributes table */
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"\022PSE36" /* 36 bit address space support */
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"\023PN" /* Processor Serial number */
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"\024CLFLUSH" /* Has the CLFLUSH instruction */
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"\025<b20>"
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"\026DTS" /* Debug Trace Store */
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"\027ACPI" /* ACPI support */
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"\030MMX" /* MMX instructions */
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"\031FXSR" /* FXSAVE/FXRSTOR */
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"\032SSE" /* Streaming SIMD Extensions */
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"\033SSE2" /* Streaming SIMD Extensions #2 */
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"\034SS" /* Self snoop */
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"\035HTT" /* Hyperthreading (see EBX bit 16-23) */
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"\036TM" /* Thermal Monitor clock slowdown */
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"\037IA64" /* CPU can execute IA64 instructions */
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"\040PBE" /* Pending Break Enable */
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);
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if (cpu_feature2 != 0) {
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printf("\n Features2=0x%b", cpu_feature2,
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"\020"
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"\001SSE3" /* SSE3 */
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"\002PCLMULQDQ" /* Carry-Less Mul Quadword */
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"\003DTES64" /* 64-bit Debug Trace */
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"\004MON" /* MONITOR/MWAIT Instructions */
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"\005DS_CPL" /* CPL Qualified Debug Store */
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"\006VMX" /* Virtual Machine Extensions */
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"\007SMX" /* Safer Mode Extensions */
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"\010EST" /* Enhanced SpeedStep */
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"\011TM2" /* Thermal Monitor 2 */
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"\012SSSE3" /* SSSE3 */
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"\013CNXT-ID" /* L1 context ID available */
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"\014<b11>"
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"\015FMA" /* Fused Multiply Add */
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"\016CX16" /* CMPXCHG16B Instruction */
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"\017xTPR" /* Send Task Priority Messages*/
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"\020PDCM" /* Perf/Debug Capability MSR */
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"\021<b16>"
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"\022PCID" /* Process-context Identifiers*/
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"\023DCA" /* Direct Cache Access */
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"\024SSE4.1" /* SSE 4.1 */
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"\025SSE4.2" /* SSE 4.2 */
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"\026x2APIC" /* xAPIC Extensions */
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"\027MOVBE" /* MOVBE Instruction */
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"\030POPCNT" /* POPCNT Instruction */
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"\031TSCDLT" /* TSC-Deadline Timer */
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"\032AESNI" /* AES Crypto */
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"\033XSAVE" /* XSAVE/XRSTOR States */
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"\034OSXSAVE" /* OS-Enabled State Management*/
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"\035AVX" /* Advanced Vector Extensions */
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"\036F16C" /* Half-precision conversions */
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"\037RDRAND" /* RDRAND Instruction */
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"\040HV" /* Hypervisor */
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);
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}
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if (amd_feature != 0) {
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printf("\n AMD Features=0x%b", amd_feature,
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"\020" /* in hex */
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"\001<s0>" /* Same */
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"\002<s1>" /* Same */
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"\003<s2>" /* Same */
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"\004<s3>" /* Same */
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"\005<s4>" /* Same */
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"\006<s5>" /* Same */
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"\007<s6>" /* Same */
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"\010<s7>" /* Same */
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"\011<s8>" /* Same */
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"\012<s9>" /* Same */
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"\013<b10>" /* Undefined */
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"\014SYSCALL" /* Have SYSCALL/SYSRET */
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"\015<s12>" /* Same */
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"\016<s13>" /* Same */
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"\017<s14>" /* Same */
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"\020<s15>" /* Same */
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"\021<s16>" /* Same */
|
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"\022<s17>" /* Same */
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"\023<b18>" /* Reserved, unknown */
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"\024MP" /* Multiprocessor Capable */
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"\025NX" /* Has EFER.NXE, NX */
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"\026<b21>" /* Undefined */
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"\027MMX+" /* AMD MMX Extensions */
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"\030<s23>" /* Same */
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"\031<s24>" /* Same */
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"\032FFXSR" /* Fast FXSAVE/FXRSTOR */
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"\033Page1GB" /* 1-GB large page support */
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"\034RDTSCP" /* RDTSCP */
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"\035<b28>" /* Undefined */
|
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"\036LM" /* 64 bit long mode */
|
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"\0373DNow!+" /* AMD 3DNow! Extensions */
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"\0403DNow!" /* AMD 3DNow! */
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);
|
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}
|
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|
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if (amd_feature2 != 0) {
|
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printf("\n AMD Features2=0x%b", amd_feature2,
|
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"\020"
|
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"\001LAHF" /* LAHF/SAHF in long mode */
|
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"\002CMP" /* CMP legacy */
|
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"\003SVM" /* Secure Virtual Mode */
|
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"\004ExtAPIC" /* Extended APIC register */
|
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"\005CR8" /* CR8 in legacy mode */
|
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"\006ABM" /* LZCNT instruction */
|
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"\007SSE4A" /* SSE4A */
|
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"\010MAS" /* Misaligned SSE mode */
|
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"\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
|
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"\012OSVW" /* OS visible workaround */
|
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"\013IBS" /* Instruction based sampling */
|
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"\014XOP" /* XOP extended instructions */
|
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"\015SKINIT" /* SKINIT/STGI */
|
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"\016WDT" /* Watchdog timer */
|
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"\017<b14>"
|
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"\020LWP" /* Lightweight Profiling */
|
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"\021FMA4" /* 4-operand FMA instructions */
|
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"\022TCE" /* Translation Cache Extension */
|
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"\023<b18>"
|
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"\024NodeId" /* NodeId MSR support */
|
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"\025<b20>"
|
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"\026TBM" /* Trailing Bit Manipulation */
|
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"\027Topology" /* Topology Extensions */
|
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"\030PCXC" /* Core perf count */
|
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"\031PNXC" /* NB perf count */
|
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"\032<b25>"
|
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"\033DBE" /* Data Breakpoint extension */
|
||||
"\034PTSC" /* Performance TSC */
|
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"\035PL2I" /* L2I perf count */
|
||||
"\036<b29>"
|
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"\037<b30>"
|
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"\040<b31>"
|
||||
);
|
||||
}
|
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|
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if (cpu_stdext_feature != 0) {
|
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printf("\n Structured Extended Features=0x%b",
|
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cpu_stdext_feature,
|
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"\020"
|
||||
/* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
|
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"\001FSGSBASE"
|
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"\002TSCADJ"
|
||||
/* Bit Manipulation Instructions */
|
||||
"\004BMI1"
|
||||
/* Hardware Lock Elision */
|
||||
"\005HLE"
|
||||
/* Advanced Vector Instructions 2 */
|
||||
"\006AVX2"
|
||||
/* Supervisor Mode Execution Prot. */
|
||||
"\010SMEP"
|
||||
/* Bit Manipulation Instructions */
|
||||
"\011BMI2"
|
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"\012ERMS"
|
||||
/* Invalidate Processor Context ID */
|
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"\013INVPCID"
|
||||
/* Restricted Transactional Memory */
|
||||
"\014RTM"
|
||||
/* Intel Memory Protection Extensions */
|
||||
"\017MPX"
|
||||
/* AVX512 Foundation */
|
||||
"\021AVX512F"
|
||||
/* Enhanced NRBG */
|
||||
"\023RDSEED"
|
||||
/* ADCX + ADOX */
|
||||
"\024ADX"
|
||||
/* Supervisor Mode Access Prevention */
|
||||
"\025SMAP"
|
||||
"\030CLFLUSHOPT"
|
||||
"\032PROCTRACE"
|
||||
"\033AVX512PF"
|
||||
"\034AVX512ER"
|
||||
"\035AVX512CD"
|
||||
"\036SHA"
|
||||
);
|
||||
}
|
||||
|
||||
if (via_feature_rng != 0 || via_feature_xcrypt != 0)
|
||||
print_via_padlock_info();
|
||||
|
||||
if (cpu_feature2 & CPUID2_VMX)
|
||||
print_vmx_info();
|
||||
|
||||
if ((cpu_feature & CPUID_HTT) &&
|
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cpu_vendor_id == CPU_VENDOR_AMD)
|
||||
cpu_feature &= ~CPUID_HTT;
|
||||
|
||||
/*
|
||||
* If this CPU supports P-state invariant TSC then
|
||||
* mention the capability.
|
||||
*/
|
||||
if (tsc_is_invariant) {
|
||||
printf("\n TSC: P-state invariant");
|
||||
if (tsc_perf_stat)
|
||||
printf(", performance statistics");
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
/* Avoid ugly blank lines: only print newline when we have to. */
|
||||
if (*cpu_vendor || cpu_id)
|
||||
printf("\n");
|
||||
|
||||
if (!bootverbose)
|
||||
return;
|
||||
|
||||
if (cpu_vendor_id == CPU_VENDOR_AMD)
|
||||
print_AMD_info();
|
||||
}
|
||||
|
||||
void
|
||||
panicifcpuunsupported(void)
|
||||
{
|
||||
|
||||
#ifndef HAMMER
|
||||
#error "You need to specify a cpu type"
|
||||
#endif
|
||||
/*
|
||||
* Now that we have told the user what they have,
|
||||
* let them know if that machine type isn't configured.
|
||||
*/
|
||||
switch (cpu_class) {
|
||||
case CPUCLASS_X86:
|
||||
#ifndef HAMMER
|
||||
case CPUCLASS_K8:
|
||||
#endif
|
||||
panic("CPU class not configured");
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Update TSC freq with the value indicated by the caller. */
|
||||
static void
|
||||
tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
|
||||
{
|
||||
|
||||
/* If there was an error during the transition, don't do anything. */
|
||||
if (status != 0)
|
||||
return;
|
||||
|
||||
/* Total setting for this level gives the new frequency in MHz. */
|
||||
hw_clockrate = level->total_set.freq;
|
||||
}
|
||||
|
||||
static void
|
||||
hook_tsc_freq(void *arg __unused)
|
||||
{
|
||||
|
||||
if (tsc_is_invariant)
|
||||
return;
|
||||
|
||||
tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
|
||||
tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
|
||||
}
|
||||
|
||||
SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
|
||||
|
||||
/*
|
||||
* Final stage of CPU identification.
|
||||
*/
|
||||
void
|
||||
identify_cpu(void)
|
||||
{
|
||||
u_int regs[4], cpu_stdext_disable;
|
||||
|
||||
do_cpuid(0, regs);
|
||||
cpu_high = regs[0];
|
||||
((u_int *)&cpu_vendor)[0] = regs[1];
|
||||
((u_int *)&cpu_vendor)[1] = regs[3];
|
||||
((u_int *)&cpu_vendor)[2] = regs[2];
|
||||
cpu_vendor[12] = '\0';
|
||||
cpu_vendor_id = find_cpu_vendor_id();
|
||||
|
||||
do_cpuid(1, regs);
|
||||
cpu_id = regs[0];
|
||||
cpu_procinfo = regs[1];
|
||||
cpu_feature = regs[3];
|
||||
cpu_feature2 = regs[2];
|
||||
|
||||
/*
|
||||
* Clear "Limit CPUID Maxval" bit and get the largest standard CPUID
|
||||
* function number again if it is set from BIOS. It is necessary
|
||||
* for probing correct CPU topology later.
|
||||
* XXX This is only done on the BSP package.
|
||||
*/
|
||||
if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4) {
|
||||
uint64_t msr;
|
||||
msr = rdmsr(MSR_IA32_MISC_ENABLE);
|
||||
if ((msr & 0x400000ULL) != 0) {
|
||||
wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL);
|
||||
do_cpuid(0, regs);
|
||||
cpu_high = regs[0];
|
||||
}
|
||||
}
|
||||
|
||||
if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
|
||||
do_cpuid(5, regs);
|
||||
cpu_mon_mwait_flags = regs[2];
|
||||
cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE;
|
||||
cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE;
|
||||
}
|
||||
|
||||
if (cpu_high >= 7) {
|
||||
cpuid_count(7, 0, regs);
|
||||
cpu_stdext_feature = regs[1];
|
||||
|
||||
/*
|
||||
* Some hypervisors fail to filter out unsupported
|
||||
* extended features. For now, disable the
|
||||
* extensions, activation of which requires setting a
|
||||
* bit in CR4, and which VM monitors do not support.
|
||||
*/
|
||||
if (cpu_feature2 & CPUID2_HV) {
|
||||
cpu_stdext_disable = CPUID_STDEXT_FSGSBASE |
|
||||
CPUID_STDEXT_SMEP;
|
||||
} else
|
||||
cpu_stdext_disable = 0;
|
||||
TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
|
||||
cpu_stdext_feature &= ~cpu_stdext_disable;
|
||||
}
|
||||
|
||||
if (cpu_vendor_id == CPU_VENDOR_INTEL ||
|
||||
cpu_vendor_id == CPU_VENDOR_AMD ||
|
||||
cpu_vendor_id == CPU_VENDOR_CENTAUR) {
|
||||
do_cpuid(0x80000000, regs);
|
||||
cpu_exthigh = regs[0];
|
||||
}
|
||||
if (cpu_exthigh >= 0x80000001) {
|
||||
do_cpuid(0x80000001, regs);
|
||||
amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
|
||||
amd_feature2 = regs[2];
|
||||
}
|
||||
if (cpu_exthigh >= 0x80000007) {
|
||||
do_cpuid(0x80000007, regs);
|
||||
amd_pminfo = regs[3];
|
||||
}
|
||||
if (cpu_exthigh >= 0x80000008) {
|
||||
do_cpuid(0x80000008, regs);
|
||||
cpu_procinfo2 = regs[2];
|
||||
}
|
||||
|
||||
/* XXX */
|
||||
cpu = CPU_CLAWHAMMER;
|
||||
}
|
||||
|
||||
static u_int
|
||||
find_cpu_vendor_id(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++)
|
||||
if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
|
||||
return (cpu_vendors[i].vendor_id);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
print_AMD_assoc(int i)
|
||||
{
|
||||
if (i == 255)
|
||||
printf(", fully associative\n");
|
||||
else
|
||||
printf(", %d-way associative\n", i);
|
||||
}
|
||||
|
||||
static void
|
||||
print_AMD_l2_assoc(int i)
|
||||
{
|
||||
switch (i & 0x0f) {
|
||||
case 0: printf(", disabled/not present\n"); break;
|
||||
case 1: printf(", direct mapped\n"); break;
|
||||
case 2: printf(", 2-way associative\n"); break;
|
||||
case 4: printf(", 4-way associative\n"); break;
|
||||
case 6: printf(", 8-way associative\n"); break;
|
||||
case 8: printf(", 16-way associative\n"); break;
|
||||
case 15: printf(", fully associative\n"); break;
|
||||
default: printf(", reserved configuration\n"); break;
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
print_AMD_info(void)
|
||||
{
|
||||
u_int regs[4];
|
||||
|
||||
if (cpu_exthigh < 0x80000005)
|
||||
return;
|
||||
|
||||
do_cpuid(0x80000005, regs);
|
||||
printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
|
||||
print_AMD_assoc(regs[0] >> 24);
|
||||
|
||||
printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
|
||||
print_AMD_assoc((regs[0] >> 8) & 0xff);
|
||||
|
||||
printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
|
||||
print_AMD_assoc(regs[1] >> 24);
|
||||
|
||||
printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
|
||||
print_AMD_assoc((regs[1] >> 8) & 0xff);
|
||||
|
||||
printf("L1 data cache: %d kbytes", regs[2] >> 24);
|
||||
printf(", %d bytes/line", regs[2] & 0xff);
|
||||
printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
|
||||
print_AMD_assoc((regs[2] >> 16) & 0xff);
|
||||
|
||||
printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
|
||||
printf(", %d bytes/line", regs[3] & 0xff);
|
||||
printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
|
||||
print_AMD_assoc((regs[3] >> 16) & 0xff);
|
||||
|
||||
if (cpu_exthigh >= 0x80000006) {
|
||||
do_cpuid(0x80000006, regs);
|
||||
if ((regs[0] >> 16) != 0) {
|
||||
printf("L2 2MB data TLB: %d entries",
|
||||
(regs[0] >> 16) & 0xfff);
|
||||
print_AMD_l2_assoc(regs[0] >> 28);
|
||||
printf("L2 2MB instruction TLB: %d entries",
|
||||
regs[0] & 0xfff);
|
||||
print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
|
||||
} else {
|
||||
printf("L2 2MB unified TLB: %d entries",
|
||||
regs[0] & 0xfff);
|
||||
print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
|
||||
}
|
||||
if ((regs[1] >> 16) != 0) {
|
||||
printf("L2 4KB data TLB: %d entries",
|
||||
(regs[1] >> 16) & 0xfff);
|
||||
print_AMD_l2_assoc(regs[1] >> 28);
|
||||
|
||||
printf("L2 4KB instruction TLB: %d entries",
|
||||
(regs[1] >> 16) & 0xfff);
|
||||
print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
|
||||
} else {
|
||||
printf("L2 4KB unified TLB: %d entries",
|
||||
(regs[1] >> 16) & 0xfff);
|
||||
print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
|
||||
}
|
||||
printf("L2 unified cache: %d kbytes", regs[2] >> 16);
|
||||
printf(", %d bytes/line", regs[2] & 0xff);
|
||||
printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
|
||||
print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
|
||||
}
|
||||
|
||||
/*
|
||||
* Opteron Rev E shows a bug as in very rare occasions a read memory
|
||||
* barrier is not performed as expected if it is followed by a
|
||||
* non-atomic read-modify-write instruction.
|
||||
* As long as that bug pops up very rarely (intensive machine usage
|
||||
* on other operating systems generally generates one unexplainable
|
||||
* crash any 2 months) and as long as a model specific fix would be
|
||||
* impratical at this stage, print out a warning string if the broken
|
||||
* model and family are identified.
|
||||
*/
|
||||
if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
|
||||
CPUID_TO_MODEL(cpu_id) <= 0x3f)
|
||||
printf("WARNING: This architecture revision has known SMP "
|
||||
"hardware bugs which may cause random instability\n");
|
||||
}
|
||||
|
||||
static void
|
||||
print_via_padlock_info(void)
|
||||
{
|
||||
u_int regs[4];
|
||||
|
||||
do_cpuid(0xc0000001, regs);
|
||||
printf("\n VIA Padlock Features=0x%b", regs[3],
|
||||
"\020"
|
||||
"\003RNG" /* RNG */
|
||||
"\007AES" /* ACE */
|
||||
"\011AES-CTR" /* ACE2 */
|
||||
"\013SHA1,SHA256" /* PHE */
|
||||
"\015RSA" /* PMM */
|
||||
);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
vmx_settable(uint64_t basic, int msr, int true_msr)
|
||||
{
|
||||
uint64_t val;
|
||||
|
||||
if (basic & (1UL << 55))
|
||||
val = rdmsr(true_msr);
|
||||
else
|
||||
val = rdmsr(msr);
|
||||
|
||||
/* Just report the controls that can be set to 1. */
|
||||
return (val >> 32);
|
||||
}
|
||||
|
||||
static void
|
||||
print_vmx_info(void)
|
||||
{
|
||||
uint64_t basic, msr;
|
||||
uint32_t entry, exit, mask, pin, proc, proc2;
|
||||
int comma;
|
||||
|
||||
printf("\n VT-x: ");
|
||||
msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
|
||||
if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
|
||||
printf("(disabled in BIOS) ");
|
||||
basic = rdmsr(MSR_VMX_BASIC);
|
||||
pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
|
||||
MSR_VMX_TRUE_PINBASED_CTLS);
|
||||
proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
|
||||
MSR_VMX_TRUE_PROCBASED_CTLS);
|
||||
if (proc & PROCBASED_SECONDARY_CONTROLS)
|
||||
proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
|
||||
MSR_VMX_PROCBASED_CTLS2);
|
||||
else
|
||||
proc2 = 0;
|
||||
exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
|
||||
entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
|
||||
|
||||
if (!bootverbose) {
|
||||
comma = 0;
|
||||
if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
|
||||
entry & VM_ENTRY_LOAD_PAT) {
|
||||
printf("%sPAT", comma ? "," : "");
|
||||
comma = 1;
|
||||
}
|
||||
if (proc & PROCBASED_HLT_EXITING) {
|
||||
printf("%sHLT", comma ? "," : "");
|
||||
comma = 1;
|
||||
}
|
||||
if (proc & PROCBASED_MTF) {
|
||||
printf("%sMTF", comma ? "," : "");
|
||||
comma = 1;
|
||||
}
|
||||
if (proc & PROCBASED_PAUSE_EXITING) {
|
||||
printf("%sPAUSE", comma ? "," : "");
|
||||
comma = 1;
|
||||
}
|
||||
if (proc2 & PROCBASED2_ENABLE_EPT) {
|
||||
printf("%sEPT", comma ? "," : "");
|
||||
comma = 1;
|
||||
}
|
||||
if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
|
||||
printf("%sUG", comma ? "," : "");
|
||||
comma = 1;
|
||||
}
|
||||
if (proc2 & PROCBASED2_ENABLE_VPID) {
|
||||
printf("%sVPID", comma ? "," : "");
|
||||
comma = 1;
|
||||
}
|
||||
if (proc & PROCBASED_USE_TPR_SHADOW &&
|
||||
proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
|
||||
proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
|
||||
proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
|
||||
proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
|
||||
printf("%sVID", comma ? "," : "");
|
||||
comma = 1;
|
||||
if (pin & PINBASED_POSTED_INTERRUPT)
|
||||
printf(",PostIntr");
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
mask = basic >> 32;
|
||||
printf("Basic Features=0x%b", mask,
|
||||
"\020"
|
||||
"\02132PA" /* 32-bit physical addresses */
|
||||
"\022SMM" /* SMM dual-monitor */
|
||||
"\027INS/OUTS" /* VM-exit info for INS and OUTS */
|
||||
"\030TRUE" /* TRUE_CTLS MSRs */
|
||||
);
|
||||
printf("\n Pin-Based Controls=0x%b", pin,
|
||||
"\020"
|
||||
"\001ExtINT" /* External-interrupt exiting */
|
||||
"\004NMI" /* NMI exiting */
|
||||
"\006VNMI" /* Virtual NMIs */
|
||||
"\007PreTmr" /* Activate VMX-preemption timer */
|
||||
"\010PostIntr" /* Process posted interrupts */
|
||||
);
|
||||
printf("\n Primary Processor Controls=0x%b", proc,
|
||||
"\020"
|
||||
"\003INTWIN" /* Interrupt-window exiting */
|
||||
"\004TSCOff" /* Use TSC offsetting */
|
||||
"\010HLT" /* HLT exiting */
|
||||
"\012INVLPG" /* INVLPG exiting */
|
||||
"\013MWAIT" /* MWAIT exiting */
|
||||
"\014RDPMC" /* RDPMC exiting */
|
||||
"\015RDTSC" /* RDTSC exiting */
|
||||
"\020CR3-LD" /* CR3-load exiting */
|
||||
"\021CR3-ST" /* CR3-store exiting */
|
||||
"\024CR8-LD" /* CR8-load exiting */
|
||||
"\025CR8-ST" /* CR8-store exiting */
|
||||
"\026TPR" /* Use TPR shadow */
|
||||
"\027NMIWIN" /* NMI-window exiting */
|
||||
"\030MOV-DR" /* MOV-DR exiting */
|
||||
"\031IO" /* Unconditional I/O exiting */
|
||||
"\032IOmap" /* Use I/O bitmaps */
|
||||
"\034MTF" /* Monitor trap flag */
|
||||
"\035MSRmap" /* Use MSR bitmaps */
|
||||
"\036MONITOR" /* MONITOR exiting */
|
||||
"\037PAUSE" /* PAUSE exiting */
|
||||
);
|
||||
if (proc & PROCBASED_SECONDARY_CONTROLS)
|
||||
printf("\n Secondary Processor Controls=0x%b", proc2,
|
||||
"\020"
|
||||
"\001APIC" /* Virtualize APIC accesses */
|
||||
"\002EPT" /* Enable EPT */
|
||||
"\003DT" /* Descriptor-table exiting */
|
||||
"\004RDTSCP" /* Enable RDTSCP */
|
||||
"\005x2APIC" /* Virtualize x2APIC mode */
|
||||
"\006VPID" /* Enable VPID */
|
||||
"\007WBINVD" /* WBINVD exiting */
|
||||
"\010UG" /* Unrestricted guest */
|
||||
"\011APIC-reg" /* APIC-register virtualization */
|
||||
"\012VID" /* Virtual-interrupt delivery */
|
||||
"\013PAUSE-loop" /* PAUSE-loop exiting */
|
||||
"\014RDRAND" /* RDRAND exiting */
|
||||
"\015INVPCID" /* Enable INVPCID */
|
||||
"\016VMFUNC" /* Enable VM functions */
|
||||
"\017VMCS" /* VMCS shadowing */
|
||||
"\020EPT#VE" /* EPT-violation #VE */
|
||||
"\021XSAVES" /* Enable XSAVES/XRSTORS */
|
||||
);
|
||||
printf("\n Exit Controls=0x%b", mask,
|
||||
"\020"
|
||||
"\003DR" /* Save debug controls */
|
||||
/* Ignore Host address-space size */
|
||||
"\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */
|
||||
"\020AckInt" /* Acknowledge interrupt on exit */
|
||||
"\023PAT-SV" /* Save MSR_PAT */
|
||||
"\024PAT-LD" /* Load MSR_PAT */
|
||||
"\025EFER-SV" /* Save MSR_EFER */
|
||||
"\026EFER-LD" /* Load MSR_EFER */
|
||||
"\027PTMR-SV" /* Save VMX-preemption timer value */
|
||||
);
|
||||
printf("\n Entry Controls=0x%b", mask,
|
||||
"\020"
|
||||
"\003DR" /* Save debug controls */
|
||||
/* Ignore IA-32e mode guest */
|
||||
/* Ignore Entry to SMM */
|
||||
/* Ignore Deactivate dual-monitor treatment */
|
||||
"\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */
|
||||
"\017PAT" /* Load MSR_PAT */
|
||||
"\020EFER" /* Load MSR_EFER */
|
||||
);
|
||||
if (proc & PROCBASED_SECONDARY_CONTROLS &&
|
||||
(proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
|
||||
msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
|
||||
mask = msr;
|
||||
printf("\n EPT Features=0x%b", mask,
|
||||
"\020"
|
||||
"\001XO" /* Execute-only translations */
|
||||
"\007PW4" /* Page-walk length of 4 */
|
||||
"\011UC" /* EPT paging-structure mem can be UC */
|
||||
"\017WB" /* EPT paging-structure mem can be WB */
|
||||
"\0212M" /* EPT PDE can map a 2-Mbyte page */
|
||||
"\0221G" /* EPT PDPTE can map a 1-Gbyte page */
|
||||
"\025INVEPT" /* INVEPT is supported */
|
||||
"\026AD" /* Accessed and dirty flags for EPT */
|
||||
"\032single" /* INVEPT single-context type */
|
||||
"\033all" /* INVEPT all-context type */
|
||||
);
|
||||
mask = msr >> 32;
|
||||
printf("\n VPID Features=0x%b", mask,
|
||||
"\020"
|
||||
"\001INVVPID" /* INVVPID is supported */
|
||||
"\011individual" /* INVVPID individual-address type */
|
||||
"\012single" /* INVVPID single-context type */
|
||||
"\013all" /* INVVPID all-context type */
|
||||
/* INVVPID single-context-retaining-globals type */
|
||||
"\014single-globals"
|
||||
);
|
||||
}
|
||||
}
|
@ -103,7 +103,6 @@ amd64/amd64/elf_machdep.c standard
|
||||
amd64/amd64/exception.S standard
|
||||
amd64/amd64/fpu.c standard
|
||||
amd64/amd64/gdb_machdep.c optional gdb
|
||||
amd64/amd64/identcpu.c standard
|
||||
amd64/amd64/in_cksum.c optional inet | inet6
|
||||
amd64/amd64/initcpu.c standard
|
||||
amd64/amd64/io.c optional io
|
||||
@ -542,6 +541,7 @@ x86/x86/busdma_bounce.c standard
|
||||
x86/x86/busdma_machdep.c standard
|
||||
x86/x86/dump_machdep.c standard
|
||||
x86/x86/fdt_machdep.c optional fdt
|
||||
x86/x86/identcpu.c standard
|
||||
x86/x86/intr_machdep.c standard
|
||||
x86/x86/io_apic.c standard
|
||||
x86/x86/legacy.c standard
|
||||
|
@ -443,7 +443,6 @@ i386/xen/exception.s optional xen
|
||||
i386/i386/gdb_machdep.c optional gdb
|
||||
i386/i386/geode.c optional cpu_geode
|
||||
i386/i386/i686_mem.c optional mem
|
||||
i386/i386/identcpu.c standard
|
||||
i386/i386/in_cksum.c optional inet | inet6
|
||||
i386/i386/initcpu.c standard
|
||||
i386/i386/io.c optional io
|
||||
@ -581,6 +580,7 @@ x86/x86/busdma_bounce.c standard
|
||||
x86/x86/busdma_machdep.c standard
|
||||
x86/x86/dump_machdep.c standard
|
||||
x86/x86/fdt_machdep.c optional fdt
|
||||
x86/x86/identcpu.c standard
|
||||
x86/x86/intr_machdep.c standard
|
||||
x86/x86/io_apic.c optional apic
|
||||
x86/x86/legacy.c optional native
|
||||
|
@ -140,7 +140,6 @@ i386/i386/elf_machdep.c standard
|
||||
i386/i386/exception.s standard
|
||||
i386/i386/gdb_machdep.c optional gdb
|
||||
i386/i386/i686_mem.c optional mem
|
||||
i386/i386/identcpu.c standard
|
||||
i386/i386/in_cksum.c optional inet | inet6
|
||||
i386/i386/initcpu.c standard
|
||||
i386/i386/io.c optional io
|
||||
@ -248,6 +247,7 @@ x86/pci/pci_bus.c optional pci
|
||||
x86/x86/busdma_bounce.c standard
|
||||
x86/x86/busdma_machdep.c standard
|
||||
x86/x86/dump_machdep.c standard
|
||||
x86/x86/identcpu.c standard
|
||||
x86/x86/intr_machdep.c standard
|
||||
x86/x86/io_apic.c optional apic
|
||||
x86/x86/legacy.c standard
|
||||
|
@ -95,6 +95,7 @@ u_int cpu_fxsr; /* SSE enabled */
|
||||
u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
|
||||
#endif
|
||||
u_int cpu_clflush_line_size = 32;
|
||||
u_int cpu_stdext_feature;
|
||||
u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
|
||||
u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
|
||||
u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
|
||||
|
@ -48,6 +48,7 @@ extern u_int amd_pminfo;
|
||||
extern u_int via_feature_rng;
|
||||
extern u_int via_feature_xcrypt;
|
||||
extern u_int cpu_clflush_line_size;
|
||||
extern u_int cpu_stdext_feature;
|
||||
extern u_int cpu_fxsr;
|
||||
extern u_int cpu_high;
|
||||
extern u_int cpu_id;
|
||||
|
@ -55,27 +55,61 @@ __FBSDID("$FreeBSD$");
|
||||
#include <machine/asmacros.h>
|
||||
#include <machine/clock.h>
|
||||
#include <machine/cputypes.h>
|
||||
#include <machine/frame.h>
|
||||
#include <machine/intr_machdep.h>
|
||||
#include <machine/md_var.h>
|
||||
#include <machine/segments.h>
|
||||
#include <machine/specialreg.h>
|
||||
|
||||
#include <amd64/vmm/intel/vmx_controls.h>
|
||||
#include <x86/isa/icu.h>
|
||||
|
||||
#ifdef __i386__
|
||||
#define IDENTBLUE_CYRIX486 0
|
||||
#define IDENTBLUE_IBMCPU 1
|
||||
#define IDENTBLUE_CYRIXM2 2
|
||||
|
||||
static void identifycyrix(void);
|
||||
static void print_transmeta_info(void);
|
||||
#endif
|
||||
static u_int find_cpu_vendor_id(void);
|
||||
static void print_AMD_info(void);
|
||||
static void print_INTEL_info(void);
|
||||
static void print_INTEL_TLB(u_int data);
|
||||
static void print_transmeta_info(void);
|
||||
static void print_via_padlock_info(void);
|
||||
static void print_vmx_info(void);
|
||||
|
||||
int cpu_class;
|
||||
char machine[] = MACHINE;
|
||||
|
||||
#ifdef __amd64__
|
||||
#ifdef SCTL_MASK32
|
||||
extern int adaptive_machine_arch;
|
||||
#endif
|
||||
|
||||
static int
|
||||
sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
|
||||
{
|
||||
#ifdef SCTL_MASK32
|
||||
static const char machine32[] = "i386";
|
||||
#endif
|
||||
int error;
|
||||
|
||||
#ifdef SCTL_MASK32
|
||||
if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
|
||||
error = SYSCTL_OUT(req, machine32, sizeof(machine32));
|
||||
else
|
||||
#endif
|
||||
error = SYSCTL_OUT(req, machine, sizeof(machine));
|
||||
return (error);
|
||||
|
||||
}
|
||||
SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD,
|
||||
NULL, 0, sysctl_hw_machine, "A", "Machine class");
|
||||
#else
|
||||
SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
|
||||
machine, 0, "Machine class");
|
||||
#endif
|
||||
|
||||
static char cpu_model[128];
|
||||
SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
|
||||
@ -89,6 +123,7 @@ static eventhandler_tag tsc_post_tag;
|
||||
|
||||
static char cpu_brand[48];
|
||||
|
||||
#ifdef __i386__
|
||||
#define MAX_BRAND_INDEX 8
|
||||
|
||||
static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
|
||||
@ -102,11 +137,13 @@ static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
|
||||
NULL,
|
||||
"Intel Pentium 4"
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct {
|
||||
char *cpu_name;
|
||||
int cpu_class;
|
||||
} i386_cpus[] = {
|
||||
} cpus[] = {
|
||||
#ifdef __i386__
|
||||
{ "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
|
||||
{ "i386SX", CPUCLASS_386 }, /* CPU_386SX */
|
||||
{ "i386DX", CPUCLASS_386 }, /* CPU_386 */
|
||||
@ -124,6 +161,10 @@ static struct {
|
||||
{ "Pentium II", CPUCLASS_686 }, /* CPU_PII */
|
||||
{ "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
|
||||
{ "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
|
||||
#else
|
||||
{ "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */
|
||||
{ "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct {
|
||||
@ -133,6 +174,7 @@ static struct {
|
||||
{ INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
|
||||
{ AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
|
||||
{ CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
|
||||
#ifdef __i386__
|
||||
{ NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
|
||||
{ CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
|
||||
{ TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
|
||||
@ -144,6 +186,7 @@ static struct {
|
||||
/* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
|
||||
{ "TransmetaCPU", CPU_VENDOR_TRANSMETA },
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
void
|
||||
@ -152,9 +195,9 @@ printcpuinfo(void)
|
||||
u_int regs[4], i;
|
||||
char *brand;
|
||||
|
||||
cpu_class = i386_cpus[cpu].cpu_class;
|
||||
cpu_class = cpus[cpu].cpu_class;
|
||||
printf("CPU: ");
|
||||
strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
|
||||
strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
|
||||
|
||||
/* Check for extended CPUID information and a processor name. */
|
||||
if (cpu_exthigh >= 0x80000004) {
|
||||
@ -166,7 +209,9 @@ printcpuinfo(void)
|
||||
}
|
||||
}
|
||||
|
||||
if (cpu_vendor_id == CPU_VENDOR_INTEL) {
|
||||
switch (cpu_vendor_id) {
|
||||
case CPU_VENDOR_INTEL:
|
||||
#ifdef __i386__
|
||||
if ((cpu_id & 0xf00) > 0x300) {
|
||||
u_int brand_index;
|
||||
|
||||
@ -299,13 +344,19 @@ printcpuinfo(void)
|
||||
cpu_brandtable[brand_index]);
|
||||
}
|
||||
}
|
||||
} else if (cpu_vendor_id == CPU_VENDOR_AMD) {
|
||||
#else
|
||||
/* Please make up your mind folks! */
|
||||
strcat(cpu_model, "EM64T");
|
||||
#endif
|
||||
break;
|
||||
case CPU_VENDOR_AMD:
|
||||
/*
|
||||
* Values taken from AMD Processor Recognition
|
||||
* http://www.amd.com/K6/k6docs/pdf/20734g.pdf
|
||||
* (also describes ``Features'' encodings.
|
||||
*/
|
||||
strcpy(cpu_model, "AMD ");
|
||||
#ifdef __i386__
|
||||
switch (cpu_id & 0xFF0) {
|
||||
case 0x410:
|
||||
strcat(cpu_model, "Standard Am486DX");
|
||||
@ -378,7 +429,15 @@ printcpuinfo(void)
|
||||
enable_K6_wt_alloc();
|
||||
}
|
||||
#endif
|
||||
} else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
|
||||
#else
|
||||
if ((cpu_id & 0xf00) == 0xf00)
|
||||
strcat(cpu_model, "AMD64 Processor");
|
||||
else
|
||||
strcat(cpu_model, "Unknown");
|
||||
#endif
|
||||
break;
|
||||
#ifdef __i386__
|
||||
case CPU_VENDOR_CYRIX:
|
||||
strcpy(cpu_model, "Cyrix ");
|
||||
switch (cpu_id & 0xff0) {
|
||||
case 0x440:
|
||||
@ -514,7 +573,8 @@ printcpuinfo(void)
|
||||
}
|
||||
break;
|
||||
}
|
||||
} else if (cpu_vendor_id == CPU_VENDOR_RISE) {
|
||||
break;
|
||||
case CPU_VENDOR_RISE:
|
||||
strcpy(cpu_model, "Rise ");
|
||||
switch (cpu_id & 0xff0) {
|
||||
case 0x500: /* 6401 and 6441 (Kirin) */
|
||||
@ -524,7 +584,10 @@ printcpuinfo(void)
|
||||
default:
|
||||
strcat(cpu_model, "Unknown");
|
||||
}
|
||||
} else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) {
|
||||
break;
|
||||
#endif
|
||||
case CPU_VENDOR_CENTAUR:
|
||||
#ifdef __i386__
|
||||
switch (cpu_id & 0xff0) {
|
||||
case 0x540:
|
||||
strcpy(cpu_model, "IDT WinChip C6");
|
||||
@ -560,9 +623,19 @@ printcpuinfo(void)
|
||||
default:
|
||||
strcpy(cpu_model, "VIA/IDT Unknown");
|
||||
}
|
||||
} else if (cpu_vendor_id == CPU_VENDOR_IBM) {
|
||||
#else
|
||||
strcpy(cpu_model, "VIA ");
|
||||
if ((cpu_id & 0xff0) == 0x6f0)
|
||||
strcat(cpu_model, "Nano Processor");
|
||||
else
|
||||
strcat(cpu_model, "Unknown");
|
||||
#endif
|
||||
break;
|
||||
#ifdef __i386__
|
||||
case CPU_VENDOR_IBM:
|
||||
strcpy(cpu_model, "Blue Lightning CPU");
|
||||
} else if (cpu_vendor_id == CPU_VENDOR_NSC) {
|
||||
break;
|
||||
case CPU_VENDOR_NSC:
|
||||
switch (cpu_id & 0xff0) {
|
||||
case 0x540:
|
||||
strcpy(cpu_model, "Geode SC1100");
|
||||
@ -572,6 +645,11 @@ printcpuinfo(void)
|
||||
strcpy(cpu_model, "Geode/NSC unknown");
|
||||
break;
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
strcat(cpu_model, "Unknown");
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
@ -585,7 +663,14 @@ printcpuinfo(void)
|
||||
strcpy(cpu_model, brand);
|
||||
|
||||
printf("%s (", cpu_model);
|
||||
if (tsc_freq != 0) {
|
||||
hw_clockrate = (tsc_freq + 5000) / 1000000;
|
||||
printf("%jd.%02d-MHz ",
|
||||
(intmax_t)(tsc_freq + 4999) / 1000000,
|
||||
(u_int)((tsc_freq + 4999) / 10000) % 100);
|
||||
}
|
||||
switch(cpu_class) {
|
||||
#ifdef __i386__
|
||||
case CPUCLASS_286:
|
||||
printf("286");
|
||||
break;
|
||||
@ -599,48 +684,46 @@ printcpuinfo(void)
|
||||
#endif
|
||||
#if defined(I586_CPU)
|
||||
case CPUCLASS_586:
|
||||
if (tsc_freq != 0) {
|
||||
hw_clockrate = (tsc_freq + 5000) / 1000000;
|
||||
printf("%jd.%02d-MHz ",
|
||||
(intmax_t)(tsc_freq + 4999) / 1000000,
|
||||
(u_int)((tsc_freq + 4999) / 10000) % 100);
|
||||
}
|
||||
printf("586");
|
||||
break;
|
||||
#endif
|
||||
#if defined(I686_CPU)
|
||||
case CPUCLASS_686:
|
||||
if (tsc_freq != 0) {
|
||||
hw_clockrate = (tsc_freq + 5000) / 1000000;
|
||||
printf("%jd.%02d-MHz ",
|
||||
(intmax_t)(tsc_freq + 4999) / 1000000,
|
||||
(u_int)((tsc_freq + 4999) / 10000) % 100);
|
||||
}
|
||||
printf("686");
|
||||
break;
|
||||
#endif
|
||||
#else
|
||||
case CPUCLASS_K8:
|
||||
printf("K8");
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
printf("Unknown"); /* will panic below... */
|
||||
}
|
||||
printf("-class CPU)\n");
|
||||
if(*cpu_vendor)
|
||||
printf(" Origin=\"%s\"",cpu_vendor);
|
||||
if(cpu_id)
|
||||
if (*cpu_vendor)
|
||||
printf(" Origin=\"%s\"", cpu_vendor);
|
||||
if (cpu_id)
|
||||
printf(" Id=0x%x", cpu_id);
|
||||
|
||||
if (cpu_vendor_id == CPU_VENDOR_INTEL ||
|
||||
cpu_vendor_id == CPU_VENDOR_AMD ||
|
||||
cpu_vendor_id == CPU_VENDOR_CENTAUR ||
|
||||
#ifdef __i386__
|
||||
cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
|
||||
cpu_vendor_id == CPU_VENDOR_RISE ||
|
||||
cpu_vendor_id == CPU_VENDOR_CENTAUR ||
|
||||
cpu_vendor_id == CPU_VENDOR_NSC ||
|
||||
(cpu_vendor_id == CPU_VENDOR_CYRIX &&
|
||||
((cpu_id & 0xf00) > 0x500))) {
|
||||
(cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
|
||||
#endif
|
||||
0) {
|
||||
printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id));
|
||||
printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id));
|
||||
printf(" Stepping=%u", cpu_id & CPUID_STEPPING);
|
||||
#ifdef __i386__
|
||||
if (cpu_vendor_id == CPU_VENDOR_CYRIX)
|
||||
printf("\n DIR=0x%04x", cyrix_did);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* AMD CPUID Specification
|
||||
* http://support.amd.com/us/Embedded_TechDocs/25481.pdf
|
||||
@ -808,9 +891,53 @@ printcpuinfo(void)
|
||||
);
|
||||
}
|
||||
|
||||
if (cpu_stdext_feature != 0) {
|
||||
printf("\n Structured Extended Features=0x%b",
|
||||
cpu_stdext_feature,
|
||||
"\020"
|
||||
/* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
|
||||
"\001FSGSBASE"
|
||||
"\002TSCADJ"
|
||||
/* Bit Manipulation Instructions */
|
||||
"\004BMI1"
|
||||
/* Hardware Lock Elision */
|
||||
"\005HLE"
|
||||
/* Advanced Vector Instructions 2 */
|
||||
"\006AVX2"
|
||||
/* Supervisor Mode Execution Prot. */
|
||||
"\010SMEP"
|
||||
/* Bit Manipulation Instructions */
|
||||
"\011BMI2"
|
||||
"\012ERMS"
|
||||
/* Invalidate Processor Context ID */
|
||||
"\013INVPCID"
|
||||
/* Restricted Transactional Memory */
|
||||
"\014RTM"
|
||||
/* Intel Memory Protection Extensions */
|
||||
"\017MPX"
|
||||
/* AVX512 Foundation */
|
||||
"\021AVX512F"
|
||||
/* Enhanced NRBG */
|
||||
"\023RDSEED"
|
||||
/* ADCX + ADOX */
|
||||
"\024ADX"
|
||||
/* Supervisor Mode Access Prevention */
|
||||
"\025SMAP"
|
||||
"\030CLFLUSHOPT"
|
||||
"\032PROCTRACE"
|
||||
"\033AVX512PF"
|
||||
"\034AVX512ER"
|
||||
"\035AVX512CD"
|
||||
"\036SHA"
|
||||
);
|
||||
}
|
||||
|
||||
if (via_feature_rng != 0 || via_feature_xcrypt != 0)
|
||||
print_via_padlock_info();
|
||||
|
||||
if (cpu_feature2 & CPUID2_VMX)
|
||||
print_vmx_info();
|
||||
|
||||
if ((cpu_feature & CPUID_HTT) &&
|
||||
cpu_vendor_id == CPU_VENDOR_AMD)
|
||||
cpu_feature &= ~CPUID_HTT;
|
||||
@ -826,6 +953,7 @@ printcpuinfo(void)
|
||||
}
|
||||
|
||||
}
|
||||
#ifdef __i386__
|
||||
} else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
|
||||
printf(" DIR=0x%04x", cyrix_did);
|
||||
printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
|
||||
@ -833,6 +961,7 @@ printcpuinfo(void)
|
||||
#ifndef CYRIX_CACHE_REALLY_WORKS
|
||||
if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
|
||||
printf("\n CPU cache: write-through mode");
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -847,25 +976,34 @@ printcpuinfo(void)
|
||||
print_AMD_info();
|
||||
else if (cpu_vendor_id == CPU_VENDOR_INTEL)
|
||||
print_INTEL_info();
|
||||
#ifdef __i386__
|
||||
else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
|
||||
print_transmeta_info();
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
panicifcpuunsupported(void)
|
||||
{
|
||||
|
||||
#ifdef __i386__
|
||||
#if !defined(lint)
|
||||
#if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
|
||||
#error This kernel is not configured for one of the supported CPUs
|
||||
#endif
|
||||
#else /* lint */
|
||||
#endif /* lint */
|
||||
#else /* __amd64__ */
|
||||
#ifndef HAMMER
|
||||
#error "You need to specify a cpu type"
|
||||
#endif
|
||||
#endif
|
||||
/*
|
||||
* Now that we have told the user what they have,
|
||||
* let them know if that machine type isn't configured.
|
||||
*/
|
||||
switch (cpu_class) {
|
||||
#ifdef __i386__
|
||||
case CPUCLASS_286: /* a 286 should not make it this far, anyway */
|
||||
case CPUCLASS_386:
|
||||
#if !defined(I486_CPU)
|
||||
@ -876,6 +1014,12 @@ panicifcpuunsupported(void)
|
||||
#endif
|
||||
#if !defined(I686_CPU)
|
||||
case CPUCLASS_686:
|
||||
#endif
|
||||
#else /* __amd64__ */
|
||||
case CPUCLASS_X86:
|
||||
#ifndef HAMMER
|
||||
case CPUCLASS_K8:
|
||||
#endif
|
||||
#endif
|
||||
panic("CPU class not configured");
|
||||
default:
|
||||
@ -883,7 +1027,7 @@ panicifcpuunsupported(void)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#ifdef __i386__
|
||||
static volatile u_int trap_by_rdmsr;
|
||||
|
||||
/*
|
||||
@ -1012,6 +1156,7 @@ identifycyrix(void)
|
||||
|
||||
intr_restore(saveintr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Update TSC freq with the value indicated by the caller. */
|
||||
static void
|
||||
@ -1040,14 +1185,35 @@ hook_tsc_freq(void *arg __unused)
|
||||
SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
|
||||
|
||||
/*
|
||||
* Final stage of CPU identification. -- Should I check TI?
|
||||
* Final stage of CPU identification.
|
||||
*/
|
||||
#ifdef __i386__
|
||||
void
|
||||
finishidentcpu(void)
|
||||
#else
|
||||
void
|
||||
identify_cpu(void)
|
||||
#endif
|
||||
{
|
||||
int isblue = 0;
|
||||
u_char ccr3;
|
||||
u_int regs[4];
|
||||
u_int regs[4], cpu_stdext_disable;
|
||||
#ifdef __i386__
|
||||
u_char ccr3;
|
||||
#endif
|
||||
|
||||
#ifdef __amd64__
|
||||
do_cpuid(0, regs);
|
||||
cpu_high = regs[0];
|
||||
((u_int *)&cpu_vendor)[0] = regs[1];
|
||||
((u_int *)&cpu_vendor)[1] = regs[3];
|
||||
((u_int *)&cpu_vendor)[2] = regs[2];
|
||||
cpu_vendor[12] = '\0';
|
||||
|
||||
do_cpuid(1, regs);
|
||||
cpu_id = regs[0];
|
||||
cpu_procinfo = regs[1];
|
||||
cpu_feature = regs[3];
|
||||
cpu_feature2 = regs[2];
|
||||
#endif
|
||||
|
||||
cpu_vendor_id = find_cpu_vendor_id();
|
||||
|
||||
@ -1076,6 +1242,26 @@ finishidentcpu(void)
|
||||
cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE;
|
||||
}
|
||||
|
||||
if (cpu_high >= 7) {
|
||||
cpuid_count(7, 0, regs);
|
||||
cpu_stdext_feature = regs[1];
|
||||
|
||||
/*
|
||||
* Some hypervisors fail to filter out unsupported
|
||||
* extended features. For now, disable the
|
||||
* extensions, activation of which requires setting a
|
||||
* bit in CR4, and which VM monitors do not support.
|
||||
*/
|
||||
if (cpu_feature2 & CPUID2_HV) {
|
||||
cpu_stdext_disable = CPUID_STDEXT_FSGSBASE |
|
||||
CPUID_STDEXT_SMEP;
|
||||
} else
|
||||
cpu_stdext_disable = 0;
|
||||
TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
|
||||
cpu_stdext_feature &= ~cpu_stdext_disable;
|
||||
}
|
||||
|
||||
#ifdef __i386__
|
||||
if (cpu_high > 0 &&
|
||||
(cpu_vendor_id == CPU_VENDOR_INTEL ||
|
||||
cpu_vendor_id == CPU_VENDOR_AMD ||
|
||||
@ -1086,37 +1272,37 @@ finishidentcpu(void)
|
||||
if (regs[0] >= 0x80000000)
|
||||
cpu_exthigh = regs[0];
|
||||
}
|
||||
|
||||
/* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
|
||||
#else
|
||||
if (cpu_vendor_id == CPU_VENDOR_INTEL ||
|
||||
cpu_vendor_id == CPU_VENDOR_AMD) {
|
||||
if (cpu_exthigh >= 0x80000001) {
|
||||
do_cpuid(0x80000001, regs);
|
||||
amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
|
||||
amd_feature2 = regs[2];
|
||||
}
|
||||
if (cpu_exthigh >= 0x80000007) {
|
||||
do_cpuid(0x80000007, regs);
|
||||
amd_pminfo = regs[3];
|
||||
}
|
||||
if (cpu_exthigh >= 0x80000008) {
|
||||
do_cpuid(0x80000008, regs);
|
||||
cpu_procinfo2 = regs[2];
|
||||
}
|
||||
} else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) {
|
||||
if (cpu_exthigh >= 0x80000001) {
|
||||
do_cpuid(0x80000001, regs);
|
||||
amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
|
||||
}
|
||||
} else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
|
||||
cpu_vendor_id == CPU_VENDOR_AMD ||
|
||||
cpu_vendor_id == CPU_VENDOR_CENTAUR) {
|
||||
do_cpuid(0x80000000, regs);
|
||||
cpu_exthigh = regs[0];
|
||||
}
|
||||
#endif
|
||||
if (cpu_exthigh >= 0x80000001) {
|
||||
do_cpuid(0x80000001, regs);
|
||||
amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
|
||||
amd_feature2 = regs[2];
|
||||
}
|
||||
if (cpu_exthigh >= 0x80000007) {
|
||||
do_cpuid(0x80000007, regs);
|
||||
amd_pminfo = regs[3];
|
||||
}
|
||||
if (cpu_exthigh >= 0x80000008) {
|
||||
do_cpuid(0x80000008, regs);
|
||||
cpu_procinfo2 = regs[2];
|
||||
}
|
||||
|
||||
#ifdef __i386__
|
||||
if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
|
||||
if (cpu == CPU_486) {
|
||||
/*
|
||||
* These conditions are equivalent to:
|
||||
* - CPU does not support cpuid instruction.
|
||||
* - Cyrix/IBM CPU is detected.
|
||||
*/
|
||||
isblue = identblue();
|
||||
if (isblue == IDENTBLUE_IBMCPU) {
|
||||
if (identblue() == IDENTBLUE_IBMCPU) {
|
||||
strcpy(cpu_vendor, "IBM");
|
||||
cpu_vendor_id = CPU_VENDOR_IBM;
|
||||
cpu = CPU_BLUE;
|
||||
@ -1189,14 +1375,17 @@ finishidentcpu(void)
|
||||
* cpu_vendor null string and puts CPU_486 into the
|
||||
* cpu.
|
||||
*/
|
||||
isblue = identblue();
|
||||
if (isblue == IDENTBLUE_IBMCPU) {
|
||||
if (identblue() == IDENTBLUE_IBMCPU) {
|
||||
strcpy(cpu_vendor, "IBM");
|
||||
cpu_vendor_id = CPU_VENDOR_IBM;
|
||||
cpu = CPU_BLUE;
|
||||
return;
|
||||
}
|
||||
}
|
||||
#else
|
||||
/* XXX */
|
||||
cpu = CPU_CLAWHAMMER;
|
||||
#endif
|
||||
}
|
||||
|
||||
static u_int
|
||||
@ -1219,35 +1408,88 @@ print_AMD_assoc(int i)
|
||||
printf(", %d-way associative\n", i);
|
||||
}
|
||||
|
||||
static void
|
||||
print_AMD_l2_assoc(int i)
|
||||
{
|
||||
switch (i & 0x0f) {
|
||||
case 0: printf(", disabled/not present\n"); break;
|
||||
case 1: printf(", direct mapped\n"); break;
|
||||
case 2: printf(", 2-way associative\n"); break;
|
||||
case 4: printf(", 4-way associative\n"); break;
|
||||
case 6: printf(", 8-way associative\n"); break;
|
||||
case 8: printf(", 16-way associative\n"); break;
|
||||
case 15: printf(", fully associative\n"); break;
|
||||
default: printf(", reserved configuration\n"); break;
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
print_AMD_info(void)
|
||||
{
|
||||
quad_t amd_whcr;
|
||||
#ifdef __i386__
|
||||
uint64_t amd_whcr;
|
||||
#endif
|
||||
u_int regs[4];
|
||||
|
||||
if (cpu_exthigh >= 0x80000005) {
|
||||
u_int regs[4];
|
||||
|
||||
do_cpuid(0x80000005, regs);
|
||||
printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
|
||||
printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
|
||||
print_AMD_assoc(regs[0] >> 24);
|
||||
|
||||
printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
|
||||
print_AMD_assoc((regs[0] >> 8) & 0xff);
|
||||
|
||||
printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
|
||||
print_AMD_assoc(regs[1] >> 24);
|
||||
printf("Instruction TLB: %d entries", regs[1] & 0xff);
|
||||
|
||||
printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
|
||||
print_AMD_assoc((regs[1] >> 8) & 0xff);
|
||||
|
||||
printf("L1 data cache: %d kbytes", regs[2] >> 24);
|
||||
printf(", %d bytes/line", regs[2] & 0xff);
|
||||
printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
|
||||
print_AMD_assoc((regs[2] >> 16) & 0xff);
|
||||
|
||||
printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
|
||||
printf(", %d bytes/line", regs[3] & 0xff);
|
||||
printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
|
||||
print_AMD_assoc((regs[3] >> 16) & 0xff);
|
||||
if (cpu_exthigh >= 0x80000006) { /* K6-III only */
|
||||
do_cpuid(0x80000006, regs);
|
||||
printf("L2 internal cache: %d kbytes", regs[2] >> 16);
|
||||
printf(", %d bytes/line", regs[2] & 0xff);
|
||||
printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
|
||||
print_AMD_assoc((regs[2] >> 12) & 0x0f);
|
||||
}
|
||||
}
|
||||
|
||||
if (cpu_exthigh >= 0x80000006) {
|
||||
do_cpuid(0x80000006, regs);
|
||||
if ((regs[0] >> 16) != 0) {
|
||||
printf("L2 2MB data TLB: %d entries",
|
||||
(regs[0] >> 16) & 0xfff);
|
||||
print_AMD_l2_assoc(regs[0] >> 28);
|
||||
printf("L2 2MB instruction TLB: %d entries",
|
||||
regs[0] & 0xfff);
|
||||
print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
|
||||
} else {
|
||||
printf("L2 2MB unified TLB: %d entries",
|
||||
regs[0] & 0xfff);
|
||||
print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
|
||||
}
|
||||
if ((regs[1] >> 16) != 0) {
|
||||
printf("L2 4KB data TLB: %d entries",
|
||||
(regs[1] >> 16) & 0xfff);
|
||||
print_AMD_l2_assoc(regs[1] >> 28);
|
||||
|
||||
printf("L2 4KB instruction TLB: %d entries",
|
||||
(regs[1] >> 16) & 0xfff);
|
||||
print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
|
||||
} else {
|
||||
printf("L2 4KB unified TLB: %d entries",
|
||||
(regs[1] >> 16) & 0xfff);
|
||||
print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
|
||||
}
|
||||
printf("L2 unified cache: %d kbytes", regs[2] >> 16);
|
||||
printf(", %d bytes/line", regs[2] & 0xff);
|
||||
printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
|
||||
print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
|
||||
}
|
||||
|
||||
#ifdef __i386__
|
||||
if (((cpu_id & 0xf00) == 0x500)
|
||||
&& (((cpu_id & 0x0f0) > 0x80)
|
||||
|| (((cpu_id & 0x0f0) == 0x80)
|
||||
@ -1277,7 +1519,7 @@ print_AMD_info(void)
|
||||
(amd_whcr & 0x0100) ? "Enable" : "Disable");
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
/*
|
||||
* Opteron Rev E shows a bug as in very rare occasions a read memory
|
||||
* barrier is not performed as expected if it is followed by a
|
||||
@ -1499,6 +1741,7 @@ print_INTEL_TLB(u_int data)
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __i386__
|
||||
static void
|
||||
print_transmeta_info(void)
|
||||
{
|
||||
@ -1533,6 +1776,7 @@ print_transmeta_info(void)
|
||||
printf(" %s\n", info);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static void
|
||||
print_via_padlock_info(void)
|
||||
@ -1549,3 +1793,197 @@ print_via_padlock_info(void)
|
||||
"\015RSA" /* PMM */
|
||||
);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
vmx_settable(uint64_t basic, int msr, int true_msr)
|
||||
{
|
||||
uint64_t val;
|
||||
|
||||
if (basic & (1ULL << 55))
|
||||
val = rdmsr(true_msr);
|
||||
else
|
||||
val = rdmsr(msr);
|
||||
|
||||
/* Just report the controls that can be set to 1. */
|
||||
return (val >> 32);
|
||||
}
|
||||
|
||||
static void
|
||||
print_vmx_info(void)
|
||||
{
|
||||
uint64_t basic, msr;
|
||||
uint32_t entry, exit, mask, pin, proc, proc2;
|
||||
int comma;
|
||||
|
||||
printf("\n VT-x: ");
|
||||
msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
|
||||
if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
|
||||
printf("(disabled in BIOS) ");
|
||||
basic = rdmsr(MSR_VMX_BASIC);
|
||||
pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
|
||||
MSR_VMX_TRUE_PINBASED_CTLS);
|
||||
proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
|
||||
MSR_VMX_TRUE_PROCBASED_CTLS);
|
||||
if (proc & PROCBASED_SECONDARY_CONTROLS)
|
||||
proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
|
||||
MSR_VMX_PROCBASED_CTLS2);
|
||||
else
|
||||
proc2 = 0;
|
||||
exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
|
||||
entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
|
||||
|
||||
if (!bootverbose) {
|
||||
comma = 0;
|
||||
if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
|
||||
entry & VM_ENTRY_LOAD_PAT) {
|
||||
printf("%sPAT", comma ? "," : "");
|
||||
comma = 1;
|
||||
}
|
||||
if (proc & PROCBASED_HLT_EXITING) {
|
||||
printf("%sHLT", comma ? "," : "");
|
||||
comma = 1;
|
||||
}
|
||||
if (proc & PROCBASED_MTF) {
|
||||
printf("%sMTF", comma ? "," : "");
|
||||
comma = 1;
|
||||
}
|
||||
if (proc & PROCBASED_PAUSE_EXITING) {
|
||||
printf("%sPAUSE", comma ? "," : "");
|
||||
comma = 1;
|
||||
}
|
||||
if (proc2 & PROCBASED2_ENABLE_EPT) {
|
||||
printf("%sEPT", comma ? "," : "");
|
||||
comma = 1;
|
||||
}
|
||||
if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
|
||||
printf("%sUG", comma ? "," : "");
|
||||
comma = 1;
|
||||
}
|
||||
if (proc2 & PROCBASED2_ENABLE_VPID) {
|
||||
printf("%sVPID", comma ? "," : "");
|
||||
comma = 1;
|
||||
}
|
||||
if (proc & PROCBASED_USE_TPR_SHADOW &&
|
||||
proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
|
||||
proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
|
||||
proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
|
||||
proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
|
||||
printf("%sVID", comma ? "," : "");
|
||||
comma = 1;
|
||||
if (pin & PINBASED_POSTED_INTERRUPT)
|
||||
printf(",PostIntr");
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
mask = basic >> 32;
|
||||
printf("Basic Features=0x%b", mask,
|
||||
"\020"
|
||||
"\02132PA" /* 32-bit physical addresses */
|
||||
"\022SMM" /* SMM dual-monitor */
|
||||
"\027INS/OUTS" /* VM-exit info for INS and OUTS */
|
||||
"\030TRUE" /* TRUE_CTLS MSRs */
|
||||
);
|
||||
printf("\n Pin-Based Controls=0x%b", pin,
|
||||
"\020"
|
||||
"\001ExtINT" /* External-interrupt exiting */
|
||||
"\004NMI" /* NMI exiting */
|
||||
"\006VNMI" /* Virtual NMIs */
|
||||
"\007PreTmr" /* Activate VMX-preemption timer */
|
||||
"\010PostIntr" /* Process posted interrupts */
|
||||
);
|
||||
printf("\n Primary Processor Controls=0x%b", proc,
|
||||
"\020"
|
||||
"\003INTWIN" /* Interrupt-window exiting */
|
||||
"\004TSCOff" /* Use TSC offsetting */
|
||||
"\010HLT" /* HLT exiting */
|
||||
"\012INVLPG" /* INVLPG exiting */
|
||||
"\013MWAIT" /* MWAIT exiting */
|
||||
"\014RDPMC" /* RDPMC exiting */
|
||||
"\015RDTSC" /* RDTSC exiting */
|
||||
"\020CR3-LD" /* CR3-load exiting */
|
||||
"\021CR3-ST" /* CR3-store exiting */
|
||||
"\024CR8-LD" /* CR8-load exiting */
|
||||
"\025CR8-ST" /* CR8-store exiting */
|
||||
"\026TPR" /* Use TPR shadow */
|
||||
"\027NMIWIN" /* NMI-window exiting */
|
||||
"\030MOV-DR" /* MOV-DR exiting */
|
||||
"\031IO" /* Unconditional I/O exiting */
|
||||
"\032IOmap" /* Use I/O bitmaps */
|
||||
"\034MTF" /* Monitor trap flag */
|
||||
"\035MSRmap" /* Use MSR bitmaps */
|
||||
"\036MONITOR" /* MONITOR exiting */
|
||||
"\037PAUSE" /* PAUSE exiting */
|
||||
);
|
||||
if (proc & PROCBASED_SECONDARY_CONTROLS)
|
||||
printf("\n Secondary Processor Controls=0x%b", proc2,
|
||||
"\020"
|
||||
"\001APIC" /* Virtualize APIC accesses */
|
||||
"\002EPT" /* Enable EPT */
|
||||
"\003DT" /* Descriptor-table exiting */
|
||||
"\004RDTSCP" /* Enable RDTSCP */
|
||||
"\005x2APIC" /* Virtualize x2APIC mode */
|
||||
"\006VPID" /* Enable VPID */
|
||||
"\007WBINVD" /* WBINVD exiting */
|
||||
"\010UG" /* Unrestricted guest */
|
||||
"\011APIC-reg" /* APIC-register virtualization */
|
||||
"\012VID" /* Virtual-interrupt delivery */
|
||||
"\013PAUSE-loop" /* PAUSE-loop exiting */
|
||||
"\014RDRAND" /* RDRAND exiting */
|
||||
"\015INVPCID" /* Enable INVPCID */
|
||||
"\016VMFUNC" /* Enable VM functions */
|
||||
"\017VMCS" /* VMCS shadowing */
|
||||
"\020EPT#VE" /* EPT-violation #VE */
|
||||
"\021XSAVES" /* Enable XSAVES/XRSTORS */
|
||||
);
|
||||
printf("\n Exit Controls=0x%b", mask,
|
||||
"\020"
|
||||
"\003DR" /* Save debug controls */
|
||||
/* Ignore Host address-space size */
|
||||
"\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */
|
||||
"\020AckInt" /* Acknowledge interrupt on exit */
|
||||
"\023PAT-SV" /* Save MSR_PAT */
|
||||
"\024PAT-LD" /* Load MSR_PAT */
|
||||
"\025EFER-SV" /* Save MSR_EFER */
|
||||
"\026EFER-LD" /* Load MSR_EFER */
|
||||
"\027PTMR-SV" /* Save VMX-preemption timer value */
|
||||
);
|
||||
printf("\n Entry Controls=0x%b", mask,
|
||||
"\020"
|
||||
"\003DR" /* Save debug controls */
|
||||
/* Ignore IA-32e mode guest */
|
||||
/* Ignore Entry to SMM */
|
||||
/* Ignore Deactivate dual-monitor treatment */
|
||||
"\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */
|
||||
"\017PAT" /* Load MSR_PAT */
|
||||
"\020EFER" /* Load MSR_EFER */
|
||||
);
|
||||
if (proc & PROCBASED_SECONDARY_CONTROLS &&
|
||||
(proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
|
||||
msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
|
||||
mask = msr;
|
||||
printf("\n EPT Features=0x%b", mask,
|
||||
"\020"
|
||||
"\001XO" /* Execute-only translations */
|
||||
"\007PW4" /* Page-walk length of 4 */
|
||||
"\011UC" /* EPT paging-structure mem can be UC */
|
||||
"\017WB" /* EPT paging-structure mem can be WB */
|
||||
"\0212M" /* EPT PDE can map a 2-Mbyte page */
|
||||
"\0221G" /* EPT PDPTE can map a 1-Gbyte page */
|
||||
"\025INVEPT" /* INVEPT is supported */
|
||||
"\026AD" /* Accessed and dirty flags for EPT */
|
||||
"\032single" /* INVEPT single-context type */
|
||||
"\033all" /* INVEPT all-context type */
|
||||
);
|
||||
mask = msr >> 32;
|
||||
printf("\n VPID Features=0x%b", mask,
|
||||
"\020"
|
||||
"\001INVVPID" /* INVVPID is supported */
|
||||
"\011individual" /* INVVPID individual-address type */
|
||||
"\012single" /* INVVPID single-context type */
|
||||
"\013all" /* INVVPID all-context type */
|
||||
/* INVVPID single-context-retaining-globals type */
|
||||
"\014single-globals"
|
||||
);
|
||||
}
|
||||
}
|
Loading…
Reference in New Issue
Block a user