- Masking IFM_GMASK when also masking IFM_FDX is redundant and just
complicates the code. - Don't let atphy_setmedia() announce PAUSE support for half-duplex when MIIF_FORCEPAUSE is set. - Simplify e1000phy_service() and ip1000phy_service() to only set the manual configuration bits once after we have figured them all out. For ip1000phy_service() this also means we no longer unnecessarily update the hardware along the road. MFC after: 1 week
This commit is contained in:
parent
2dc29adb9f
commit
34259ba39b
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=217412
@ -187,9 +187,9 @@ atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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}
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anar = atphy_anar(ife);
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if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
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if ((ife->ifm_media & IFM_FDX) != 0) {
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bmcr |= BMCR_FDX;
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if (((ife->ifm_media & IFM_GMASK) & IFM_FLOW) != 0 ||
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if ((ife->ifm_media & IFM_FLOW) != 0 ||
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(sc->mii_flags & MIIF_FORCEPAUSE) != 0)
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anar |= ANAR_PAUSE_TOWARDS;
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}
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@ -371,7 +371,7 @@ atphy_anar(struct ifmedia_entry *ife)
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return (0);
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}
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if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
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if ((ife->ifm_media & IFM_FDX) != 0) {
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if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX)
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anar |= ANAR_TX_FD;
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else
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@ -387,13 +387,13 @@ atphy_setmedia(struct mii_softc *sc, int media)
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uint16_t anar;
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anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
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if (((IFM_SUBTYPE(media) == IFM_AUTO ||
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((media & IFM_GMASK) & IFM_FDX) != 0) &&
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((media & IFM_GMASK) & IFM_FLOW) != 0) ||
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(sc->mii_flags & MIIF_FORCEPAUSE) != 0)
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if ((IFM_SUBTYPE(media) == IFM_AUTO || (media & IFM_FDX) != 0) &&
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((media & IFM_FLOW) != 0 ||
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(sc->mii_flags & MIIF_FORCEPAUSE) != 0))
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anar |= ANAR_PAUSE_TOWARDS;
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PHY_WRITE(sc, MII_ANAR, anar);
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if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
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if ((sc->mii_extcapabilities &
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(EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
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PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX |
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GTCR_ADV_1000THDX);
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PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
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@ -358,7 +358,7 @@ e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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return (EINVAL);
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}
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if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
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if ((ife->ifm_media & IFM_FDX) != 0) {
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speed |= E1000_CR_FULL_DUPLEX;
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gig = E1000_1GCR_1000T_FD;
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} else
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@ -372,10 +372,10 @@ e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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gig |= E1000_1GCR_MS_ENABLE;
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if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
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gig |= E1000_1GCR_MS_VALUE;
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PHY_WRITE(sc, E1000_1GCR, gig);
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} else if ((sc->mii_extcapabilities &
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(EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
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PHY_WRITE(sc, E1000_1GCR, 0);
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gig = 0;
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PHY_WRITE(sc, E1000_1GCR, gig);
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PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD);
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PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET);
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done:
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@ -186,22 +186,21 @@ ip1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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return (EINVAL);
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}
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if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
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if ((ife->ifm_media & IFM_FDX) != 0) {
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speed |= IP1000PHY_BMCR_FDX;
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gig = IP1000PHY_1000CR_1000T_FDX;
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} else
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gig = IP1000PHY_1000CR_1000T;
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PHY_WRITE(sc, IP1000PHY_MII_1000CR, 0);
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PHY_WRITE(sc, IP1000PHY_MII_BMCR, speed);
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
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break;
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gig |= IP1000PHY_1000CR_MASTER | IP1000PHY_1000CR_MANUAL;
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if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
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gig |= IP1000PHY_1000CR_MMASTER;
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if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
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gig |=
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IP1000PHY_1000CR_MASTER | IP1000PHY_1000CR_MANUAL;
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if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
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gig |= IP1000PHY_1000CR_MMASTER;
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} else
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gig = 0;
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PHY_WRITE(sc, IP1000PHY_MII_1000CR, gig);
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PHY_WRITE(sc, IP1000PHY_MII_BMCR, speed);
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done:
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break;
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