cgem: support SGMII PHY connection mode
As the PolarFire SoC needs SGMII to connect the PHY, check the 'phy-mode' property of device tree node for ethernet and act on it appropriately. Add the compatible strings for the PolarFire SoC device tree. 'microchip,mpfs-mss-gem" is not officially documented but has been observed in the available firmware for this platform, so it is included for now. Also, fix a typo in if_cgem_hw.h. Reviewed by: mhorne MFC after: 1 week Sponsored by: Conclusive Engineering Differential Revision: https://reviews.freebsd.org/D34764
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@ -76,6 +76,7 @@ __FBSDID("$FreeBSD$");
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mii/mii_fdt.h>
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#include <dev/extres/clk/clk.h>
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@ -109,9 +110,11 @@ __FBSDID("$FreeBSD$");
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static struct ofw_compat_data compat_data[] = {
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{ "cdns,zynq-gem", HWQUIRK_RXHANGWAR | HWQUIRK_TXCLK },
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{ "cdns,zynqmp-gem", HWQUIRK_NEEDNULLQS | HWQUIRK_TXCLK },
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{ "microchip,mpfs-mss-gem", HWQUIRK_NEEDNULLQS | HWQUIRK_TXCLK },
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{ "sifive,fu540-c000-gem", HWQUIRK_PCLK },
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{ "sifive,fu740-c000-gem", HWQUIRK_PCLK },
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{ "cdns,gem", HWQUIRK_NONE },
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{ "cdns,macb", HWQUIRK_NONE },
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{ "cadence,gem", HWQUIRK_NONE },
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{ NULL, 0 }
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};
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@ -131,6 +134,7 @@ struct cgem_softc {
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uint32_t net_cfg_shadow;
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clk_t ref_clk;
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int neednullqs;
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int phy_contype;
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bus_dma_tag_t desc_dma_tag;
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bus_dma_tag_t mbuf_dma_tag;
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@ -1084,6 +1088,12 @@ cgem_config(struct cgem_softc *sc)
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CGEM_NET_CFG_GIGE_EN | CGEM_NET_CFG_1536RXEN |
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CGEM_NET_CFG_FULL_DUPLEX | CGEM_NET_CFG_SPEED100);
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/* Check connection type, enable SGMII bits if necessary. */
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if (sc->phy_contype == MII_CONTYPE_SGMII) {
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sc->net_cfg_shadow |= CGEM_NET_CFG_SGMII_EN;
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sc->net_cfg_shadow |= CGEM_NET_CFG_PCS_SEL;
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}
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/* Enable receive checksum offloading? */
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if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
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sc->net_cfg_shadow |= CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN;
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@ -1728,6 +1738,7 @@ cgem_attach(device_t dev)
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int rid, err;
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u_char eaddr[ETHER_ADDR_LEN];
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int hwquirks;
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phandle_t node;
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sc->dev = dev;
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CGEM_LOCK_INIT(sc);
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@ -1753,6 +1764,9 @@ cgem_attach(device_t dev)
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device_printf(dev, "could not enable clock.\n");
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}
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node = ofw_bus_get_node(dev);
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sc->phy_contype = mii_fdt_get_contype(node);
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/* Get memory resource. */
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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@ -63,7 +63,7 @@
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#define CGEM_NET_CTRL_RX_EN (1 << 2)
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#define CGEM_NET_CTRL_LOOP_LOCAL (1 << 1)
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#define CGEM_NET_CFG 0x004 /* Netowrk Configuration */
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#define CGEM_NET_CFG 0x004 /* Network Configuration */
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#define CGEM_NET_CFG_UNIDIR_EN (1U << 31)
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#define CGEM_NET_CFG_IGNORE_IPG_RX_ER (1 << 30)
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#define CGEM_NET_CFG_RX_BAD_PREAMBLE (1 << 29)
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