Allwinner usb phy: Rework resource allocation
The usbphy node for allwinner have two kind of resources, one for the phy_ctrl and one per phy. Instead of blindy allocating resources, alloc the phy_ctrl and pmu ones separately. Also add a configuration struct for all different phy that hold the difference between them (number of phys, unknow needed register write etc ...). While here remove A83T code as upstream and FreeBSD dts don't have nodes for USB. This (plus 323640) re-enable OHCI on Pine64 on the bottom USB port. The top USB port is routed to the OHCI0/EHCI0 which is by default in OTG mode. While the phy code can handle the re-route to standard OHCI/EHCI we still need a driver for musb to probe and configure it in host mode. EHCI is still buggy on Pine64 (hang the board) so do not enable it for now. Tested On: Bananapi (A20), BananapiM2 (A31S), OrangePi One (H3) Pine64 (A64)
This commit is contained in:
Emmanuel Vadot
parent
489cba7d58
commit
36dcd6a499
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=323641
@ -53,52 +53,89 @@ __FBSDID("$FreeBSD$");
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#include "phy_if.h"
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#define USBPHY_NPHYS 4
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#define USBPHY_NRES USBPHY_NPHYS
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enum awusbphy_type {
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AWUSBPHY_TYPE_A10 = 1,
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AWUSBPHY_TYPE_A13,
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AWUSBPHY_TYPE_A20,
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AWUSBPHY_TYPE_A31,
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AWUSBPHY_TYPE_A83T,
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AWUSBPHY_TYPE_H3,
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AWUSBPHY_TYPE_A64
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};
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struct aw_usbphy_conf {
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int num_phys;
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enum awusbphy_type phy_type;
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bool pmu_unk1;
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bool phy0_route;
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};
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static const struct aw_usbphy_conf a10_usbphy_conf = {
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.num_phys = 3,
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.phy_type = AWUSBPHY_TYPE_A10,
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.pmu_unk1 = false,
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.phy0_route = false,
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};
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static const struct aw_usbphy_conf a13_usbphy_conf = {
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.num_phys = 2,
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.phy_type = AWUSBPHY_TYPE_A13,
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.pmu_unk1 = false,
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.phy0_route = false,
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};
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static const struct aw_usbphy_conf a20_usbphy_conf = {
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.num_phys = 3,
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.phy_type = AWUSBPHY_TYPE_A20,
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.pmu_unk1 = false,
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.phy0_route = false,
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};
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static const struct aw_usbphy_conf a31_usbphy_conf = {
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.num_phys = 3,
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.phy_type = AWUSBPHY_TYPE_A31,
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.pmu_unk1 = false,
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.phy0_route = false,
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};
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static const struct aw_usbphy_conf h3_usbphy_conf = {
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.num_phys = 4,
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.phy_type = AWUSBPHY_TYPE_H3,
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.pmu_unk1 = true,
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.phy0_route = false,
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};
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static const struct aw_usbphy_conf a64_usbphy_conf = {
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.num_phys = 2,
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.phy_type = AWUSBPHY_TYPE_A64,
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.pmu_unk1 = true,
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.phy0_route = true,
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};
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static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun4i-a10-usb-phy", AWUSBPHY_TYPE_A10 },
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{ "allwinner,sun5i-a13-usb-phy", AWUSBPHY_TYPE_A13 },
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{ "allwinner,sun6i-a31-usb-phy", AWUSBPHY_TYPE_A31 },
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{ "allwinner,sun7i-a20-usb-phy", AWUSBPHY_TYPE_A20 },
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{ "allwinner,sun8i-a83t-usb-phy", AWUSBPHY_TYPE_A83T },
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{ "allwinner,sun8i-h3-usb-phy", AWUSBPHY_TYPE_H3 },
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{ "allwinner,sun50i-a64-usb-phy", AWUSBPHY_TYPE_A64 },
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{ "allwinner,sun4i-a10-usb-phy", (uintptr_t)&a10_usbphy_conf },
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{ "allwinner,sun5i-a13-usb-phy", (uintptr_t)&a13_usbphy_conf },
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{ "allwinner,sun6i-a31-usb-phy", (uintptr_t)&a31_usbphy_conf },
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{ "allwinner,sun7i-a20-usb-phy", (uintptr_t)&a20_usbphy_conf },
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{ "allwinner,sun8i-h3-usb-phy", (uintptr_t)&h3_usbphy_conf },
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{ "allwinner,sun50i-a64-usb-phy", (uintptr_t)&a64_usbphy_conf },
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{ NULL, 0 }
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};
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struct awusbphy_softc {
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struct resource * res[USBPHY_NRES];
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regulator_t reg[USBPHY_NPHYS];
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struct resource * phy_ctrl;
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struct resource ** pmu;
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regulator_t * reg;
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gpio_pin_t id_det_pin;
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int id_det_valid;
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gpio_pin_t vbus_det_pin;
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int vbus_det_valid;
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enum awusbphy_type phy_type;
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struct aw_usbphy_conf *phy_conf;
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};
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static struct resource_spec awusbphy_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_MEMORY, 1, RF_ACTIVE },
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{ SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL },
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{ SYS_RES_MEMORY, 3, RF_ACTIVE | RF_OPTIONAL },
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{ -1, 0 }
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};
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#define RD4(sc, i, o) bus_read_4((sc)->res[(i)], (o))
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#define WR4(sc, i, o, v) bus_write_4((sc)->res[(i)], (o), (v))
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#define CLR4(sc, i, o, m) WR4(sc, i, o, RD4(sc, i, o) & ~(m))
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#define SET4(sc, i, o, m) WR4(sc, i, o, RD4(sc, i, o) | (m))
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#define RD4(res, o) bus_read_4(res, (o))
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#define WR4(res, o, v) bus_write_4(res, (o), (v))
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#define CLR4(res, o, m) WR4(res, o, RD4(res, o) & ~(m))
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#define SET4(res, o, m) WR4(res, o, RD4(res, o) | (m))
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#define OTG_PHY_CFG 0x20
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#define OTG_PHY_ROUTE_OTG (1 << 0)
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@ -117,24 +154,21 @@ awusbphy_configure(device_t dev, int phyno)
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sc = device_get_softc(dev);
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if (sc->res[phyno] == NULL)
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if (sc->pmu[phyno] == NULL)
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return;
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if (sc->phy_type == AWUSBPHY_TYPE_A64) {
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CLR4(sc, phyno, PMU_UNK_H3, PMU_UNK_H3_CLR);
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if (sc->phy_conf->pmu_unk1 == true)
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CLR4(sc->phy_ctrl, PMU_UNK_H3, PMU_UNK_H3_CLR);
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/* EHCI0 and OTG share a PHY */
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if (sc->phy_conf->phy0_route == true) {
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if (phyno == 0)
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SET4(sc, 0, OTG_PHY_CFG, OTG_PHY_ROUTE_OTG);
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else if (phyno == 1)
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CLR4(sc, 0, OTG_PHY_CFG, OTG_PHY_ROUTE_OTG);
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SET4(sc->phy_ctrl, OTG_PHY_CFG, OTG_PHY_ROUTE_OTG);
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else
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CLR4(sc->phy_ctrl, OTG_PHY_CFG, OTG_PHY_ROUTE_OTG);
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}
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if (phyno > 0) {
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/* Enable passby */
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SET4(sc, phyno, PMU_IRQ_ENABLE, PMU_ULPI_BYPASS |
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PMU_AHB_INCR8 | PMU_AHB_INCR4 | PMU_AHB_INCRX_ALIGN);
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}
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SET4(sc->pmu[phyno], PMU_IRQ_ENABLE, PMU_ULPI_BYPASS |
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PMU_AHB_INCR8 | PMU_AHB_INCR4 | PMU_AHB_INCRX_ALIGN);
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}
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static int
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@ -143,7 +177,7 @@ awusbphy_init(device_t dev)
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struct awusbphy_softc *sc;
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phandle_t node;
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char pname[20];
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int error, off;
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int error, off, rid;
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regulator_t reg;
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hwreset_t rst;
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clk_t clk;
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@ -151,7 +185,19 @@ awusbphy_init(device_t dev)
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sc = device_get_softc(dev);
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node = ofw_bus_get_node(dev);
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sc->phy_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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sc->phy_conf = (struct aw_usbphy_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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/* Get phy_ctrl region */
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if (ofw_bus_find_string_index(node, "reg-names", "phy_ctrl", &rid) != 0) {
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device_printf(dev, "Cannot locate phy control resource\n");
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return (ENXIO);
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}
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sc->phy_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->phy_ctrl == NULL) {
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device_printf(dev, "Cannot allocate resource\n");
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return (ENXIO);
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}
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/* Enable clocks */
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for (off = 0; clk_get_by_ofw_index(dev, 0, off, &clk) == 0; off++) {
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@ -173,13 +219,6 @@ awusbphy_init(device_t dev)
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}
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}
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/* Get regulators */
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for (off = 0; off < USBPHY_NPHYS; off++) {
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snprintf(pname, sizeof(pname), "usb%d_vbus-supply", off);
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if (regulator_get_by_ofw_property(dev, 0, pname, ®) == 0)
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sc->reg[off] = reg;
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}
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/* Get GPIOs */
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error = gpio_pin_get_by_ofw_property(dev, node, "usb0_id_det-gpios",
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&sc->id_det_pin);
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@ -190,9 +229,28 @@ awusbphy_init(device_t dev)
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if (error == 0)
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sc->vbus_det_valid = 1;
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/* Allocate resources */
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if (bus_alloc_resources(dev, awusbphy_spec, sc->res) != 0)
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device_printf(dev, "couldn't allocate resources\n");
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sc->reg = malloc(sizeof(*(sc->reg)) * sc->phy_conf->num_phys, M_DEVBUF,
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M_WAITOK | M_ZERO);
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sc->pmu = malloc(sizeof(*(sc->pmu)) * sc->phy_conf->num_phys, M_DEVBUF,
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M_WAITOK | M_ZERO);
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/* Get regulators */
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for (off = 0; off < sc->phy_conf->num_phys; off++) {
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snprintf(pname, sizeof(pname), "usb%d_vbus-supply", off);
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if (regulator_get_by_ofw_property(dev, 0, pname, ®) == 0)
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sc->reg[off] = reg;
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snprintf(pname, sizeof(pname), "pmu%d", off);
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if (ofw_bus_find_string_index(node, "reg-names",
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pname, &rid) != 0)
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continue;
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sc->pmu[off] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->pmu[off] == NULL) {
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device_printf(dev, "Cannot allocate resource\n");
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return (ENXIO);
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}
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}
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return (0);
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}
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@ -225,11 +283,11 @@ awusbphy_phy_enable(device_t dev, intptr_t phy, bool enable)
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regulator_t reg;
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int error, vbus_det;
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if (phy < 0 || phy >= USBPHY_NPHYS)
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return (ERANGE);
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sc = device_get_softc(dev);
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if (phy < 0 || phy >= sc->phy_conf->num_phys)
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return (ERANGE);
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/* Configure PHY */
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awusbphy_configure(dev, phy);
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