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[PowerPC] [PowerPCSPE] Fix multiple issues in fpsetmask().

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Building R on powerpc64 exposed a problem in fpsetmask() whereby we
were not properly clamping the provided mask to the valid range.

This same issue affects powerpc and powerpcspe.

Properly limit the range of bits that can be set via fpsetmask().

While here, use the correct fp_except_t type instead of fp_rnd_t.

Reported by:	pkubaj, jhibbits (in IRC)
Sponsored by:	Tag1 Consulting, Inc.
MFC after:	1 week
This commit is contained in:
Brandon Bergren 2021-02-28 21:06:59 -06:00
parent dd95b39235
commit 384ee7cc6e
2 changed files with 6 additions and 6 deletions
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6
lib/libc/powerpc/gen/fpsetmask.c
View File

@ -43,11 +43,11 @@ fp_except_t
fpsetmask(fp_except_t mask)
{
u_int64_t fpscr;
fp_rnd_t old;
fp_except_t old;
__asm__("mffs %0" : "=f"(fpscr));
old = (fp_rnd_t)((fpscr >> 3) & 0x1f);
fpscr = (fpscr & 0xffffff07) | (mask << 3);
old = (fp_except_t)((fpscr >> 3) & 0x1f);
fpscr = (fpscr & 0xffffff07) | ((mask & 0x1f) << 3);
__asm__ __volatile("mtfsf 0xff,%0" :: "f"(fpscr));
return (old);
}

6
lib/libc/powerpcspe/gen/fpsetmask.c
View File

@ -42,11 +42,11 @@ fp_except_t
fpsetmask(fp_except_t mask)
{
uint32_t fpscr;
fp_rnd_t old;
fp_except_t old;
__asm__ __volatile("mfspr %0, %1" : "=r"(fpscr) : "K"(SPR_SPEFSCR));
old = (fp_rnd_t)((fpscr >> 2) & 0x1f);
fpscr = (fpscr & 0xffffff83) | (mask << 2);
old = (fp_except_t)((fpscr >> 2) & 0x1f);
fpscr = (fpscr & 0xffffff83) | ((mask & 0x1f) << 2);
__asm__ __volatile("mtspr %1,%0;isync" :: "r"(fpscr), "K"(SPR_SPEFSCR));
return (old);
}