iir: Remove
Belatedly remove iir(4). It was slated to go before 13, but was overlooked. Sponsored by: Netflix Relnotes: yes Reviewed by: scottl Differential Revision: https://reviews.freebsd.org/D33112
This commit is contained in:
Warner Losh
parent
a9620045a5
commit
399188a2c6
@ -223,7 +223,6 @@ MAN= aac.4 \
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iichid.4 \
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iicmux.4 \
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iicsmb.4 \
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iir.4 \
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${_igc.4} \
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${_imcsmb.4} \
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inet.4 \
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@ -1,82 +0,0 @@
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.\" $FreeBSD$
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.\" Written by Tom Rhodes
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.\" This file is in the public domain.
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.\"
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.Dd August 8, 2004
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.Dt IIR 4
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.Os
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.Sh NAME
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.Nm iir
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.Nd Intel Integrated RAID controller and ICP Vortex driver
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.Sh DEPRECATION NOTICE
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The
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.Nm
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driver is not present in
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.Fx 13.0 .
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.Sh SYNOPSIS
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To compile this driver into the kernel,
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place the following lines in your
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kernel configuration file:
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.Bd -ragged -offset indent
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.Cd "device pci"
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.Cd "device scbus"
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.Cd "device iir"
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.Ed
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.Pp
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Alternatively, to load the driver as a
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module at boot time, place the following line in
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.Xr loader.conf 5 :
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.Bd -literal -offset indent
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iir_load="YES"
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.Ed
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.Sh DESCRIPTION
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The
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.Nm
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driver claims to interface with the Intel integrated
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RAID controller cards, and all versions of the
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ICP Vortex controllers (including FC).
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.Sh HARDWARE
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Controllers supported by the
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.Nm
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driver include:
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.Pp
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.Bl -bullet -compact
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.It
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Intel RAID Controller SRCMR
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.It
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Intel Server RAID Controller U3-l (SRCU31a)
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.It
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Intel Server RAID Controller U3-1L (SRCU31La)
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.It
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Intel Server RAID Controller U3-2 (SRCU32)
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.It
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All past and future releases of Intel and ICP RAID Controllers.
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.El
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.Pp
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.Bl -bullet -compact
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.It
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Intel RAID Controller SRCU21 (discontinued)
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.It
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Intel RAID Controller SRCU31 (older revision, not compatible)
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.It
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Intel RAID Controller SRCU31L (older revision, not compatible)
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.El
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.Pp
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The SRCU31 and SRCU31L can be updated via a firmware update available
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from Intel.
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.Sh SEE ALSO
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.Xr cam 4 ,
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.Xr pass 4 ,
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.Xr xpt 4 ,
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.Xr camcontrol 8
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.Sh AUTHORS
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The
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.Nm
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driver is supported and maintained by
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.An -nosplit
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.An Achim Leubner Aq Mt Achim_Leubner@adaptec.com .
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.Pp
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This manual page was written by
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.An Tom Rhodes Aq Mt trhodes@FreeBSD.org
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and is based on information supplied by the driver authors and the website of
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.An Mike Smith Aq Mt msmith@FreeBSD.org .
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@ -183,7 +183,6 @@ device ses # Enclosure Services (SES and SAF-TE)
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device amr # AMI MegaRAID
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device arcmsr # Areca SATA II RAID
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device ciss # Compaq Smart RAID 5*
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device iir # Intel Integrated RAID
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device ips # IBM (Adaptec) ServeRAID
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device twa # 3ware 9000 series PATA/SATA RAID
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device smartpqi # Microsemi smartpqi driver
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@ -1635,15 +1635,6 @@ options ISP_DEFAULT_ROLES=0
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#
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device ciss
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#
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# Intel Integrated RAID controllers.
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# This driver was developed and is maintained by Intel. Contacts
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# at Intel for this driver are
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# "Kannanthanam, Boji T" <boji.t.kannanthanam@intel.com> and
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# "Leubner, Achim" <achim.leubner@intel.com>.
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#
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device iir
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#
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# Compaq Smart RAID, Mylex DAC960 and AMI MegaRAID controllers. Only
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# one entry is needed; the code will find and configure all supported
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@ -1874,9 +1874,6 @@ dev/iicbus/syr827.c optional syr827 ext_resources fdt
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dev/iicbus/gpio/tca6408.c optional tca6408 fdt gpio
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dev/iicbus/gpio/tca6416.c optional tca6416 fdt
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dev/iicbus/pmic/fan53555.c optional fan53555 ext_resources fdt
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dev/iir/iir.c optional iir
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dev/iir/iir_ctrl.c optional iir
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dev/iir/iir_pci.c optional iir pci
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dev/igc/if_igc.c optional igc iflib pci
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dev/igc/igc_api.c optional igc iflib pci
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dev/igc/igc_base.c optional igc iflib pci
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1914
sys/dev/iir/iir.c
1914
sys/dev/iir/iir.c
File diff suppressed because it is too large
Load Diff
@ -1,754 +0,0 @@
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/* $FreeBSD$ */
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/*-
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2000-04 ICP vortex GmbH
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* Copyright (c) 2002-04 Intel Corporation
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* Copyright (c) 2003-04 Adaptec Inc.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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*
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* iir.h: Definitions/Constants used by the Intel Integrated RAID driver
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*
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* Written by: Achim Leubner <achim_leubner@adaptec.com>
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* Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com>
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*
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* credits: Niklas Hallqvist; OpenBSD driver for the ICP Controllers.
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* FreeBSD.ORG; Great O/S to work on and for.
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*
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* $Id: iir.h 1.6 2004/03/30 10:19:44 achim Exp $"
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*/
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#ifndef _IIR_H
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#define _IIR_H
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#ifndef _SYS_CDEFS_H_
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#error this file needs sys/cdefs.h as a prerequisite
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#endif
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#define IIR_DRIVER_VERSION 1
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#define IIR_DRIVER_SUBVERSION 5
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/* OEM IDs */
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#define OEM_ID_ICP 0x941c
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#define OEM_ID_INTEL 0x8000
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#define GDT_VENDOR_ID 0x1119
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#define GDT_DEVICE_ID_MIN 0x100
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#define GDT_DEVICE_ID_MAX 0x2ff
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#define GDT_DEVICE_ID_NEWRX 0x300
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#define INTEL_VENDOR_ID_IIR 0x8086
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#define INTEL_DEVICE_ID_IIR 0x600
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#define GDT_MAXBUS 6 /* XXX Why not 5? */
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#define GDT_MAX_HDRIVES 100 /* max 100 host drives */
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#define GDT_MAXID_FC 127 /* Fibre-channel IDs */
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#define GDT_MAXID 16 /* SCSI IDs */
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#define GDT_MAXOFFSETS 128
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#define GDT_MAXSG 32 /* Max. s/g elements */
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#define GDT_PROTOCOL_VERSION 1
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#define GDT_LINUX_OS 8 /* Used for cache optimization */
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#define GDT_SCATTER_GATHER 1 /* s/g feature */
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#define GDT_SECS32 0x1f /* round capacity */
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#define GDT_LOCALBOARD 0 /* Board node always 0 */
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#define GDT_MAXCMDS 124
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#define GDT_SECTOR_SIZE 0x200 /* Always 512 bytes for cache devs */
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#define GDT_MAX_EVENTS 0x100 /* event buffer */
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/* DPMEM constants */
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#define GDT_MPR_MAGIC 0xc0ffee11
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#define GDT_IC_HEADER_BYTES 48
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#define GDT_IC_QUEUE_BYTES 4
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#define GDT_DPMEM_COMMAND_OFFSET \
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(GDT_IC_HEADER_BYTES + GDT_IC_QUEUE_BYTES * GDT_MAXOFFSETS)
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/* geometry constants */
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#define GDT_MAXCYLS 1024
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#define GDT_HEADS 64
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#define GDT_SECS 32 /* mapping 64*32 */
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#define GDT_MEDHEADS 127
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#define GDT_MEDSECS 63 /* mapping 127*63 */
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#define GDT_BIGHEADS 255
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#define GDT_BIGSECS 63 /* mapping 255*63 */
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/* data direction raw service */
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#define GDT_DATA_IN 0x01000000L
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#define GDT_DATA_OUT 0x00000000L
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/* Cache/raw service commands */
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#define GDT_INIT 0 /* service initialization */
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#define GDT_READ 1 /* read command */
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#define GDT_WRITE 2 /* write command */
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#define GDT_INFO 3 /* information about devices */
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#define GDT_FLUSH 4 /* flush dirty cache buffers */
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#define GDT_IOCTL 5 /* ioctl command */
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#define GDT_DEVTYPE 9 /* additional information */
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#define GDT_MOUNT 10 /* mount cache device */
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#define GDT_UNMOUNT 11 /* unmount cache device */
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#define GDT_SET_FEAT 12 /* set features (scatter/gather) */
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#define GDT_GET_FEAT 13 /* get features */
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#define GDT_WRITE_THR 16 /* write through */
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#define GDT_READ_THR 17 /* read through */
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#define GDT_EXT_INFO 18 /* extended info */
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#define GDT_RESET 19 /* controller reset */
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#define GDT_FREEZE_IO 25 /* freeze all IOs */
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#define GDT_UNFREEZE_IO 26 /* unfreeze all IOs */
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/* Additional raw service commands */
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#define GDT_RESERVE 14 /* reserve device to raw service */
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#define GDT_RELEASE 15 /* release device */
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#define GDT_RESERVE_ALL 16 /* reserve all devices */
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#define GDT_RELEASE_ALL 17 /* release all devices */
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#define GDT_RESET_BUS 18 /* reset bus */
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#define GDT_SCAN_START 19 /* start device scan */
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#define GDT_SCAN_END 20 /* stop device scan */
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/* IOCTL command defines */
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#define GDT_SCSI_DR_INFO 0x00 /* SCSI drive info */
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#define GDT_SCSI_CHAN_CNT 0x05 /* SCSI channel count */
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#define GDT_SCSI_DR_LIST 0x06 /* SCSI drive list */
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#define GDT_SCSI_DEF_CNT 0x15 /* grown/primary defects */
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#define GDT_DSK_STATISTICS 0x4b /* SCSI disk statistics */
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#define GDT_IOCHAN_DESC 0x5d /* description of IO channel */
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#define GDT_IOCHAN_RAW_DESC 0x5e /* description of raw IO channel */
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#define GDT_L_CTRL_PATTERN 0x20000000 /* SCSI IOCTL mask */
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#define GDT_ARRAY_INFO 0x12 /* array drive info */
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#define GDT_ARRAY_DRV_LIST 0x0f /* array drive list */
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#define GDT_LA_CTRL_PATTERN 0x10000000 /* array IOCTL mask */
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#define GDT_CACHE_DRV_CNT 0x01 /* cache drive count */
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#define GDT_CACHE_DRV_LIST 0x02 /* cache drive list */
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#define GDT_CACHE_INFO 0x04 /* cache info */
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#define GDT_CACHE_CONFIG 0x05 /* cache configuration */
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#define GDT_CACHE_DRV_INFO 0x07 /* cache drive info */
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#define GDT_BOARD_FEATURES 0x15 /* controller features */
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#define GDT_BOARD_INFO 0x28 /* controller info */
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#define GDT_OEM_STR_RECORD 0x84 /* OEM info */
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#define GDT_HOST_GET 0x10001 /* get host drive list */
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#define GDT_IO_CHANNEL 0x20000 /* default IO channel */
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#define GDT_INVALID_CHANNEL 0xffff /* invalid channel */
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/* IOCTLs */
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#define GDT_IOCTL_GENERAL _IOWR('J', 0, gdt_ucmd_t) /* general IOCTL */
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#define GDT_IOCTL_DRVERS _IOR('J', 1, int) /* get driver version */
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#define GDT_IOCTL_CTRTYPE _IOWR('J', 2, gdt_ctrt_t) /* get ctr. type */
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#define GDT_IOCTL_DRVERS_OLD _IOWR('J', 1, int) /* get driver version */
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#define GDT_IOCTL_CTRTYPE_OLD _IOR('J', 2, gdt_ctrt_t) /* get ctr. type */
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#define GDT_IOCTL_OSVERS _IOR('J', 3, gdt_osv_t) /* get OS version */
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#define GDT_IOCTL_CTRCNT _IOR('J', 5, int) /* get ctr. count */
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#define GDT_IOCTL_EVENT _IOWR('J', 8, gdt_event_t) /* get event */
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#define GDT_IOCTL_STATIST _IOR('J', 9, gdt_statist_t) /* get statistics */
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/* Service errors */
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#define GDT_S_OK 1 /* no error */
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#define GDT_S_BSY 7 /* controller busy */
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#define GDT_S_RAW_SCSI 12 /* raw service: target error */
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#define GDT_S_RAW_ILL 0xff /* raw service: illegal */
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#define GDT_S_NO_STATUS 0x1000 /* got no status (driver-generated) */
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/* Controller services */
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#define GDT_SCSIRAWSERVICE 3
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#define GDT_CACHESERVICE 9
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#define GDT_SCREENSERVICE 11
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/* Scatter/gather element */
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#define GDT_SG_PTR 0x00 /* u_int32_t, address */
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#define GDT_SG_LEN 0x04 /* u_int32_t, length */
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#define GDT_SG_SZ 0x08
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/* Cache service command */
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#define GDT_CACHE_DEVICENO 0x00 /* u_int16_t, number of cache drive */
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#define GDT_CACHE_BLOCKNO 0x02 /* u_int32_t, block number */
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#define GDT_CACHE_BLOCKCNT 0x06 /* u_int32_t, block count */
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#define GDT_CACHE_DESTADDR 0x0a /* u_int32_t, dest. addr. (-1: s/g) */
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#define GDT_CACHE_SG_CANZ 0x0e /* u_int32_t, s/g element count */
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#define GDT_CACHE_SG_LST 0x12 /* [GDT_MAXSG], s/g list */
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#define GDT_CACHE_SZ (0x12 + GDT_MAXSG * GDT_SG_SZ)
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/* Ioctl command */
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#define GDT_IOCTL_PARAM_SIZE 0x00 /* u_int16_t, size of buffer */
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#define GDT_IOCTL_SUBFUNC 0x02 /* u_int32_t, ioctl function */
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#define GDT_IOCTL_CHANNEL 0x06 /* u_int32_t, device */
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#define GDT_IOCTL_P_PARAM 0x0a /* u_int32_t, buffer */
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#define GDT_IOCTL_SZ 0x0e
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/* Screen service defines */
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#define GDT_MSG_INV_HANDLE -1 /* special message handle */
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#define GDT_MSGLEN 16 /* size of message text */
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#define GDT_MSG_SIZE 34 /* size of message structure */
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#define GDT_MSG_REQUEST 0 /* async. event. message */
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/* Screen service command */
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#define GDT_SCREEN_MSG_HANDLE 0x02 /* u_int32_t, message handle */
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#define GDT_SCREEN_MSG_ADDR 0x06 /* u_int32_t, message buffer address */
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#define GDT_SCREEN_SZ 0x0a
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/* Screen service message */
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#define GDT_SCR_MSG_HANDLE 0x00 /* u_int32_t, message handle */
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#define GDT_SCR_MSG_LEN 0x04 /* u_int32_t, size of message */
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#define GDT_SCR_MSG_ALEN 0x08 /* u_int32_t, answer length */
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#define GDT_SCR_MSG_ANSWER 0x0c /* u_int8_t, answer flag */
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#define GDT_SCR_MSG_EXT 0x0d /* u_int8_t, more messages? */
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#define GDT_SCR_MSG_RES 0x0e /* u_int16_t, reserved */
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#define GDT_SCR_MSG_TEXT 0x10 /* GDT_MSGLEN+2, message text */
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#define GDT_SCR_MSG_SZ (0x12 + GDT_MSGLEN)
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/* Raw service command */
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#define GDT_RAW_DIRECTION 0x02 /* u_int32_t, data direction */
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#define GDT_RAW_MDISC_TIME 0x06 /* u_int32_t, disc. time (0: none) */
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#define GDT_RAW_MCON_TIME 0x0a /* u_int32_t, conn. time (0: none) */
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#define GDT_RAW_SDATA 0x0e /* u_int32_t, dest. addr. (-1: s/g) */
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#define GDT_RAW_SDLEN 0x12 /* u_int32_t, data length */
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#define GDT_RAW_CLEN 0x16 /* u_int32_t, SCSI cmd len (6/10/12) */
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#define GDT_RAW_CMD 0x1a /* u_int8_t [12], SCSI command */
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#define GDT_RAW_TARGET 0x26 /* u_int8_t, target ID */
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#define GDT_RAW_LUN 0x27 /* u_int8_t, LUN */
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#define GDT_RAW_BUS 0x28 /* u_int8_t, SCSI bus number */
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#define GDT_RAW_PRIORITY 0x29 /* u_int8_t, only 0 used */
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#define GDT_RAW_SENSE_LEN 0x2a /* u_int32_t, sense data length */
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#define GDT_RAW_SENSE_DATA 0x2e /* u_int32_t, sense data address */
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#define GDT_RAW_SG_RANZ 0x36 /* u_int32_t, s/g element count */
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#define GDT_RAW_SG_LST 0x3a /* [GDT_MAXSG], s/g list */
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#define GDT_RAW_SZ (0x3a + GDT_MAXSG * GDT_SG_SZ)
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/* Command structure */
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#define GDT_CMD_BOARDNODE 0x00 /* u_int32_t, board node (always 0) */
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#define GDT_CMD_COMMANDINDEX 0x04 /* u_int32_t, command number */
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#define GDT_CMD_OPCODE 0x08 /* u_int16_t, opcode (READ, ...) */
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#define GDT_CMD_UNION 0x0a /* cache/screen/raw service command */
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#define GDT_CMD_UNION_SZ GDT_RAW_SZ
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#define GDT_CMD_SZ (0x0a + GDT_CMD_UNION_SZ)
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/* Command queue entries */
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#define GDT_OFFSET 0x00 /* u_int16_t, command offset in the DP RAM */
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||||
#define GDT_SERV_ID 0x02 /* u_int16_t, service */
|
||||
#define GDT_COMM_Q_SZ 0x04
|
||||
|
||||
/* Interface area */
|
||||
#define GDT_S_CMD_INDX 0x00 /* u_int8_t, special command */
|
||||
#define GDT_S_STATUS 0x01 /* volatile u_int8_t, status special command */
|
||||
#define GDT_S_INFO 0x04 /* u_int32_t [4], add. info special command */
|
||||
#define GDT_SEMA0 0x14 /* volatile u_int8_t, command semaphore */
|
||||
#define GDT_CMD_INDEX 0x18 /* u_int8_t, command number */
|
||||
#define GDT_STATUS 0x1c /* volatile u_int16_t, command status */
|
||||
#define GDT_SERVICE 0x1e /* u_int16_t, service (for asynch. events) */
|
||||
#define GDT_DPR_INFO 0x20 /* u_int32_t [2], additional info */
|
||||
#define GDT_COMM_QUEUE 0x28 /* command queue */
|
||||
#define GDT_DPR_CMD (0x30 + GDT_MAXOFFSETS * GDT_COMM_Q_SZ)
|
||||
/* u_int8_t [], commands */
|
||||
|
||||
/* I/O channel header */
|
||||
#define GDT_IOC_VERSION 0x00 /* u_int32_t, version (~0: newest) */
|
||||
#define GDT_IOC_LIST_ENTRIES 0x04 /* u_int8_t, list entry count */
|
||||
#define GDT_IOC_FIRST_CHAN 0x05 /* u_int8_t, first channel number */
|
||||
#define GDT_IOC_LAST_CHAN 0x06 /* u_int8_t, last channel number */
|
||||
#define GDT_IOC_CHAN_COUNT 0x07 /* u_int8_t, (R) channel count */
|
||||
#define GDT_IOC_LIST_OFFSET 0x08 /* u_int32_t, offset of list[0] */
|
||||
#define GDT_IOC_HDR_SZ 0x0c
|
||||
|
||||
#define GDT_IOC_NEWEST 0xffffffff /* goes into GDT_IOC_VERSION */
|
||||
|
||||
/* Get I/O channel description */
|
||||
#define GDT_IOC_ADDRESS 0x00 /* u_int32_t, channel address */
|
||||
#define GDT_IOC_TYPE 0x04 /* u_int8_t, type (SCSI/FCSL) */
|
||||
#define GDT_IOC_LOCAL_NO 0x05 /* u_int8_t, local number */
|
||||
#define GDT_IOC_FEATURES 0x06 /* u_int16_t, channel features */
|
||||
#define GDT_IOC_SZ 0x08
|
||||
|
||||
/* Get raw I/O channel description */
|
||||
#define GDT_RAWIOC_PROC_ID 0x00 /* u_int8_t, processor id */
|
||||
#define GDT_RAWIOC_PROC_DEFECT 0x01 /* u_int8_t, defect? */
|
||||
#define GDT_RAWIOC_SZ 0x04
|
||||
|
||||
/* Get SCSI channel count */
|
||||
#define GDT_GETCH_CHANNEL_NO 0x00 /* u_int32_t, channel number */
|
||||
#define GDT_GETCH_DRIVE_CNT 0x04 /* u_int32_t, drive count */
|
||||
#define GDT_GETCH_SIOP_ID 0x08 /* u_int8_t, SCSI processor ID */
|
||||
#define GDT_GETCH_SIOP_STATE 0x09 /* u_int8_t, SCSI processor state */
|
||||
#define GDT_GETCH_SZ 0x0a
|
||||
|
||||
/* Cache info/config IOCTL structures */
|
||||
#define GDT_CPAR_VERSION 0x00 /* u_int32_t, firmware version */
|
||||
#define GDT_CPAR_STATE 0x04 /* u_int16_t, cache state (on/off) */
|
||||
#define GDT_CPAR_STRATEGY 0x06 /* u_int16_t, cache strategy */
|
||||
#define GDT_CPAR_WRITE_BACK 0x08 /* u_int16_t, write back (on/off) */
|
||||
#define GDT_CPAR_BLOCK_SIZE 0x0a /* u_int16_t, cache block size */
|
||||
#define GDT_CPAR_SZ 0x0c
|
||||
|
||||
#define GDT_CSTAT_CSIZE 0x00 /* u_int32_t, cache size */
|
||||
#define GDT_CSTAT_READ_CNT 0x04 /* u_int32_t, read counter */
|
||||
#define GDT_CSTAT_WRITE_CNT 0x08 /* u_int32_t, write counter */
|
||||
#define GDT_CSTAT_TR_HITS 0x0c /* u_int32_t, track hits */
|
||||
#define GDT_CSTAT_SEC_HITS 0x10 /* u_int32_t, sector hits */
|
||||
#define GDT_CSTAT_SEC_MISS 0x14 /* u_int32_t, sector misses */
|
||||
#define GDT_CSTAT_SZ 0x18
|
||||
|
||||
/* Get cache info */
|
||||
#define GDT_CINFO_CPAR 0x00
|
||||
#define GDT_CINFO_CSTAT GDT_CPAR_SZ
|
||||
#define GDT_CINFO_SZ (GDT_CPAR_SZ + GDT_CSTAT_SZ)
|
||||
|
||||
/* Get board info */
|
||||
#define GDT_BINFO_SER_NO 0x00 /* u_int32_t, serial number */
|
||||
#define GDT_BINFO_OEM_ID 0x04 /* u_int8_t [2], OEM ID */
|
||||
#define GDT_BINFO_EP_FLAGS 0x06 /* u_int16_t, eprom flags */
|
||||
#define GDT_BINFO_PROC_ID 0x08 /* u_int32_t, processor ID */
|
||||
#define GDT_BINFO_MEMSIZE 0x0c /* u_int32_t, memory size (bytes) */
|
||||
#define GDT_BINFO_MEM_BANKS 0x10 /* u_int8_t, memory banks */
|
||||
#define GDT_BINFO_CHAN_TYPE 0x11 /* u_int8_t, channel type */
|
||||
#define GDT_BINFO_CHAN_COUNT 0x12 /* u_int8_t, channel count */
|
||||
#define GDT_BINFO_RDONGLE_PRES 0x13 /* u_int8_t, dongle present */
|
||||
#define GDT_BINFO_EPR_FW_VER 0x14 /* u_int32_t, (eprom) firmware ver */
|
||||
#define GDT_BINFO_UPD_FW_VER 0x18 /* u_int32_t, (update) firmware ver */
|
||||
#define GDT_BINFO_UPD_REVISION 0x1c /* u_int32_t, update revision */
|
||||
#define GDT_BINFO_TYPE_STRING 0x20 /* char [16], controller name */
|
||||
#define GDT_BINFO_RAID_STRING 0x30 /* char [16], RAID firmware name */
|
||||
#define GDT_BINFO_UPDATE_PRES 0x40 /* u_int8_t, update present? */
|
||||
#define GDT_BINFO_XOR_PRES 0x41 /* u_int8_t, XOR engine present */
|
||||
#define GDT_BINFO_PROM_TYPE 0x42 /* u_int8_t, ROM type (eprom/flash) */
|
||||
#define GDT_BINFO_PROM_COUNT 0x43 /* u_int8_t, number of ROM devices */
|
||||
#define GDT_BINFO_DUP_PRES 0x44 /* u_int32_t, duplexing module pres? */
|
||||
#define GDT_BINFO_CHAN_PRES 0x48 /* u_int32_t, # of exp. channels */
|
||||
#define GDT_BINFO_MEM_PRES 0x4c /* u_int32_t, memory expansion inst? */
|
||||
#define GDT_BINFO_FT_BUS_SYSTEM 0x50 /* u_int8_t, fault bus supported? */
|
||||
#define GDT_BINFO_SUBTYPE_VALID 0x51 /* u_int8_t, board_subtype valid */
|
||||
#define GDT_BINFO_BOARD_SUBTYPE 0x52 /* u_int8_t, subtype/hardware level */
|
||||
#define GDT_BINFO_RAMPAR_PRES 0x53 /* u_int8_t, RAM parity check hw? */
|
||||
#define GDT_BINFO_SZ 0x54
|
||||
|
||||
/* Get board features */
|
||||
#define GDT_BFEAT_CHAINING 0x00 /* u_int8_t, chaining supported */
|
||||
#define GDT_BFEAT_STRIPING 0x01 /* u_int8_t, striping (RAID-0) supp. */
|
||||
#define GDT_BFEAT_MIRRORING 0x02 /* u_int8_t, mirroring (RAID-1) supp */
|
||||
#define GDT_BFEAT_RAID 0x03 /* u_int8_t, RAID-4/5/10 supported */
|
||||
#define GDT_BFEAT_SZ 0x04
|
||||
|
||||
/* Other defines */
|
||||
#define GDT_ASYNCINDEX 0 /* command index asynchronous event */
|
||||
#define GDT_SPEZINDEX 1 /* command index unknown service */
|
||||
|
||||
/* Debugging */
|
||||
#ifdef GDT_DEBUG
|
||||
#define GDT_D_INTR 0x01
|
||||
#define GDT_D_MISC 0x02
|
||||
#define GDT_D_CMD 0x04
|
||||
#define GDT_D_QUEUE 0x08
|
||||
#define GDT_D_TIMEOUT 0x10
|
||||
#define GDT_D_INIT 0x20
|
||||
#define GDT_D_INVALID 0x40
|
||||
#define GDT_D_DEBUG 0x80
|
||||
extern int gdt_debug;
|
||||
#ifdef __SERIAL__
|
||||
extern int ser_printf(const char *fmt, ...);
|
||||
#define GDT_DPRINTF(mask, args) if (gdt_debug & (mask)) ser_printf args
|
||||
#else
|
||||
#define GDT_DPRINTF(mask, args) if (gdt_debug & (mask)) printf args
|
||||
#endif
|
||||
#else
|
||||
#define GDT_DPRINTF(mask, args)
|
||||
#endif
|
||||
|
||||
/* Miscellaneous constants */
|
||||
#define GDT_RETRIES 100000000 /* 100000 * 1us = 100s */
|
||||
#define GDT_TIMEOUT 100000000 /* 100000 * 1us = 100s */
|
||||
#define GDT_POLL_TIMEOUT 10000000 /* 10000 * 1us = 10s */
|
||||
#define GDT_WATCH_TIMEOUT 10000000 /* 10000 * 1us = 10s */
|
||||
#define GDT_SCRATCH_SZ 3072 /* 3KB scratch buffer */
|
||||
|
||||
/* Map minor numbers to device identity */
|
||||
#define LUN_MASK 0x0007
|
||||
#define TARGET_MASK 0x03f8
|
||||
#define BUS_MASK 0x1c00
|
||||
#define HBA_MASK 0xe000
|
||||
|
||||
#define minor2lun(minor) ( minor & LUN_MASK )
|
||||
#define minor2target(minor) ( (minor & TARGET_MASK) >> 3 )
|
||||
#define minor2bus(minor) ( (minor & BUS_MASK) >> 10 )
|
||||
#define minor2hba(minor) ( (minor & HBA_MASK) >> 13 )
|
||||
#define hba2minor(hba) ( (hba << 13) & HBA_MASK )
|
||||
|
||||
|
||||
/* struct for GDT_IOCTL_GENERAL */
|
||||
#pragma pack(1)
|
||||
typedef struct gdt_ucmd {
|
||||
u_int16_t io_node;
|
||||
u_int16_t service;
|
||||
u_int32_t timeout;
|
||||
u_int16_t status;
|
||||
u_int32_t info;
|
||||
|
||||
u_int32_t BoardNode; /* board node (always 0) */
|
||||
u_int32_t CommandIndex; /* command number */
|
||||
u_int16_t OpCode; /* the command (READ,..) */
|
||||
union {
|
||||
struct {
|
||||
u_int16_t DeviceNo; /* number of cache drive */
|
||||
u_int32_t BlockNo; /* block number */
|
||||
u_int32_t BlockCnt; /* block count */
|
||||
void *DestAddr; /* data */
|
||||
} cache; /* cache service cmd. str. */
|
||||
struct {
|
||||
u_int16_t param_size; /* size of p_param buffer */
|
||||
u_int32_t subfunc; /* IOCTL function */
|
||||
u_int32_t channel; /* device */
|
||||
void *p_param; /* data */
|
||||
} ioctl; /* IOCTL command structure */
|
||||
struct {
|
||||
u_int16_t reserved;
|
||||
u_int32_t direction; /* data direction */
|
||||
u_int32_t mdisc_time; /* disc. time (0: no timeout)*/
|
||||
u_int32_t mcon_time; /* connect time(0: no to.) */
|
||||
void *sdata; /* dest. addr. (if s/g: -1) */
|
||||
u_int32_t sdlen; /* data length (bytes) */
|
||||
u_int32_t clen; /* SCSI cmd. length(6,10,12) */
|
||||
u_int8_t cmd[12]; /* SCSI command */
|
||||
u_int8_t target; /* target ID */
|
||||
u_int8_t lun; /* LUN */
|
||||
u_int8_t bus; /* SCSI bus number */
|
||||
u_int8_t priority; /* only 0 used */
|
||||
u_int32_t sense_len; /* sense data length */
|
||||
void *sense_data; /* sense data addr. */
|
||||
u_int32_t link_p; /* linked cmds (not supp.) */
|
||||
} raw; /* raw service cmd. struct. */
|
||||
} u;
|
||||
u_int8_t data[GDT_SCRATCH_SZ];
|
||||
int complete_flag;
|
||||
TAILQ_ENTRY(gdt_ucmd) links;
|
||||
} gdt_ucmd_t;
|
||||
|
||||
/* struct for GDT_IOCTL_CTRTYPE */
|
||||
typedef struct gdt_ctrt {
|
||||
u_int16_t io_node;
|
||||
u_int16_t oem_id;
|
||||
u_int16_t type;
|
||||
u_int32_t info;
|
||||
u_int8_t access;
|
||||
u_int8_t remote;
|
||||
u_int16_t ext_type;
|
||||
u_int16_t device_id;
|
||||
u_int16_t sub_device_id;
|
||||
} gdt_ctrt_t;
|
||||
|
||||
/* struct for GDT_IOCTL_OSVERS */
|
||||
typedef struct gdt_osv {
|
||||
u_int8_t oscode;
|
||||
u_int8_t version;
|
||||
u_int8_t subversion;
|
||||
u_int16_t revision;
|
||||
char name[64];
|
||||
} gdt_osv_t;
|
||||
|
||||
/* OEM */
|
||||
#define GDT_OEM_VERSION 0x00
|
||||
#define GDT_OEM_BUFSIZE 0x0c
|
||||
typedef struct {
|
||||
u_int32_t ctl_version;
|
||||
u_int32_t file_major_version;
|
||||
u_int32_t file_minor_version;
|
||||
u_int32_t buffer_size;
|
||||
u_int32_t cpy_count;
|
||||
u_int32_t ext_error;
|
||||
u_int32_t oem_id;
|
||||
u_int32_t board_id;
|
||||
} gdt_oem_param_t;
|
||||
|
||||
typedef struct {
|
||||
char product_0_1_name[16];
|
||||
char product_4_5_name[16];
|
||||
char product_cluster_name[16];
|
||||
char product_reserved[16];
|
||||
char scsi_cluster_target_vendor_id[16];
|
||||
char cluster_raid_fw_name[16];
|
||||
char oem_brand_name[16];
|
||||
char oem_raid_type[16];
|
||||
char bios_type[13];
|
||||
char bios_title[50];
|
||||
char oem_company_name[37];
|
||||
u_int32_t pci_id_1;
|
||||
u_int32_t pci_id_2;
|
||||
char validation_status[80];
|
||||
char reserved_1[4];
|
||||
char scsi_host_drive_inquiry_vendor_id[16];
|
||||
char library_file_template[32];
|
||||
char tool_name_1[32];
|
||||
char tool_name_2[32];
|
||||
char tool_name_3[32];
|
||||
char oem_contact_1[84];
|
||||
char oem_contact_2[84];
|
||||
char oem_contact_3[84];
|
||||
} gdt_oem_record_t;
|
||||
|
||||
typedef struct {
|
||||
gdt_oem_param_t parameters;
|
||||
gdt_oem_record_t text;
|
||||
} gdt_oem_str_record_t;
|
||||
|
||||
|
||||
/* controller event structure */
|
||||
#define GDT_ES_ASYNC 1
|
||||
#define GDT_ES_DRIVER 2
|
||||
#define GDT_ES_TEST 3
|
||||
#define GDT_ES_SYNC 4
|
||||
typedef struct {
|
||||
u_int16_t size; /* size of structure */
|
||||
union {
|
||||
char stream[16];
|
||||
struct {
|
||||
u_int16_t ionode;
|
||||
u_int16_t service;
|
||||
u_int32_t index;
|
||||
} driver;
|
||||
struct {
|
||||
u_int16_t ionode;
|
||||
u_int16_t service;
|
||||
u_int16_t status;
|
||||
u_int32_t info;
|
||||
u_int8_t scsi_coord[3];
|
||||
} async;
|
||||
struct {
|
||||
u_int16_t ionode;
|
||||
u_int16_t service;
|
||||
u_int16_t status;
|
||||
u_int32_t info;
|
||||
u_int16_t hostdrive;
|
||||
u_int8_t scsi_coord[3];
|
||||
u_int8_t sense_key;
|
||||
} sync;
|
||||
struct {
|
||||
u_int32_t l1, l2, l3, l4;
|
||||
} test;
|
||||
} eu;
|
||||
u_int32_t severity;
|
||||
u_int8_t event_string[256];
|
||||
} gdt_evt_data;
|
||||
|
||||
/* dvrevt structure */
|
||||
typedef struct {
|
||||
u_int32_t first_stamp;
|
||||
u_int32_t last_stamp;
|
||||
u_int16_t same_count;
|
||||
u_int16_t event_source;
|
||||
u_int16_t event_idx;
|
||||
u_int8_t application;
|
||||
u_int8_t reserved;
|
||||
gdt_evt_data event_data;
|
||||
} gdt_evt_str;
|
||||
|
||||
/* struct for GDT_IOCTL_EVENT */
|
||||
typedef struct gdt_event {
|
||||
int erase;
|
||||
int handle;
|
||||
gdt_evt_str dvr;
|
||||
} gdt_event_t;
|
||||
|
||||
/* struct for GDT_IOCTL_STATIST */
|
||||
typedef struct gdt_statist {
|
||||
u_int16_t io_count_act;
|
||||
u_int16_t io_count_max;
|
||||
u_int16_t req_queue_act;
|
||||
u_int16_t req_queue_max;
|
||||
u_int16_t cmd_index_act;
|
||||
u_int16_t cmd_index_max;
|
||||
u_int16_t sg_count_act;
|
||||
u_int16_t sg_count_max;
|
||||
} gdt_statist_t;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
/* Context structure for interrupt services */
|
||||
struct gdt_intr_ctx {
|
||||
u_int32_t info, info2;
|
||||
u_int16_t cmd_status, service;
|
||||
u_int8_t istatus;
|
||||
};
|
||||
|
||||
/* softc structure */
|
||||
struct gdt_softc {
|
||||
device_t sc_devnode;
|
||||
struct mtx sc_lock;
|
||||
int sc_hanum;
|
||||
int sc_class; /* Controller class */
|
||||
#define GDT_MPR 0x05
|
||||
#define GDT_CLASS_MASK 0x07
|
||||
#define GDT_FC 0x10
|
||||
#define GDT_CLASS(gdt) ((gdt)->sc_class & GDT_CLASS_MASK)
|
||||
int sc_bus, sc_slot;
|
||||
u_int16_t sc_vendor;
|
||||
u_int16_t sc_device, sc_subdevice;
|
||||
u_int16_t sc_fw_vers;
|
||||
int sc_init_level;
|
||||
int sc_state;
|
||||
#define GDT_NORMAL 0x00
|
||||
#define GDT_POLLING 0x01
|
||||
#define GDT_SHUTDOWN 0x02
|
||||
#define GDT_POLL_WAIT 0x80
|
||||
struct cdev *sc_dev;
|
||||
struct resource *sc_dpmem;
|
||||
bus_dma_tag_t sc_parent_dmat;
|
||||
bus_dma_tag_t sc_buffer_dmat;
|
||||
bus_dma_tag_t sc_gcscratch_dmat;
|
||||
bus_dmamap_t sc_gcscratch_dmamap;
|
||||
bus_addr_t sc_gcscratch_busbase;
|
||||
|
||||
struct gdt_ccb *sc_gccbs;
|
||||
u_int8_t *sc_gcscratch;
|
||||
SLIST_HEAD(, gdt_ccb) sc_free_gccb, sc_pending_gccb;
|
||||
TAILQ_HEAD(, ccb_hdr) sc_ccb_queue;
|
||||
TAILQ_HEAD(, gdt_ucmd) sc_ucmd_queue;
|
||||
|
||||
u_int16_t sc_ic_all_size;
|
||||
u_int16_t sc_cmd_off;
|
||||
u_int16_t sc_cmd_cnt;
|
||||
|
||||
u_int32_t sc_info;
|
||||
u_int32_t sc_info2;
|
||||
u_int16_t sc_status;
|
||||
u_int16_t sc_service;
|
||||
|
||||
u_int8_t sc_bus_cnt;
|
||||
u_int8_t sc_virt_bus;
|
||||
u_int8_t sc_bus_id[GDT_MAXBUS];
|
||||
u_int8_t sc_more_proc;
|
||||
|
||||
struct {
|
||||
u_int8_t hd_present;
|
||||
u_int8_t hd_is_logdrv;
|
||||
u_int8_t hd_is_arraydrv;
|
||||
u_int8_t hd_is_master;
|
||||
u_int8_t hd_is_parity;
|
||||
u_int8_t hd_is_hotfix;
|
||||
u_int8_t hd_master_no;
|
||||
u_int8_t hd_lock;
|
||||
u_int8_t hd_heads;
|
||||
u_int8_t hd_secs;
|
||||
u_int16_t hd_devtype;
|
||||
u_int32_t hd_size;
|
||||
u_int8_t hd_ldr_no;
|
||||
u_int8_t hd_rw_attribs;
|
||||
u_int32_t hd_start_sec;
|
||||
} sc_hdr[GDT_MAX_HDRIVES];
|
||||
|
||||
u_int16_t sc_raw_feat;
|
||||
u_int16_t sc_cache_feat;
|
||||
|
||||
gdt_evt_data sc_dvr;
|
||||
char oem_name[8];
|
||||
|
||||
struct cam_sim *sims[GDT_MAXBUS];
|
||||
struct cam_path *paths[GDT_MAXBUS];
|
||||
|
||||
void (*sc_copy_cmd)(struct gdt_softc *, struct gdt_ccb *);
|
||||
u_int8_t (*sc_get_status)(struct gdt_softc *);
|
||||
void (*sc_intr)(struct gdt_softc *, struct gdt_intr_ctx *);
|
||||
void (*sc_release_event)(struct gdt_softc *);
|
||||
void (*sc_set_sema0)(struct gdt_softc *);
|
||||
int (*sc_test_busy)(struct gdt_softc *);
|
||||
|
||||
TAILQ_ENTRY(gdt_softc) links;
|
||||
};
|
||||
|
||||
/*
|
||||
* A command control block, one for each corresponding command index of the
|
||||
* controller.
|
||||
*/
|
||||
struct gdt_ccb {
|
||||
u_int8_t *gc_scratch;
|
||||
bus_addr_t gc_scratch_busbase;
|
||||
union ccb *gc_ccb;
|
||||
gdt_ucmd_t *gc_ucmd;
|
||||
bus_dmamap_t gc_dmamap;
|
||||
struct callout gc_timeout;
|
||||
int gc_map_flag;
|
||||
u_int8_t gc_service;
|
||||
u_int8_t gc_cmd_index;
|
||||
u_int8_t gc_flags;
|
||||
#define GDT_GCF_UNUSED 0
|
||||
#define GDT_GCF_INTERNAL 1
|
||||
#define GDT_GCF_SCREEN 2
|
||||
#define GDT_GCF_SCSI 3
|
||||
#define GDT_GCF_IOCTL 4
|
||||
u_int16_t gc_cmd_len;
|
||||
u_int8_t gc_cmd[GDT_CMD_SZ];
|
||||
SLIST_ENTRY(gdt_ccb) sle;
|
||||
};
|
||||
|
||||
|
||||
int iir_init(struct gdt_softc *);
|
||||
void iir_free(struct gdt_softc *);
|
||||
void iir_attach(struct gdt_softc *);
|
||||
void iir_intr(void *arg);
|
||||
|
||||
#ifdef __CC_SUPPORTS___INLINE__
|
||||
/* These all require correctly aligned buffers */
|
||||
static __inline__ void gdt_enc16(u_int8_t *, u_int16_t);
|
||||
static __inline__ void gdt_enc32(u_int8_t *, u_int32_t);
|
||||
static __inline__ u_int16_t gdt_dec16(u_int8_t *);
|
||||
static __inline__ u_int32_t gdt_dec32(u_int8_t *);
|
||||
|
||||
static __inline__ void
|
||||
gdt_enc16(u_int8_t *addr, u_int16_t value)
|
||||
{
|
||||
*(u_int16_t *)addr = htole16(value);
|
||||
}
|
||||
|
||||
static __inline__ void
|
||||
gdt_enc32(u_int8_t *addr, u_int32_t value)
|
||||
{
|
||||
*(u_int32_t *)addr = htole32(value);
|
||||
}
|
||||
|
||||
static __inline__ u_int16_t
|
||||
gdt_dec16(u_int8_t *addr)
|
||||
{
|
||||
return le16toh(*(u_int16_t *)addr);
|
||||
}
|
||||
|
||||
static __inline__ u_int32_t
|
||||
gdt_dec32(u_int8_t *addr)
|
||||
{
|
||||
return le32toh(*(u_int32_t *)addr);
|
||||
}
|
||||
#endif
|
||||
|
||||
extern u_int8_t gdt_polling;
|
||||
|
||||
struct cdev *gdt_make_dev(struct gdt_softc *gdt);
|
||||
void gdt_destroy_dev(struct cdev *dev);
|
||||
void gdt_next(struct gdt_softc *gdt);
|
||||
void gdt_free_ccb(struct gdt_softc *gdt, struct gdt_ccb *gccb);
|
||||
|
||||
void gdt_store_event(u_int16_t source, u_int16_t idx,
|
||||
gdt_evt_data *evt);
|
||||
int gdt_read_event(int handle, gdt_evt_str *estr);
|
||||
void gdt_readapp_event(u_int8_t app, gdt_evt_str *estr);
|
||||
void gdt_clear_events(void);
|
||||
|
||||
#endif
|
||||
@ -1,312 +0,0 @@
|
||||
/*-
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Copyright (c) 2000-03 ICP vortex GmbH
|
||||
* Copyright (c) 2002-03 Intel Corporation
|
||||
* Copyright (c) 2003 Adaptec Inc.
|
||||
* All Rights Reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions, and the following disclaimer,
|
||||
* without modification, immediately at the beginning of the file.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* iir_ctrl.c: Control functions and /dev entry points for /dev/iir*
|
||||
*
|
||||
* Written by: Achim Leubner <achim_leubner@adaptec.com>
|
||||
* Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com>
|
||||
*
|
||||
* $Id: iir_ctrl.c 1.3 2003/08/26 12:31:15 achim Exp $"
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/conf.h>
|
||||
#include <sys/disk.h>
|
||||
#include <sys/disklabel.h>
|
||||
#include <sys/endian.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/lock.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/mutex.h>
|
||||
#include <sys/stat.h>
|
||||
#include <sys/sysctl.h>
|
||||
#include <sys/sx.h>
|
||||
#include <sys/uio.h>
|
||||
#include <machine/bus.h>
|
||||
|
||||
#include <dev/iir/iir.h>
|
||||
|
||||
/* Entry points and other prototypes */
|
||||
static struct gdt_softc *gdt_minor2softc(struct cdev *dev, int minor_no);
|
||||
|
||||
static d_open_t iir_open;
|
||||
static d_close_t iir_close;
|
||||
static d_write_t iir_write;
|
||||
static d_read_t iir_read;
|
||||
static d_ioctl_t iir_ioctl;
|
||||
|
||||
/* Normally, this is a static structure. But we need it in pci/iir_pci.c */
|
||||
static struct cdevsw iir_cdevsw = {
|
||||
.d_version = D_VERSION,
|
||||
.d_open = iir_open,
|
||||
.d_close = iir_close,
|
||||
.d_read = iir_read,
|
||||
.d_write = iir_write,
|
||||
.d_ioctl = iir_ioctl,
|
||||
.d_name = "iir",
|
||||
};
|
||||
|
||||
#ifndef SDEV_PER_HBA
|
||||
static int sdev_made = 0;
|
||||
static struct sx sdev_lock;
|
||||
SX_SYSINIT(iir_sdev_lock, &sdev_lock, "iir sdev");
|
||||
#endif
|
||||
extern int gdt_cnt;
|
||||
extern gdt_statist_t gdt_stat;
|
||||
|
||||
/*
|
||||
* Given a controller number,
|
||||
* make a special device and return the dev_t
|
||||
*/
|
||||
struct cdev *
|
||||
gdt_make_dev(struct gdt_softc *gdt)
|
||||
{
|
||||
struct cdev *dev;
|
||||
|
||||
#ifdef SDEV_PER_HBA
|
||||
dev = make_dev(&iir_cdevsw, 0, UID_ROOT, GID_OPERATOR,
|
||||
S_IRUSR | S_IWUSR, "iir%d", unit);
|
||||
dev->si_drv1 = gdt;
|
||||
#else
|
||||
sx_xlock(&sdev_lock);
|
||||
if (sdev_made)
|
||||
return (NULL);
|
||||
dev = make_dev(&iir_cdevsw, 0, UID_ROOT, GID_OPERATOR,
|
||||
S_IRUSR | S_IWUSR, "iir");
|
||||
sdev_made = 1;
|
||||
sx_xunlock(&sdev_lock);
|
||||
#endif
|
||||
return (dev);
|
||||
}
|
||||
|
||||
void
|
||||
gdt_destroy_dev(struct cdev *dev)
|
||||
{
|
||||
if (dev != NULL)
|
||||
destroy_dev(dev);
|
||||
}
|
||||
|
||||
/*
|
||||
* Given a minor device number,
|
||||
* return the pointer to its softc structure
|
||||
*/
|
||||
static struct gdt_softc *
|
||||
gdt_minor2softc(struct cdev *dev, int minor_no)
|
||||
{
|
||||
#ifdef SDEV_PER_HBA
|
||||
|
||||
return (dev->si_drv1);
|
||||
#else
|
||||
devclass_t dc;
|
||||
device_t child;
|
||||
|
||||
dc = devclass_find("iir");
|
||||
if (dc == NULL)
|
||||
return (NULL);
|
||||
child = devclass_get_device(dc, minor_no);
|
||||
if (child == NULL)
|
||||
return (NULL);
|
||||
return (device_get_softc(child));
|
||||
#endif
|
||||
}
|
||||
|
||||
static int
|
||||
iir_open(struct cdev *dev, int flags, int fmt, struct thread * p)
|
||||
{
|
||||
GDT_DPRINTF(GDT_D_DEBUG, ("iir_open()\n"));
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
iir_close(struct cdev *dev, int flags, int fmt, struct thread * p)
|
||||
{
|
||||
GDT_DPRINTF(GDT_D_DEBUG, ("iir_close()\n"));
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
iir_write(struct cdev *dev, struct uio * uio, int ioflag)
|
||||
{
|
||||
GDT_DPRINTF(GDT_D_DEBUG, ("iir_write()\n"));
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
iir_read(struct cdev *dev, struct uio * uio, int ioflag)
|
||||
{
|
||||
GDT_DPRINTF(GDT_D_DEBUG, ("iir_read()\n"));
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/**
|
||||
* This is the control syscall interface.
|
||||
* It should be binary compatible with UnixWare,
|
||||
* if not totally syntatically so.
|
||||
*/
|
||||
|
||||
static int
|
||||
iir_ioctl(struct cdev *dev, u_long cmd, caddr_t cmdarg, int flags, struct thread * p)
|
||||
{
|
||||
GDT_DPRINTF(GDT_D_DEBUG, ("iir_ioctl() cmd 0x%lx\n",cmd));
|
||||
|
||||
++gdt_stat.io_count_act;
|
||||
if (gdt_stat.io_count_act > gdt_stat.io_count_max)
|
||||
gdt_stat.io_count_max = gdt_stat.io_count_act;
|
||||
|
||||
switch (cmd) {
|
||||
case GDT_IOCTL_GENERAL:
|
||||
{
|
||||
gdt_ucmd_t *ucmd;
|
||||
struct gdt_softc *gdt;
|
||||
|
||||
ucmd = (gdt_ucmd_t *)cmdarg;
|
||||
gdt = gdt_minor2softc(dev, ucmd->io_node);
|
||||
if (gdt == NULL)
|
||||
return (ENXIO);
|
||||
mtx_lock(&gdt->sc_lock);
|
||||
TAILQ_INSERT_TAIL(&gdt->sc_ucmd_queue, ucmd, links);
|
||||
ucmd->complete_flag = FALSE;
|
||||
gdt_next(gdt);
|
||||
if (!ucmd->complete_flag)
|
||||
(void) mtx_sleep(ucmd, &gdt->sc_lock, PCATCH | PRIBIO, "iirucw",
|
||||
0);
|
||||
mtx_unlock(&gdt->sc_lock);
|
||||
break;
|
||||
}
|
||||
|
||||
case GDT_IOCTL_DRVERS:
|
||||
case GDT_IOCTL_DRVERS_OLD:
|
||||
*(int *)cmdarg =
|
||||
(IIR_DRIVER_VERSION << 8) | IIR_DRIVER_SUBVERSION;
|
||||
break;
|
||||
|
||||
case GDT_IOCTL_CTRTYPE:
|
||||
case GDT_IOCTL_CTRTYPE_OLD:
|
||||
{
|
||||
gdt_ctrt_t *p;
|
||||
struct gdt_softc *gdt;
|
||||
|
||||
p = (gdt_ctrt_t *)cmdarg;
|
||||
gdt = gdt_minor2softc(dev, p->io_node);
|
||||
if (gdt == NULL)
|
||||
return (ENXIO);
|
||||
/* only RP controllers */
|
||||
p->ext_type = 0x6000 | gdt->sc_device;
|
||||
if (gdt->sc_vendor == INTEL_VENDOR_ID_IIR) {
|
||||
p->oem_id = OEM_ID_INTEL;
|
||||
p->type = 0xfd;
|
||||
/* new -> subdevice into ext_type */
|
||||
if (gdt->sc_device >= 0x600)
|
||||
p->ext_type = 0x6000 | gdt->sc_subdevice;
|
||||
} else {
|
||||
p->oem_id = OEM_ID_ICP;
|
||||
p->type = 0xfe;
|
||||
/* new -> subdevice into ext_type */
|
||||
if (gdt->sc_device >= 0x300)
|
||||
p->ext_type = 0x6000 | gdt->sc_subdevice;
|
||||
}
|
||||
p->info = (gdt->sc_bus << 8) | (gdt->sc_slot << 3);
|
||||
p->device_id = gdt->sc_device;
|
||||
p->sub_device_id = gdt->sc_subdevice;
|
||||
break;
|
||||
}
|
||||
|
||||
case GDT_IOCTL_OSVERS:
|
||||
{
|
||||
gdt_osv_t *p;
|
||||
|
||||
p = (gdt_osv_t *)cmdarg;
|
||||
p->oscode = 10;
|
||||
p->version = osreldate / 100000;
|
||||
p->subversion = osreldate / 1000 % 100;
|
||||
p->revision = 0;
|
||||
strcpy(p->name, ostype);
|
||||
break;
|
||||
}
|
||||
|
||||
case GDT_IOCTL_CTRCNT:
|
||||
*(int *)cmdarg = gdt_cnt;
|
||||
break;
|
||||
|
||||
case GDT_IOCTL_EVENT:
|
||||
{
|
||||
gdt_event_t *p;
|
||||
|
||||
p = (gdt_event_t *)cmdarg;
|
||||
if (p->erase == 0xff) {
|
||||
if (p->dvr.event_source == GDT_ES_TEST)
|
||||
p->dvr.event_data.size = sizeof(p->dvr.event_data.eu.test);
|
||||
else if (p->dvr.event_source == GDT_ES_DRIVER)
|
||||
p->dvr.event_data.size= sizeof(p->dvr.event_data.eu.driver);
|
||||
else if (p->dvr.event_source == GDT_ES_SYNC)
|
||||
p->dvr.event_data.size = sizeof(p->dvr.event_data.eu.sync);
|
||||
else
|
||||
p->dvr.event_data.size = sizeof(p->dvr.event_data.eu.async);
|
||||
gdt_store_event(p->dvr.event_source, p->dvr.event_idx,
|
||||
&p->dvr.event_data);
|
||||
} else if (p->erase == 0xfe) {
|
||||
gdt_clear_events();
|
||||
} else if (p->erase == 0) {
|
||||
p->handle = gdt_read_event(p->handle, &p->dvr);
|
||||
} else {
|
||||
gdt_readapp_event((u_int8_t)p->erase, &p->dvr);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case GDT_IOCTL_STATIST:
|
||||
{
|
||||
gdt_statist_t *p;
|
||||
|
||||
p = (gdt_statist_t *)cmdarg;
|
||||
bcopy(&gdt_stat, p, sizeof(gdt_statist_t));
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
--gdt_stat.io_count_act;
|
||||
return (0);
|
||||
}
|
||||
@ -1,460 +0,0 @@
|
||||
/*-
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Copyright (c) 2000-03 ICP vortex GmbH
|
||||
* Copyright (c) 2002-03 Intel Corporation
|
||||
* Copyright (c) 2003 Adaptec Inc.
|
||||
* All Rights Reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions, and the following disclaimer,
|
||||
* without modification, immediately at the beginning of the file.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
/*
|
||||
* iir_pci.c: PCI Bus Attachment for Intel Integrated RAID Controller driver
|
||||
*
|
||||
* Written by: Achim Leubner <achim.leubner@intel.com>
|
||||
* Written by: Achim Leubner <achim_leubner@adaptec.com>
|
||||
* Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com>
|
||||
*
|
||||
* TODO:
|
||||
*/
|
||||
|
||||
/* #include "opt_iir.h" */
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/endian.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/lock.h>
|
||||
#include <sys/mutex.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/bus.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
#include <machine/resource.h>
|
||||
#include <sys/rman.h>
|
||||
|
||||
#include <dev/pci/pcireg.h>
|
||||
#include <dev/pci/pcivar.h>
|
||||
|
||||
#include <cam/scsi/scsi_all.h>
|
||||
|
||||
#include <dev/iir/iir.h>
|
||||
|
||||
/* Mapping registers for various areas */
|
||||
#define PCI_DPMEM PCIR_BAR(0)
|
||||
|
||||
/* Product numbers for Fibre-Channel are greater than or equal to 0x200 */
|
||||
#define GDT_PCI_PRODUCT_FC 0x200
|
||||
|
||||
/* PCI SRAM structure */
|
||||
#define GDT_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */
|
||||
#define GDT_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */
|
||||
#define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */
|
||||
#define GDT_OS_USED 0x10 /* u_int8_t [16], OS code per service */
|
||||
#define GDT_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */
|
||||
#define GDT_SRAM_SZ 0x40
|
||||
|
||||
/* DPRAM PCI controllers */
|
||||
#define GDT_DPR_IF 0x00 /* interface area */
|
||||
#define GDT_6SR (0xff0 - GDT_SRAM_SZ)
|
||||
#define GDT_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */
|
||||
#define GDT_IRQEN 0xff5 /* u_int8_t, board interrupts enable */
|
||||
#define GDT_EVENT 0xff8 /* u_int8_t, release event */
|
||||
#define GDT_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */
|
||||
#define GDT_DPRAM_SZ 0x1000
|
||||
|
||||
/* PLX register structure (new PCI controllers) */
|
||||
#define GDT_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */
|
||||
#define GDT_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */
|
||||
#define GDT_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */
|
||||
#define GDT_PLX_STATUS 0x44 /* volatile u_int16_t, command status */
|
||||
#define GDT_PLX_SERVICE 0x46 /* u_int16_t, service */
|
||||
#define GDT_PLX_INFO 0x48 /* u_int32_t [2], additional info */
|
||||
#define GDT_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */
|
||||
#define GDT_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */
|
||||
#define GDT_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */
|
||||
#define GDT_CONTROL1 0x69 /* u_int8_t, board interrupts enable */
|
||||
#define GDT_PLX_SZ 0x80
|
||||
|
||||
/* DPRAM new PCI controllers */
|
||||
#define GDT_IC 0x00 /* interface */
|
||||
#define GDT_PCINEW_6SR (0x4000 - GDT_SRAM_SZ)
|
||||
/* SRAM structure */
|
||||
#define GDT_PCINEW_SZ 0x4000
|
||||
|
||||
/* i960 register structure (PCI MPR controllers) */
|
||||
#define GDT_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */
|
||||
#define GDT_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */
|
||||
#define GDT_MPR_STATUS 0x14 /* volatile u_int16_t, command status */
|
||||
#define GDT_MPR_SERVICE 0x16 /* u_int16_t, service */
|
||||
#define GDT_MPR_INFO 0x18 /* u_int32_t [2], additional info */
|
||||
#define GDT_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */
|
||||
#define GDT_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */
|
||||
#define GDT_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */
|
||||
#define GDT_SEVERITY 0xefc /* u_int8_t, event severity */
|
||||
#define GDT_EVT_BUF 0xf00 /* u_int8_t [256], event buffer */
|
||||
#define GDT_I960_SZ 0x1000
|
||||
|
||||
/* DPRAM PCI MPR controllers */
|
||||
#define GDT_I960R 0x00 /* 4KB i960 registers */
|
||||
#define GDT_MPR_IC GDT_I960_SZ
|
||||
/* i960 register area */
|
||||
#define GDT_MPR_6SR (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ)
|
||||
/* DPRAM struct. */
|
||||
#define GDT_MPR_SZ (0x3000 - GDT_SRAM_SZ)
|
||||
|
||||
static int iir_pci_probe(device_t dev);
|
||||
static int iir_pci_attach(device_t dev);
|
||||
|
||||
void gdt_pci_enable_intr(struct gdt_softc *);
|
||||
|
||||
void gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *);
|
||||
u_int8_t gdt_mpr_get_status(struct gdt_softc *);
|
||||
void gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *);
|
||||
void gdt_mpr_release_event(struct gdt_softc *);
|
||||
void gdt_mpr_set_sema0(struct gdt_softc *);
|
||||
int gdt_mpr_test_busy(struct gdt_softc *);
|
||||
|
||||
static device_method_t iir_pci_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, iir_pci_probe),
|
||||
DEVMETHOD(device_attach, iir_pci_attach),
|
||||
{ 0, 0}
|
||||
};
|
||||
|
||||
|
||||
static driver_t iir_pci_driver =
|
||||
{
|
||||
"iir",
|
||||
iir_pci_methods,
|
||||
sizeof(struct gdt_softc)
|
||||
};
|
||||
|
||||
static devclass_t iir_devclass;
|
||||
|
||||
DRIVER_MODULE(iir, pci, iir_pci_driver, iir_devclass, 0, 0);
|
||||
MODULE_DEPEND(iir, pci, 1, 1, 1);
|
||||
MODULE_DEPEND(iir, cam, 1, 1, 1);
|
||||
|
||||
static int
|
||||
iir_pci_probe(device_t dev)
|
||||
{
|
||||
if (pci_get_vendor(dev) == INTEL_VENDOR_ID_IIR &&
|
||||
pci_get_device(dev) == INTEL_DEVICE_ID_IIR) {
|
||||
device_set_desc(dev, "Intel Integrated RAID Controller");
|
||||
return (BUS_PROBE_DEFAULT);
|
||||
}
|
||||
if (pci_get_vendor(dev) == GDT_VENDOR_ID &&
|
||||
((pci_get_device(dev) >= GDT_DEVICE_ID_MIN &&
|
||||
pci_get_device(dev) <= GDT_DEVICE_ID_MAX) ||
|
||||
pci_get_device(dev) == GDT_DEVICE_ID_NEWRX)) {
|
||||
device_set_desc(dev, "ICP Disk Array Controller");
|
||||
return (BUS_PROBE_DEFAULT);
|
||||
}
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
|
||||
static int
|
||||
iir_pci_attach(device_t dev)
|
||||
{
|
||||
struct gdt_softc *gdt;
|
||||
struct resource *irq = NULL;
|
||||
int retries, rid, error = 0;
|
||||
void *ih;
|
||||
u_int8_t protocol;
|
||||
|
||||
gdt = device_get_softc(dev);
|
||||
mtx_init(&gdt->sc_lock, "iir", NULL, MTX_DEF);
|
||||
|
||||
/* map DPMEM */
|
||||
rid = PCI_DPMEM;
|
||||
gdt->sc_dpmem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
|
||||
if (gdt->sc_dpmem == NULL) {
|
||||
device_printf(dev, "can't allocate register resources\n");
|
||||
error = ENOMEM;
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* get IRQ */
|
||||
rid = 0;
|
||||
irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
|
||||
RF_ACTIVE | RF_SHAREABLE);
|
||||
if (irq == NULL) {
|
||||
device_printf(dev, "can't find IRQ value\n");
|
||||
error = ENOMEM;
|
||||
goto err;
|
||||
}
|
||||
|
||||
gdt->sc_devnode = dev;
|
||||
gdt->sc_init_level = 0;
|
||||
gdt->sc_hanum = device_get_unit(dev);
|
||||
gdt->sc_bus = pci_get_bus(dev);
|
||||
gdt->sc_slot = pci_get_slot(dev);
|
||||
gdt->sc_vendor = pci_get_vendor(dev);
|
||||
gdt->sc_device = pci_get_device(dev);
|
||||
gdt->sc_subdevice = pci_get_subdevice(dev);
|
||||
gdt->sc_class = GDT_MPR;
|
||||
/* no FC ctr.
|
||||
if (gdt->sc_device >= GDT_PCI_PRODUCT_FC)
|
||||
gdt->sc_class |= GDT_FC;
|
||||
*/
|
||||
|
||||
/* initialize RP controller */
|
||||
/* check and reset interface area */
|
||||
bus_write_4(gdt->sc_dpmem, GDT_MPR_IC, htole32(GDT_MPR_MAGIC));
|
||||
if (bus_read_4(gdt->sc_dpmem, GDT_MPR_IC) != htole32(GDT_MPR_MAGIC)) {
|
||||
device_printf(dev, "cannot access DPMEM at 0x%jx (shadowed?)\n",
|
||||
rman_get_start(gdt->sc_dpmem));
|
||||
error = ENXIO;
|
||||
goto err;
|
||||
}
|
||||
bus_set_region_4(gdt->sc_dpmem, GDT_I960_SZ, htole32(0), GDT_MPR_SZ >> 2);
|
||||
|
||||
/* Disable everything */
|
||||
bus_write_1(gdt->sc_dpmem, GDT_EDOOR_EN,
|
||||
bus_read_1(gdt->sc_dpmem, GDT_EDOOR_EN) | 4);
|
||||
bus_write_1(gdt->sc_dpmem, GDT_MPR_EDOOR, 0xff);
|
||||
bus_write_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_STATUS, 0);
|
||||
bus_write_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_CMD_INDEX, 0);
|
||||
|
||||
bus_write_4(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_INFO,
|
||||
htole32(rman_get_start(gdt->sc_dpmem)));
|
||||
bus_write_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_CMD_INDX, 0xff);
|
||||
bus_write_1(gdt->sc_dpmem, GDT_MPR_LDOOR, 1);
|
||||
|
||||
DELAY(20);
|
||||
retries = GDT_RETRIES;
|
||||
while (bus_read_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_STATUS) != 0xff) {
|
||||
if (--retries == 0) {
|
||||
device_printf(dev, "DEINIT failed\n");
|
||||
error = ENXIO;
|
||||
goto err;
|
||||
}
|
||||
DELAY(1);
|
||||
}
|
||||
|
||||
protocol = (uint8_t)le32toh(bus_read_4(gdt->sc_dpmem,
|
||||
GDT_MPR_IC + GDT_S_INFO));
|
||||
bus_write_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_STATUS, 0);
|
||||
if (protocol != GDT_PROTOCOL_VERSION) {
|
||||
device_printf(dev, "unsupported protocol %d\n", protocol);
|
||||
error = ENXIO;
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* special command to controller BIOS */
|
||||
bus_write_4(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_INFO, htole32(0));
|
||||
bus_write_4(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t),
|
||||
htole32(0));
|
||||
bus_write_4(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t),
|
||||
htole32(1));
|
||||
bus_write_4(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t),
|
||||
htole32(0));
|
||||
bus_write_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_CMD_INDX, 0xfe);
|
||||
bus_write_1(gdt->sc_dpmem, GDT_MPR_LDOOR, 1);
|
||||
|
||||
DELAY(20);
|
||||
retries = GDT_RETRIES;
|
||||
while (bus_read_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_STATUS) != 0xfe) {
|
||||
if (--retries == 0) {
|
||||
device_printf(dev, "initialization error\n");
|
||||
error = ENXIO;
|
||||
goto err;
|
||||
}
|
||||
DELAY(1);
|
||||
}
|
||||
|
||||
bus_write_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_STATUS, 0);
|
||||
|
||||
gdt->sc_ic_all_size = GDT_MPR_SZ;
|
||||
|
||||
gdt->sc_copy_cmd = gdt_mpr_copy_cmd;
|
||||
gdt->sc_get_status = gdt_mpr_get_status;
|
||||
gdt->sc_intr = gdt_mpr_intr;
|
||||
gdt->sc_release_event = gdt_mpr_release_event;
|
||||
gdt->sc_set_sema0 = gdt_mpr_set_sema0;
|
||||
gdt->sc_test_busy = gdt_mpr_test_busy;
|
||||
|
||||
/* Allocate a dmatag representing the capabilities of this attachment */
|
||||
if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev),
|
||||
/*alignemnt*/1, /*boundary*/0,
|
||||
/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
|
||||
/*highaddr*/BUS_SPACE_MAXADDR,
|
||||
/*filter*/NULL, /*filterarg*/NULL,
|
||||
/*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
|
||||
/*nsegments*/BUS_SPACE_UNRESTRICTED,
|
||||
/*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
|
||||
/*flags*/0, /*lockfunc*/busdma_lock_mutex,
|
||||
/*lockarg*/&gdt->sc_lock, &gdt->sc_parent_dmat) != 0) {
|
||||
error = ENXIO;
|
||||
goto err;
|
||||
}
|
||||
gdt->sc_init_level++;
|
||||
|
||||
if (iir_init(gdt) != 0) {
|
||||
iir_free(gdt);
|
||||
error = ENXIO;
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* Register with the XPT */
|
||||
iir_attach(gdt);
|
||||
|
||||
/* associate interrupt handler */
|
||||
if (bus_setup_intr(dev, irq, INTR_TYPE_CAM | INTR_MPSAFE,
|
||||
NULL, iir_intr, gdt, &ih )) {
|
||||
device_printf(dev, "Unable to register interrupt handler\n");
|
||||
error = ENXIO;
|
||||
goto err;
|
||||
}
|
||||
|
||||
gdt_pci_enable_intr(gdt);
|
||||
gone_in_dev(dev, 13, "iir(4) removed");
|
||||
return (0);
|
||||
|
||||
err:
|
||||
if (irq)
|
||||
bus_release_resource( dev, SYS_RES_IRQ, 0, irq );
|
||||
|
||||
if (gdt->sc_dpmem)
|
||||
bus_release_resource( dev, SYS_RES_MEMORY, rid, gdt->sc_dpmem );
|
||||
mtx_destroy(&gdt->sc_lock);
|
||||
|
||||
return (error);
|
||||
}
|
||||
|
||||
|
||||
/* Enable interrupts */
|
||||
void
|
||||
gdt_pci_enable_intr(struct gdt_softc *gdt)
|
||||
{
|
||||
GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", gdt));
|
||||
|
||||
switch(GDT_CLASS(gdt)) {
|
||||
case GDT_MPR:
|
||||
bus_write_1(gdt->sc_dpmem, GDT_MPR_EDOOR, 0xff);
|
||||
bus_write_1(gdt->sc_dpmem, GDT_EDOOR_EN,
|
||||
bus_read_1(gdt->sc_dpmem, GDT_EDOOR_EN) & ~4);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* MPR PCI controller-specific functions
|
||||
*/
|
||||
|
||||
void
|
||||
gdt_mpr_copy_cmd(struct gdt_softc *gdt, struct gdt_ccb *gccb)
|
||||
{
|
||||
u_int16_t cp_count = roundup(gccb->gc_cmd_len, sizeof (u_int32_t));
|
||||
u_int16_t dp_offset = gdt->sc_cmd_off;
|
||||
u_int16_t cmd_no = gdt->sc_cmd_cnt++;
|
||||
|
||||
GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", gdt));
|
||||
|
||||
gdt->sc_cmd_off += cp_count;
|
||||
|
||||
bus_write_region_4(gdt->sc_dpmem, GDT_MPR_IC + GDT_DPR_CMD + dp_offset,
|
||||
(u_int32_t *)gccb->gc_cmd, cp_count >> 2);
|
||||
bus_write_2(gdt->sc_dpmem,
|
||||
GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET,
|
||||
htole16(GDT_DPMEM_COMMAND_OFFSET + dp_offset));
|
||||
bus_write_2(gdt->sc_dpmem,
|
||||
GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID,
|
||||
htole16(gccb->gc_service));
|
||||
}
|
||||
|
||||
u_int8_t
|
||||
gdt_mpr_get_status(struct gdt_softc *gdt)
|
||||
{
|
||||
GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", gdt));
|
||||
|
||||
return bus_read_1(gdt->sc_dpmem, GDT_MPR_EDOOR);
|
||||
}
|
||||
|
||||
void
|
||||
gdt_mpr_intr(struct gdt_softc *gdt, struct gdt_intr_ctx *ctx)
|
||||
{
|
||||
int i;
|
||||
|
||||
GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", gdt));
|
||||
|
||||
bus_write_1(gdt->sc_dpmem, GDT_MPR_EDOOR, 0xff);
|
||||
|
||||
if (ctx->istatus & 0x80) { /* error flag */
|
||||
ctx->istatus &= ~0x80;
|
||||
ctx->cmd_status = bus_read_2(gdt->sc_dpmem, GDT_MPR_STATUS);
|
||||
} else /* no error */
|
||||
ctx->cmd_status = GDT_S_OK;
|
||||
|
||||
ctx->info = bus_read_4(gdt->sc_dpmem, GDT_MPR_INFO);
|
||||
ctx->service = bus_read_2(gdt->sc_dpmem, GDT_MPR_SERVICE);
|
||||
ctx->info2 = bus_read_4(gdt->sc_dpmem, GDT_MPR_INFO + sizeof (u_int32_t));
|
||||
|
||||
/* event string */
|
||||
if (ctx->istatus == GDT_ASYNCINDEX) {
|
||||
if (ctx->service != GDT_SCREENSERVICE &&
|
||||
(gdt->sc_fw_vers & 0xff) >= 0x1a) {
|
||||
gdt->sc_dvr.severity = bus_read_1(gdt->sc_dpmem, GDT_SEVERITY);
|
||||
for (i = 0; i < 256; ++i) {
|
||||
gdt->sc_dvr.event_string[i] = bus_read_1(gdt->sc_dpmem,
|
||||
GDT_EVT_BUF + i);
|
||||
if (gdt->sc_dvr.event_string[i] == 0)
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
bus_write_1(gdt->sc_dpmem, GDT_MPR_SEMA1, 0);
|
||||
}
|
||||
|
||||
void
|
||||
gdt_mpr_release_event(struct gdt_softc *gdt)
|
||||
{
|
||||
GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", gdt));
|
||||
|
||||
bus_write_1(gdt->sc_dpmem, GDT_MPR_LDOOR, 1);
|
||||
}
|
||||
|
||||
void
|
||||
gdt_mpr_set_sema0(struct gdt_softc *gdt)
|
||||
{
|
||||
GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", gdt));
|
||||
|
||||
bus_write_1(gdt->sc_dpmem, GDT_MPR_SEMA0, 1);
|
||||
}
|
||||
|
||||
int
|
||||
gdt_mpr_test_busy(struct gdt_softc *gdt)
|
||||
{
|
||||
GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", gdt));
|
||||
|
||||
return (bus_read_1(gdt->sc_dpmem, GDT_MPR_SEMA0) & 1);
|
||||
}
|
||||
@ -157,7 +157,6 @@ device ses # Enclosure Services (SES and SAF-TE)
|
||||
device amr # AMI MegaRAID
|
||||
device arcmsr # Areca SATA II RAID
|
||||
device ciss # Compaq Smart RAID 5*
|
||||
device iir # Intel Integrated RAID
|
||||
device ips # IBM (Adaptec) ServeRAID
|
||||
device twa # 3ware 9000 series PATA/SATA RAID
|
||||
device tws # LSI 3ware 9750 SATA+SAS 6Gb/s RAID controller
|
||||
|
||||
@ -165,7 +165,6 @@ SUBDIR= \
|
||||
if_vxlan \
|
||||
iflib \
|
||||
${_igc} \
|
||||
${_iir} \
|
||||
imgact_binmisc \
|
||||
${_intelspi} \
|
||||
${_io} \
|
||||
@ -695,7 +694,6 @@ _hptrr= hptrr
|
||||
_hyperv= hyperv
|
||||
_ichwd= ichwd
|
||||
_ida= ida
|
||||
_iir= iir
|
||||
_intelspi= intelspi
|
||||
_ips= ips
|
||||
_isci= isci
|
||||
|
||||
@ -1,9 +0,0 @@
|
||||
# $FreeBSD$
|
||||
|
||||
KMOD = iir
|
||||
.PATH: ${SRCTOP}/sys/dev/${KMOD}
|
||||
SRCS = iir.c iir_ctrl.c iir_pci.c
|
||||
SRCS += opt_scsi.h opt_cam.h
|
||||
SRCS += device_if.h bus_if.h pci_if.h
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
@ -1,21 +0,0 @@
|
||||
# Doxyfile 1.5.2
|
||||
|
||||
# $FreeBSD$
|
||||
|
||||
#---------------------------------------------------------------------------
|
||||
# Project related configuration options
|
||||
#---------------------------------------------------------------------------
|
||||
PROJECT_NAME = "FreeBSD kernel IIR device code"
|
||||
OUTPUT_DIRECTORY = $(DOXYGEN_DEST_PATH)/dev_iir/
|
||||
EXTRACT_ALL = YES # for undocumented src, no warnings enabled
|
||||
#---------------------------------------------------------------------------
|
||||
# configuration options related to the input files
|
||||
#---------------------------------------------------------------------------
|
||||
INPUT = $(DOXYGEN_SRC_PATH)/dev/iir/ \
|
||||
$(NOTREVIEWED)
|
||||
|
||||
GENERATE_TAGFILE = dev_iir/dev_iir.tag
|
||||
|
||||
@INCLUDE_PATH = $(DOXYGEN_INCLUDE_PATH)
|
||||
@INCLUDE = common-Doxyfile
|
||||
|
||||
Loading…
Reference in New Issue
Block a user