Do a sweep of the tree replacing calls to pci_find_extcap() with calls to
pci_find_cap() instead.
This commit is contained in:
parent
7ee26a530a
commit
3b0a4aef96
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=219902
@ -341,7 +341,7 @@ ae_attach(device_t dev)
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ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
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IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
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IFQ_SET_READY(&ifp->if_snd);
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if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
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if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
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ifp->if_capabilities |= IFCAP_WOL_MAGIC;
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sc->flags |= AE_FLAG_PMG;
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}
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@ -929,7 +929,7 @@ ae_check_eeprom_present(ae_softc_t *sc, int *vpdc)
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val &= ~AE_SPICTL_VPD_EN;
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AE_WRITE_4(sc, AE_SPICTL_REG, val);
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}
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error = pci_find_extcap(sc->dev, PCIY_VPD, vpdc);
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error = pci_find_cap(sc->dev, PCIY_VPD, vpdc);
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return (error);
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}
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@ -1383,7 +1383,7 @@ ae_pm_init(ae_softc_t *sc)
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/*
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* Configure PME.
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*/
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pci_find_extcap(sc->dev, PCIY_PMG, &pmc);
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pci_find_cap(sc->dev, PCIY_PMG, &pmc);
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pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
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pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
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if ((ifp->if_capenable & IFCAP_WOL) != 0)
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@ -346,7 +346,7 @@ age_get_macaddr(struct age_softc *sc)
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CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);
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}
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if (pci_find_extcap(sc->age_dev, PCIY_VPD, &vpdc) == 0) {
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if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) {
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/*
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* PCI VPD capability found, let TWSI reload EEPROM.
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* This will set ethernet address of controller.
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@ -563,7 +563,7 @@ age_attach(device_t dev)
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/* Get DMA parameters from PCIe device control register. */
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if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) {
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if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
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sc->age_flags |= AGE_FLAG_PCIE;
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burst = pci_read_config(dev, i + 0x08, 2);
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/* Max read request size. */
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@ -610,7 +610,7 @@ age_attach(device_t dev)
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IFQ_SET_READY(&ifp->if_snd);
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ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
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ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO;
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if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
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if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
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sc->age_flags |= AGE_FLAG_PMCAP;
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ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
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}
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@ -1329,7 +1329,7 @@ age_setwol(struct age_softc *sc)
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AGE_LOCK_ASSERT(sc);
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if (pci_find_extcap(sc->age_dev, PCIY_PMG, &pmc) != 0) {
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if (pci_find_cap(sc->age_dev, PCIY_PMG, &pmc) != 0) {
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CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
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/*
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* No PME capability, PHY power down.
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@ -98,7 +98,7 @@ agp_find_caps(device_t dev)
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int capreg;
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if (pci_find_extcap(dev, PCIY_AGP, &capreg) != 0)
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if (pci_find_cap(dev, PCIY_AGP, &capreg) != 0)
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capreg = 0;
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return (capreg);
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}
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@ -353,7 +353,7 @@ ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry)
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* Find the PCI-X cap pointer. If we don't find it,
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* pcix_ptr will be 0.
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*/
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pci_find_extcap(ahd->dev_softc, PCIY_PCIX, &ahd->pcix_ptr);
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pci_find_cap(ahd->dev_softc, PCIY_PCIX, &ahd->pcix_ptr);
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devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
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if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
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ahd->chip |= AHD_PCI;
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@ -783,7 +783,7 @@ alc_attach(device_t dev)
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sc->alc_dma_rd_burst = 0;
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sc->alc_dma_wr_burst = 0;
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sc->alc_rcb = DMA_CFG_RCB_64;
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if (pci_find_extcap(dev, PCIY_EXPRESS, &base) == 0) {
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if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) {
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sc->alc_flags |= ALC_FLAG_PCIE;
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sc->alc_expcap = base;
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burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL);
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@ -963,7 +963,7 @@ alc_attach(device_t dev)
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IFQ_SET_READY(&ifp->if_snd);
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ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4;
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ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO;
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if (pci_find_extcap(dev, PCIY_PMG, &base) == 0) {
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if (pci_find_cap(dev, PCIY_PMG, &base) == 0) {
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ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
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sc->alc_flags |= ALC_FLAG_PM;
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sc->alc_pmcap = base;
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@ -330,7 +330,7 @@ ale_get_macaddr(struct ale_softc *sc)
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CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
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}
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if (pci_find_extcap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) {
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if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) {
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/*
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* PCI VPD capability found, let TWSI reload EEPROM.
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* This will set ethernet address of controller.
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@ -544,7 +544,7 @@ ale_attach(device_t dev)
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}
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/* Get DMA parameters from PCIe device control register. */
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if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) {
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if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
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sc->ale_flags |= ALE_FLAG_PCIE;
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burst = pci_read_config(dev, i + 0x08, 2);
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/* Max read request size. */
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@ -591,7 +591,7 @@ ale_attach(device_t dev)
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IFQ_SET_READY(&ifp->if_snd);
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ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4;
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ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO;
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if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
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if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
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sc->ale_flags |= ALE_FLAG_PMCAP;
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ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
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}
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@ -1469,7 +1469,7 @@ ale_setwol(struct ale_softc *sc)
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ALE_LOCK_ASSERT(sc);
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if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) != 0) {
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if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) {
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/* Disable WOL. */
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CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
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reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
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@ -1548,7 +1548,7 @@ ale_resume(device_t dev)
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sc = device_get_softc(dev);
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ALE_LOCK(sc);
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if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) == 0) {
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if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) {
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/* Disable PME and clear PME status. */
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pmstat = pci_read_config(sc->ale_dev,
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pmc + PCIR_POWER_STATUS, 2);
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@ -801,13 +801,13 @@ bce_probe_pci_caps(device_t dev, struct bce_softc *sc)
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DBENTER(BCE_VERBOSE_LOAD);
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/* Check if PCI-X capability is enabled. */
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if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) {
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if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) {
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if (reg != 0)
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sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
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}
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/* Check if PCIe capability is enabled. */
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if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
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if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
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if (reg != 0) {
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u16 link_status = pci_read_config(dev, reg + 0x12, 2);
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DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = "
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@ -820,13 +820,13 @@ bce_probe_pci_caps(device_t dev, struct bce_softc *sc)
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}
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/* Check if MSI capability is enabled. */
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if (pci_find_extcap(dev, PCIY_MSI, ®) == 0) {
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if (pci_find_cap(dev, PCIY_MSI, ®) == 0) {
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if (reg != 0)
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sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG;
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}
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/* Check if MSI-X capability is enabled. */
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if (pci_find_extcap(dev, PCIY_MSIX, ®) == 0) {
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if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) {
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if (reg != 0)
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sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG;
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}
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@ -2883,7 +2883,7 @@ bge_attach(device_t dev)
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/*
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* Check if this is a PCI-X or PCI Express device.
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*/
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if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
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if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
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/*
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* Found a PCI Express capabilities register, this
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* must be a PCI Express device.
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@ -2897,7 +2897,7 @@ bge_attach(device_t dev)
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* Check if the device is in PCI-X Mode.
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* (This bit is not valid on PCI Express controllers.)
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*/
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if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0)
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if (pci_find_cap(dev, PCIY_PCIX, ®) == 0)
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sc->bge_pcixcap = reg;
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if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
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BGE_PCISTATE_PCI_BUSMODE) == 0)
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@ -2917,7 +2917,7 @@ bge_attach(device_t dev)
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* normal operation.
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*/
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rid = 0;
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if (pci_find_extcap(sc->bge_dev, PCIY_MSI, ®) == 0) {
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if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) {
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sc->bge_msicap = reg;
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if (bge_can_use_msi(sc)) {
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msicount = pci_msi_count(dev);
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@ -979,7 +979,7 @@ bwn_attach(device_t dev)
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/*
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* setup PCI resources and interrupt.
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*/
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if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
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if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
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msic = pci_msi_count(dev);
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if (bootverbose)
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device_printf(sc->sc_dev, "MSI count : %d\n", msic);
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@ -1568,7 +1568,7 @@ bxe_probe_pci_caps(struct bxe_softc *sc)
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DBENTER(BXE_EXTREME_LOAD);
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/* Check if PCI Power Management capability is enabled. */
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if (pci_find_extcap(dev, PCIY_PMG, ®) == 0) {
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if (pci_find_cap(dev, PCIY_PMG, ®) == 0) {
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if (reg != 0) {
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DBPRINT(sc, BXE_EXTREME_LOAD,
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"%s(): Found PM capability at 0x%04X\n",
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@ -1578,7 +1578,7 @@ bxe_probe_pci_caps(struct bxe_softc *sc)
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}
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/* Check if PCIe capability is enabled. */
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if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
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if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
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if (reg != 0) {
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link_status = pci_read_config(dev, reg + 0x12, 2);
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@ -1612,7 +1612,7 @@ bxe_probe_pci_caps(struct bxe_softc *sc)
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/* Check if MSI capability is enabled. */
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if (pci_find_extcap(dev, PCIY_MSI, ®) == 0) {
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if (pci_find_cap(dev, PCIY_MSI, ®) == 0) {
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if (reg != 0) {
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DBPRINT(sc, BXE_EXTREME_LOAD,
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"%s(): Found MSI capability at 0x%04X\n",
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@ -1622,7 +1622,7 @@ bxe_probe_pci_caps(struct bxe_softc *sc)
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}
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/* Check if MSI-X capability is enabled. */
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if (pci_find_extcap(dev, PCIY_MSIX, ®) == 0) {
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if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) {
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if (reg != 0) {
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DBPRINT(sc, BXE_EXTREME_LOAD,
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"%s(): Found MSI-X capability at 0x%04X\n",
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@ -458,7 +458,7 @@ cxgb_controller_attach(device_t dev)
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ai = cxgb_get_adapter_info(dev);
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/* find the PCIe link width and set max read request to 4KB*/
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if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
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if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
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uint16_t lnk;
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lnk = pci_read_config(dev, reg + PCIR_EXPRESS_LINK_STA, 2);
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@ -51,7 +51,7 @@ drm_device_find_capability(struct drm_device *dev, int cap)
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{
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#if __FreeBSD_version >= 602102
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return (pci_find_extcap(dev->device, cap, NULL) == 0);
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return (pci_find_cap(dev->device, cap, NULL) == 0);
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#else
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/* Code taken from agp.c. IWBNI that was a public interface. */
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u_int32_t status;
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@ -75,7 +75,7 @@ e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
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device_t dev = ((struct e1000_osdep *)hw->back)->dev;
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u32 offset;
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pci_find_extcap(dev, PCIY_EXPRESS, &offset);
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pci_find_cap(dev, PCIY_EXPRESS, &offset);
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*value = pci_read_config(dev, offset + reg, 2);
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return (E1000_SUCCESS);
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}
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@ -89,7 +89,7 @@ e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
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device_t dev = ((struct e1000_osdep *)hw->back)->dev;
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u32 offset;
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pci_find_extcap(dev, PCIY_EXPRESS, &offset);
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pci_find_cap(dev, PCIY_EXPRESS, &offset);
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pci_write_config(dev, offset + reg, *value, 2);
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return (E1000_SUCCESS);
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}
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@ -4756,7 +4756,7 @@ em_enable_wakeup(device_t dev)
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u32 pmc, ctrl, ctrl_ext, rctl;
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u16 status;
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if ((pci_find_extcap(dev, PCIY_PMG, &pmc) != 0))
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if ((pci_find_cap(dev, PCIY_PMG, &pmc) != 0))
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return;
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/* Advertise the wakeup capability */
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@ -4924,7 +4924,7 @@ em_disable_aspm(struct adapter *adapter)
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default:
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return;
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}
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if (pci_find_extcap(dev, PCIY_EXPRESS, &base) != 0)
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if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
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return;
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reg = base + PCIR_EXPRESS_LINK_CAP;
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link_cap = pci_read_config(dev, reg, 2);
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@ -3939,7 +3939,7 @@ lem_enable_wakeup(device_t dev)
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u32 pmc, ctrl, ctrl_ext, rctl;
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u16 status;
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if ((pci_find_extcap(dev, PCIY_PMG, &pmc) != 0))
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if ((pci_find_cap(dev, PCIY_PMG, &pmc) != 0))
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return;
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/* Advertise the wakeup capability */
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@ -275,7 +275,7 @@ et_attach(device_t dev)
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}
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msic = 0;
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if (pci_find_extcap(dev, PCIY_EXPRESS, &cap) == 0) {
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if (pci_find_cap(dev, PCIY_EXPRESS, &cap) == 0) {
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sc->sc_expcap = cap;
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sc->sc_flags |= ET_FLAG_PCIE;
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msic = pci_msi_count(dev);
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@ -521,7 +521,7 @@ fxp_attach(device_t dev)
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sc->revision != FXP_REV_82559S_A) {
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fxp_read_eeprom(sc, &data, 10, 1);
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if ((data & 0x20) != 0 &&
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pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0)
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pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0)
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sc->flags |= FXP_FLAG_WOLCAP;
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}
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@ -1054,7 +1054,7 @@ fxp_suspend(device_t dev)
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FXP_LOCK(sc);
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ifp = sc->ifp;
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if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) {
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if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
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pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
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pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
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if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
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@ -1088,7 +1088,7 @@ fxp_resume(device_t dev)
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FXP_LOCK(sc);
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if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) {
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if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
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sc->flags &= ~FXP_FLAG_WOL;
|
||||
pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
|
||||
/* Disable PME and clear PME status. */
|
||||
|
@ -429,7 +429,7 @@ iwn_attach(device_t dev)
|
||||
* Get the offset of the PCI Express Capability Structure in PCI
|
||||
* Configuration Space.
|
||||
*/
|
||||
error = pci_find_extcap(dev, PCIY_EXPRESS, &sc->sc_cap_off);
|
||||
error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off);
|
||||
if (error != 0) {
|
||||
device_printf(dev, "PCIe capability structure not found!\n");
|
||||
return error;
|
||||
|
@ -1627,7 +1627,7 @@ ixv_allocate_msix(struct adapter *adapter)
|
||||
*/
|
||||
if (adapter->hw.mac.type == ixgbe_mac_82599_vf) {
|
||||
int msix_ctrl;
|
||||
pci_find_extcap(dev, PCIY_MSIX, &rid);
|
||||
pci_find_cap(dev, PCIY_MSIX, &rid);
|
||||
rid += PCIR_MSIX_CTRL;
|
||||
msix_ctrl = pci_read_config(dev, rid, 2);
|
||||
msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
|
||||
|
@ -778,7 +778,7 @@ jme_attach(device_t dev)
|
||||
sc->jme_phyaddr = 0;
|
||||
|
||||
/* Set max allowable DMA size. */
|
||||
if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) {
|
||||
if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
|
||||
sc->jme_flags |= JME_FLAG_PCIE;
|
||||
burst = pci_read_config(dev, i + PCIR_EXPRESS_DEVICE_CTL, 2);
|
||||
if (bootverbose) {
|
||||
@ -827,7 +827,7 @@ jme_attach(device_t dev)
|
||||
/* JMC250 supports Tx/Rx checksum offload as well as TSO. */
|
||||
ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
|
||||
ifp->if_hwassist = JME_CSUM_FEATURES | CSUM_TSO;
|
||||
if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
|
||||
if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
|
||||
sc->jme_flags |= JME_FLAG_PMCAP;
|
||||
ifp->if_capabilities |= IFCAP_WOL_MAGIC;
|
||||
}
|
||||
@ -1591,7 +1591,7 @@ jme_setwol(struct jme_softc *sc)
|
||||
|
||||
JME_LOCK_ASSERT(sc);
|
||||
|
||||
if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
|
||||
if (pci_find_cap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
|
||||
/* Remove Tx MAC/offload clock to save more power. */
|
||||
if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
|
||||
CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &
|
||||
@ -1663,7 +1663,7 @@ jme_resume(device_t dev)
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
JME_LOCK(sc);
|
||||
if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
|
||||
if (pci_find_cap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
|
||||
pmstat = pci_read_config(sc->jme_dev,
|
||||
pmc + PCIR_POWER_STATUS, 2);
|
||||
/* Disable PME clear PME status. */
|
||||
|
@ -175,7 +175,7 @@ malo_pci_attach(device_t dev)
|
||||
*/
|
||||
sc->malo_invalid = 1;
|
||||
|
||||
if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
|
||||
if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
|
||||
msic = pci_msi_count(dev);
|
||||
if (bootverbose)
|
||||
device_printf(dev, "MSI count : %d\n", msic);
|
||||
|
@ -1759,10 +1759,10 @@ mskc_attach(device_t dev)
|
||||
}
|
||||
|
||||
/* Check bus type. */
|
||||
if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) {
|
||||
if (pci_find_cap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) {
|
||||
sc->msk_bustype = MSK_PEX_BUS;
|
||||
sc->msk_expcap = reg;
|
||||
} else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0) {
|
||||
} else if (pci_find_cap(sc->msk_dev, PCIY_PCIX, ®) == 0) {
|
||||
sc->msk_bustype = MSK_PCIX_BUS;
|
||||
sc->msk_pcixcap = reg;
|
||||
} else
|
||||
|
@ -553,7 +553,7 @@ mxge_firmware_probe(mxge_softc_t *sc)
|
||||
* Verify the max read request size was set to 4KB
|
||||
* before trying the test with 4KB.
|
||||
*/
|
||||
if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
|
||||
if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
|
||||
pectl = pci_read_config(dev, reg + 0x8, 2);
|
||||
if ((pectl & (5 << 12)) != (5 << 12)) {
|
||||
device_printf(dev, "Max Read Req. size != 4k (0x%x\n",
|
||||
@ -3731,7 +3731,7 @@ mxge_setup_cfg_space(mxge_softc_t *sc)
|
||||
uint16_t cmd, lnk, pectl;
|
||||
|
||||
/* find the PCIe link width and set max read request to 4KB*/
|
||||
if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
|
||||
if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
|
||||
lnk = pci_read_config(dev, reg + 0x12, 2);
|
||||
sc->link_width = (lnk >> 4) & 0x3f;
|
||||
|
||||
@ -3760,7 +3760,7 @@ mxge_read_reboot(mxge_softc_t *sc)
|
||||
uint32_t vs;
|
||||
|
||||
/* find the vendor specific offset */
|
||||
if (pci_find_extcap(dev, PCIY_VENDOR, &vs) != 0) {
|
||||
if (pci_find_cap(dev, PCIY_VENDOR, &vs) != 0) {
|
||||
device_printf(sc->dev,
|
||||
"could not find vendor specific offset\n");
|
||||
return (uint32_t)-1;
|
||||
|
@ -363,7 +363,7 @@ nfe_attach(device_t dev)
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
|
||||
if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
|
||||
uint16_t v, width;
|
||||
|
||||
v = pci_read_config(dev, reg + 0x08, 2);
|
||||
@ -596,7 +596,7 @@ nfe_attach(device_t dev)
|
||||
IFCAP_VLAN_HWTSO;
|
||||
}
|
||||
|
||||
if (pci_find_extcap(dev, PCIY_PMG, ®) == 0)
|
||||
if (pci_find_cap(dev, PCIY_PMG, ®) == 0)
|
||||
ifp->if_capabilities |= IFCAP_WOL_MAGIC;
|
||||
ifp->if_capenable = ifp->if_capabilities;
|
||||
|
||||
@ -3354,7 +3354,7 @@ nfe_set_wol(struct nfe_softc *sc)
|
||||
|
||||
NFE_LOCK_ASSERT(sc);
|
||||
|
||||
if (pci_find_extcap(sc->nfe_dev, PCIY_PMG, &pmc) != 0)
|
||||
if (pci_find_cap(sc->nfe_dev, PCIY_PMG, &pmc) != 0)
|
||||
return;
|
||||
ifp = sc->nfe_ifp;
|
||||
if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
|
||||
|
@ -1061,7 +1061,7 @@ nge_attach(device_t dev)
|
||||
* supply(3VAUX) to drive PME such that checking PCI power
|
||||
* management capability is necessary.
|
||||
*/
|
||||
if (pci_find_extcap(sc->nge_dev, PCIY_PMG, &i) == 0)
|
||||
if (pci_find_cap(sc->nge_dev, PCIY_PMG, &i) == 0)
|
||||
ifp->if_capabilities |= IFCAP_WOL;
|
||||
ifp->if_capenable = ifp->if_capabilities;
|
||||
|
||||
@ -2689,7 +2689,7 @@ nge_wol(struct nge_softc *sc)
|
||||
|
||||
NGE_LOCK_ASSERT(sc);
|
||||
|
||||
if (pci_find_extcap(sc->nge_dev, PCIY_PMG, &pmc) != 0)
|
||||
if (pci_find_cap(sc->nge_dev, PCIY_PMG, &pmc) != 0)
|
||||
return;
|
||||
|
||||
ifp = sc->nge_ifp;
|
||||
@ -2776,7 +2776,7 @@ nge_resume(device_t dev)
|
||||
|
||||
NGE_LOCK(sc);
|
||||
ifp = sc->nge_ifp;
|
||||
if (pci_find_extcap(sc->nge_dev, PCIY_PMG, &pmc) == 0) {
|
||||
if (pci_find_cap(sc->nge_dev, PCIY_PMG, &pmc) == 0) {
|
||||
/* Disable PME and clear PME status. */
|
||||
pmstat = pci_read_config(sc->nge_dev,
|
||||
pmc + PCIR_POWER_STATUS, 2);
|
||||
|
@ -78,7 +78,7 @@ pci_hostb_attach(device_t dev)
|
||||
* If AGP capabilities are present on this device, then create
|
||||
* an AGP child.
|
||||
*/
|
||||
if (pci_find_extcap(dev, PCIY_AGP, NULL) == 0)
|
||||
if (pci_find_cap(dev, PCIY_AGP, NULL) == 0)
|
||||
device_add_child(dev, "agp", -1);
|
||||
bus_generic_attach(dev);
|
||||
return (0);
|
||||
|
@ -1237,7 +1237,7 @@ re_attach(device_t dev)
|
||||
|
||||
msic = pci_msi_count(dev);
|
||||
msixc = pci_msix_count(dev);
|
||||
if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0)
|
||||
if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0)
|
||||
sc->rl_flags |= RL_FLAG_PCIE;
|
||||
if (bootverbose) {
|
||||
device_printf(dev, "MSI count : %d\n", msic);
|
||||
@ -1561,7 +1561,7 @@ re_attach(device_t dev)
|
||||
if (ifp->if_capabilities & IFCAP_HWCSUM)
|
||||
ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
|
||||
/* Enable WOL if PM is supported. */
|
||||
if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0)
|
||||
if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0)
|
||||
ifp->if_capabilities |= IFCAP_WOL;
|
||||
ifp->if_capenable = ifp->if_capabilities;
|
||||
/*
|
||||
@ -3565,7 +3565,7 @@ re_setwol(struct rl_softc *sc)
|
||||
|
||||
RL_LOCK_ASSERT(sc);
|
||||
|
||||
if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
|
||||
if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
|
||||
return;
|
||||
|
||||
ifp = sc->rl_ifp;
|
||||
@ -3633,7 +3633,7 @@ re_clrwol(struct rl_softc *sc)
|
||||
|
||||
RL_LOCK_ASSERT(sc);
|
||||
|
||||
if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
|
||||
if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
|
||||
return;
|
||||
|
||||
/* Enable config register write. */
|
||||
|
@ -362,7 +362,7 @@ siba_scan(struct siba_softc *siba)
|
||||
case SIBA_DEVID_PCI:
|
||||
case SIBA_DEVID_PCIE:
|
||||
n_pci++;
|
||||
error = pci_find_extcap(siba->siba_dev, PCIY_EXPRESS,
|
||||
error = pci_find_cap(siba->siba_dev, PCIY_EXPRESS,
|
||||
&base);
|
||||
is_pcie = (error == 0) ? 1 : 0;
|
||||
|
||||
|
@ -1192,7 +1192,7 @@ sis_attach(device_t dev)
|
||||
ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1;
|
||||
IFQ_SET_READY(&ifp->if_snd);
|
||||
|
||||
if (pci_find_extcap(sc->sis_dev, PCIY_PMG, &pmc) == 0) {
|
||||
if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) == 0) {
|
||||
if (sc->sis_type == SIS_TYPE_83815)
|
||||
ifp->if_capabilities |= IFCAP_WOL;
|
||||
else
|
||||
@ -2472,7 +2472,7 @@ sis_wol(struct sis_softc *sc)
|
||||
/* Enable silent RX mode. */
|
||||
SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
|
||||
} else {
|
||||
if (pci_find_extcap(sc->sis_dev, PCIY_PMG, &pmc) != 0)
|
||||
if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) != 0)
|
||||
return;
|
||||
val = 0;
|
||||
if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
|
||||
|
@ -1176,7 +1176,7 @@ ste_attach(device_t dev)
|
||||
*/
|
||||
ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
|
||||
ifp->if_capabilities |= IFCAP_VLAN_MTU;
|
||||
if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
|
||||
if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0)
|
||||
ifp->if_capabilities |= IFCAP_WOL_MAGIC;
|
||||
ifp->if_capenable = ifp->if_capabilities;
|
||||
#ifdef DEVICE_POLLING
|
||||
@ -2157,7 +2157,7 @@ ste_resume(device_t dev)
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
STE_LOCK(sc);
|
||||
if (pci_find_extcap(sc->ste_dev, PCIY_PMG, &pmc) == 0) {
|
||||
if (pci_find_cap(sc->ste_dev, PCIY_PMG, &pmc) == 0) {
|
||||
/* Disable PME and clear PME status. */
|
||||
pmstat = pci_read_config(sc->ste_dev,
|
||||
pmc + PCIR_POWER_STATUS, 2);
|
||||
@ -2261,7 +2261,7 @@ ste_setwol(struct ste_softc *sc)
|
||||
|
||||
STE_LOCK_ASSERT(sc);
|
||||
|
||||
if (pci_find_extcap(sc->ste_dev, PCIY_PMG, &pmc) != 0) {
|
||||
if (pci_find_cap(sc->ste_dev, PCIY_PMG, &pmc) != 0) {
|
||||
/* Disable WOL. */
|
||||
CSR_READ_1(sc, STE_WAKE_EVENT);
|
||||
CSR_WRITE_1(sc, STE_WAKE_EVENT, 0);
|
||||
|
@ -423,7 +423,7 @@ txp_attach(device_t dev)
|
||||
* advertise the whole capability anyway.
|
||||
*/
|
||||
ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM;
|
||||
if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
|
||||
if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0)
|
||||
ifp->if_capabilities |= IFCAP_WOL_MAGIC;
|
||||
/* Enable all capabilities. */
|
||||
ifp->if_capenable = ifp->if_capabilities;
|
||||
@ -1153,7 +1153,7 @@ txp_suspend(device_t dev)
|
||||
WRITE_REG(sc, TXP_IER, TXP_INTR_NONE);
|
||||
WRITE_REG(sc, TXP_IMR, TXP_INTR_ALL);
|
||||
txp_sleep(sc, sc->sc_ifp->if_capenable);
|
||||
if (pci_find_extcap(sc->sc_dev, PCIY_PMG, &pmc) == 0) {
|
||||
if (pci_find_cap(sc->sc_dev, PCIY_PMG, &pmc) == 0) {
|
||||
/* Request PME. */
|
||||
pmstat = pci_read_config(sc->sc_dev,
|
||||
pmc + PCIR_POWER_STATUS, 2);
|
||||
@ -1178,7 +1178,7 @@ txp_resume(device_t dev)
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
TXP_LOCK(sc);
|
||||
if (pci_find_extcap(sc->sc_dev, PCIY_PMG, &pmc) == 0) {
|
||||
if (pci_find_cap(sc->sc_dev, PCIY_PMG, &pmc) == 0) {
|
||||
/* Disable PME and clear PME status. */
|
||||
pmstat = pci_read_config(sc->sc_dev,
|
||||
pmc + PCIR_POWER_STATUS, 2);
|
||||
|
@ -1004,12 +1004,12 @@ vge_attach(device_t dev)
|
||||
goto fail;
|
||||
}
|
||||
|
||||
if (pci_find_extcap(dev, PCIY_EXPRESS, &cap) == 0) {
|
||||
if (pci_find_cap(dev, PCIY_EXPRESS, &cap) == 0) {
|
||||
sc->vge_flags |= VGE_FLAG_PCIE;
|
||||
sc->vge_expcap = cap;
|
||||
} else
|
||||
sc->vge_flags |= VGE_FLAG_JUMBO;
|
||||
if (pci_find_extcap(dev, PCIY_PMG, &cap) == 0) {
|
||||
if (pci_find_cap(dev, PCIY_PMG, &cap) == 0) {
|
||||
sc->vge_flags |= VGE_FLAG_PMCAP;
|
||||
sc->vge_pmcap = cap;
|
||||
}
|
||||
|
@ -696,7 +696,7 @@ vr_attach(device_t dev)
|
||||
}
|
||||
|
||||
if (sc->vr_revid >= REV_ID_VT6102_A &&
|
||||
pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
|
||||
pci_find_cap(dev, PCIY_PMG, &pmc) == 0)
|
||||
ifp->if_capabilities |= IFCAP_WOL_UCAST | IFCAP_WOL_MAGIC;
|
||||
|
||||
/* Rhine supports oversized VLAN frame. */
|
||||
@ -711,7 +711,7 @@ vr_attach(device_t dev)
|
||||
* shuts down. Be sure to kick it in the head to wake it
|
||||
* up again.
|
||||
*/
|
||||
if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
|
||||
if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0)
|
||||
VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1));
|
||||
|
||||
/*
|
||||
@ -2494,7 +2494,7 @@ vr_setwol(struct vr_softc *sc)
|
||||
VR_LOCK_ASSERT(sc);
|
||||
|
||||
if (sc->vr_revid < REV_ID_VT6102_A ||
|
||||
pci_find_extcap(sc->vr_dev, PCIY_PMG, &pmc) != 0)
|
||||
pci_find_cap(sc->vr_dev, PCIY_PMG, &pmc) != 0)
|
||||
return;
|
||||
|
||||
ifp = sc->vr_ifp;
|
||||
|
@ -1407,7 +1407,7 @@ xl_attach(device_t dev)
|
||||
|
||||
/* Check availability of WOL. */
|
||||
if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 &&
|
||||
pci_find_extcap(dev, PCIY_PMG, &pmcap) == 0) {
|
||||
pci_find_cap(dev, PCIY_PMG, &pmcap) == 0) {
|
||||
sc->xl_pmcap = pmcap;
|
||||
sc->xl_flags |= XL_FLAG_WOL;
|
||||
sinfo2 = 0;
|
||||
|
@ -299,7 +299,7 @@ pci_find_capability(struct pci_dev *pdev, int capid)
|
||||
{
|
||||
int reg;
|
||||
|
||||
if (pci_find_extcap(pdev->dev.bsddev, capid, ®))
|
||||
if (pci_find_cap(pdev->dev.bsddev, capid, ®))
|
||||
return (0);
|
||||
return (reg);
|
||||
}
|
||||
|
@ -939,7 +939,7 @@ rl_attach(device_t dev)
|
||||
ifp->if_capabilities = IFCAP_VLAN_MTU;
|
||||
/* Check WOL for RTL8139B or newer controllers. */
|
||||
if (sc->rl_type == RL_8139 &&
|
||||
pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
|
||||
pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
|
||||
hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
|
||||
switch (hwrev) {
|
||||
case RL_HWREV_8139B:
|
||||
@ -2122,7 +2122,7 @@ rl_resume(device_t dev)
|
||||
RL_LOCK(sc);
|
||||
|
||||
if ((ifp->if_capabilities & IFCAP_WOL) != 0 &&
|
||||
pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
|
||||
pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
|
||||
/* Disable PME and clear PME status. */
|
||||
pmstat = pci_read_config(sc->rl_dev,
|
||||
pmc + PCIR_POWER_STATUS, 2);
|
||||
@ -2187,7 +2187,7 @@ rl_setwol(struct rl_softc *sc)
|
||||
ifp = sc->rl_ifp;
|
||||
if ((ifp->if_capabilities & IFCAP_WOL) == 0)
|
||||
return;
|
||||
if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
|
||||
if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
|
||||
return;
|
||||
|
||||
/* Enable config register write. */
|
||||
|
Loading…
Reference in New Issue
Block a user