Try to make the style used here consistent.
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commit
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=261529
@ -163,7 +163,6 @@
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#define RL_LOOPTEST_ON_CPLUS 0x00060000
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/* Known revision codes. */
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#define RL_HWREV_8169 0x00000000
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#define RL_HWREV_8169S 0x00800000
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#define RL_HWREV_8110S 0x04000000
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@ -329,8 +328,8 @@
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#define RL_RXSTAT_INDIV 0x00004000
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#define RL_RXSTAT_MULTI 0x00008000
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#define RL_RXSTAT_LENMASK 0xFFFF0000
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#define RL_RXSTAT_UNFINISHED 0x0000FFF0 /* DMA still in progress */
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#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */
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/*
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* Command register.
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*/
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@ -361,6 +360,7 @@
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#define RL_PARA7C 0x7C
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#define RL_PARA7C_DEF 0xcb38de43
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#define RL_PARA7C_RETUNE 0xfb38de03
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/*
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* EEPROM control register
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*/
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@ -473,11 +473,9 @@
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*/
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/* RL_DUMPSTATS_LO register */
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#define RL_DUMPSTATS_START 0x00000008
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/* Transmit start register */
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#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */
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#define RL_TXSTART_START 0x40 /* start normal queue transmit */
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#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */
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@ -496,7 +494,6 @@
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#define RL_BUSWIDTH_64BITS 0x08
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/* C+ mode command register */
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#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */
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#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */
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#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */
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@ -514,7 +511,6 @@
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#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */
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/* C+ early transmit threshold */
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#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */
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/* Timer interrupt register */
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@ -528,7 +524,6 @@
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/*
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* Gigabit PHY access register (8169 only)
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*/
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#define RL_PHYAR_PHYDATA 0x0000FFFF
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#define RL_PHYAR_PHYREG 0x001F0000
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#define RL_PHYAR_BUSY 0x80000000
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@ -559,7 +554,6 @@
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* For reception, there's just one large buffer where the chip stores
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* all received packets.
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*/
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#define RL_RX_BUF_SZ RL_RXBUF_64
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#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13))
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#define RL_TX_LIST_CNT 4
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@ -642,11 +636,10 @@ struct rl_hwrev {
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/*
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* RX/TX descriptor definition. When large send mode is enabled, the
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* lower 11 bits of the TX rl_cmd word are used to hold the MSS, and
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* lower 11 bits of the TX rl_cmdstat word are used to hold the MSS, and
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* the checksum offload bits are disabled. The structure layout is
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* the same for RX and TX descriptors
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*/
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struct rl_desc {
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uint32_t rl_cmdstat;
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uint32_t rl_vlanctl;
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@ -679,7 +672,6 @@ struct rl_desc {
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* Error bits are valid only on the last descriptor of a frame
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* (i.e. RL_TDESC_CMD_EOF == 1)
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*/
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#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */
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#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */
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#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */
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@ -691,7 +683,6 @@ struct rl_desc {
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/*
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* RX descriptor cmd/vlan definitions
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*/
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#define RL_RDESC_CMD_EOR 0x40000000
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#define RL_RDESC_CMD_OWN 0x80000000
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#define RL_RDESC_CMD_BUFLEN 0x00001FFF
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