arm: allwinner: clk: Add new clock aw_clk_frac
Add a clock driver for clock that can either be used in integer mode with one N factor and one M divider or in fractional mode where the output frequency is chosen between two predifined output.
This commit is contained in:
Emmanuel Vadot
parent
f7e598f60b
commit
3b85cf6b3f
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=348180
@ -305,6 +305,9 @@ aw_ccung_attach(device_t dev)
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aw_clk_prediv_mux_register(sc->clkdom,
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sc->clks[i].clk.prediv_mux);
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break;
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case AW_CLK_FRAC:
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aw_clk_frac_register(sc->clkdom, sc->clks[i].clk.frac);
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break;
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}
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}
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@ -34,6 +34,7 @@
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#include <arm/allwinner/clkng/aw_clk_nkmp.h>
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#include <arm/allwinner/clkng/aw_clk_nm.h>
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#include <arm/allwinner/clkng/aw_clk_prediv_mux.h>
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#include <arm/allwinner/clkng/aw_clk_frac.h>
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#include <dev/extres/clk/clk_mux.h>
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#include <dev/extres/clk/clk_div.h>
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#include <dev/extres/clk/clk_fixed.h>
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@ -46,6 +47,7 @@ enum aw_ccung_clk_type {
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AW_CLK_NKMP,
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AW_CLK_NM,
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AW_CLK_PREDIV_MUX,
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AW_CLK_FRAC,
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};
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struct aw_ccung_clk {
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@ -57,6 +59,7 @@ struct aw_ccung_clk {
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struct aw_clk_nkmp_def *nkmp;
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struct aw_clk_nm_def *nm;
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struct aw_clk_prediv_mux_def *prediv_mux;
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struct aw_clk_frac_def *frac;
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} clk;
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};
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@ -309,6 +309,38 @@ aw_clk_factor_get_value(struct aw_clk_factor *factor, uint32_t raw)
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.flags = _flags | AW_CLK_HAS_UPDATE, \
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}
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#define FRAC_CLK(_clkname, _id, _name, _pnames, \
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_offset, \
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_nshift, _nwidth, _nvalue, _nflags, \
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_mshift, _mwidth, _mvalue, _mflags, \
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_gate_shift, _lock_shift,_lock_retries, \
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_flags, _freq0, _freq1, _mode_sel, _freq_sel) \
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static struct aw_clk_frac_def _clkname = { \
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.clkdef = { \
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.id = _id, \
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.name = _name, \
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.parent_names = _pnames, \
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.parent_cnt = nitems(_pnames), \
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}, \
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.offset = _offset, \
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.n.shift = _nshift, \
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.n.width = _nwidth, \
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.n.value = _nvalue, \
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.n.flags = _nflags, \
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.m.shift = _mshift, \
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.m.width = _mwidth, \
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.m.value = _mvalue, \
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.m.flags = _mflags, \
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.gate_shift = _gate_shift, \
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.lock_shift = _lock_shift, \
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.lock_retries = _lock_retries, \
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.flags = _flags | AW_CLK_HAS_FRAC, \
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.frac.freq0 = _freq0, \
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.frac.freq1 = _freq1, \
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.frac.mode_sel = _mode_sel, \
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.frac.freq_sel = _freq_sel, \
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}
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#define NM_CLK(_clkname, _id, _name, _pnames, \
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_offset, \
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_nshift, _nwidth, _nvalue, _nflags, \
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338
sys/arm/allwinner/clkng/aw_clk_frac.c
Normal file
338
sys/arm/allwinner/clkng/aw_clk_frac.c
Normal file
@ -0,0 +1,338 @@
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/*-
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* Copyright (c) 2019 Emmanuel Vadot <manu@freebsd.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <dev/extres/clk/clk.h>
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#include <arm/allwinner/clkng/aw_clk.h>
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#include <arm/allwinner/clkng/aw_clk_frac.h>
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#include "clkdev_if.h"
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/*
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* clknode for clocks matching the formula :
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*
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* clk = (24Mhz * n) / m in integer mode
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* clk = frac_out1 or frac_out2 in fractional mode
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*
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*/
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struct aw_clk_frac_sc {
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uint32_t offset;
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struct aw_clk_factor m;
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struct aw_clk_factor n;
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struct aw_clk_frac frac;
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uint32_t mux_shift;
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uint32_t mux_mask;
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uint32_t gate_shift;
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uint32_t lock_shift;
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uint32_t lock_retries;
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uint32_t flags;
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};
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#define WRITE4(_clk, off, val) \
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CLKDEV_WRITE_4(clknode_get_device(_clk), off, val)
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#define READ4(_clk, off, val) \
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CLKDEV_READ_4(clknode_get_device(_clk), off, val)
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#define DEVICE_LOCK(_clk) \
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CLKDEV_DEVICE_LOCK(clknode_get_device(_clk))
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#define DEVICE_UNLOCK(_clk) \
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CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk))
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static int
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aw_clk_frac_init(struct clknode *clk, device_t dev)
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{
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struct aw_clk_frac_sc *sc;
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uint32_t val, idx;
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sc = clknode_get_softc(clk);
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idx = 0;
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if ((sc->flags & AW_CLK_HAS_MUX) != 0) {
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DEVICE_LOCK(clk);
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READ4(clk, sc->offset, &val);
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DEVICE_UNLOCK(clk);
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idx = (val & sc->mux_mask) >> sc->mux_shift;
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}
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clknode_init_parent_idx(clk, idx);
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return (0);
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}
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static int
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aw_clk_frac_set_gate(struct clknode *clk, bool enable)
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{
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struct aw_clk_frac_sc *sc;
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uint32_t val;
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sc = clknode_get_softc(clk);
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if ((sc->flags & AW_CLK_HAS_GATE) == 0)
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return (0);
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DEVICE_LOCK(clk);
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READ4(clk, sc->offset, &val);
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if (enable)
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val |= (1 << sc->gate_shift);
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else
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val &= ~(1 << sc->gate_shift);
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WRITE4(clk, sc->offset, val);
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DEVICE_UNLOCK(clk);
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return (0);
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}
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static int
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aw_clk_frac_set_mux(struct clknode *clk, int index)
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{
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struct aw_clk_frac_sc *sc;
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uint32_t val;
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sc = clknode_get_softc(clk);
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if ((sc->flags & AW_CLK_HAS_MUX) == 0)
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return (0);
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DEVICE_LOCK(clk);
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READ4(clk, sc->offset, &val);
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val &= ~sc->mux_mask;
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val |= index << sc->mux_shift;
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WRITE4(clk, sc->offset, val);
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DEVICE_UNLOCK(clk);
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return (0);
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}
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static uint64_t
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aw_clk_frac_find_best(struct aw_clk_frac_sc *sc, uint64_t fparent, uint64_t *fout,
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uint32_t *factor_n, uint32_t *factor_m)
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{
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uint64_t cur, best;
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uint32_t m, n, max_m, max_n, min_m, min_n;
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*factor_n = *factor_m = 0;
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best = cur = 0;
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max_m = aw_clk_factor_get_max(&sc->m);
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max_n = aw_clk_factor_get_max(&sc->n);
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min_m = aw_clk_factor_get_min(&sc->m);
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min_n = aw_clk_factor_get_min(&sc->n);
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for (n = min_n; n <= max_n; n++) {
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for (m = min_m; m <= max_m; m++) {
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cur = fparent * n / m;
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if ((*fout - cur) < (*fout - best)) {
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best = cur;
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*factor_n = n;
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*factor_m = m;
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}
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if (best == *fout)
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return (best);
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}
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}
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return (best);
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}
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static int
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aw_clk_frac_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
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int flags, int *stop)
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{
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struct aw_clk_frac_sc *sc;
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uint64_t cur, best, best_frac;
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uint32_t val, m, n, best_m, best_n;
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int retry;
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sc = clknode_get_softc(clk);
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best = best_frac = cur = 0;
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if (*fout == sc->frac.freq0)
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best = best_frac = sc->frac.freq0;
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else if (*fout == sc->frac.freq1)
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best = best_frac = sc->frac.freq1;
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else
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best = aw_clk_frac_find_best(sc, fparent, fout,
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&best_n, &best_m);
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if ((flags & CLK_SET_DRYRUN) != 0) {
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*fout = best;
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*stop = 1;
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return (0);
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}
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if ((best < *fout) &&
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((flags & CLK_SET_ROUND_DOWN) == 0)) {
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*stop = 1;
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return (ERANGE);
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}
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if ((best > *fout) &&
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((flags & CLK_SET_ROUND_UP) == 0)) {
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*stop = 1;
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return (ERANGE);
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}
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DEVICE_LOCK(clk);
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READ4(clk, sc->offset, &val);
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/* Disable clock during freq changes */
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val &= ~(1 << sc->gate_shift);
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WRITE4(clk, sc->offset, val);
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if (best_frac != 0) {
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val &= ~sc->frac.mode_sel;
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/* M should be 0 per the manual */
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val &= ~sc->m.mask;
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if (best_frac == sc->frac.freq0)
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val &= ~sc->frac.freq_sel;
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else
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val |= sc->frac.freq_sel;
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} else {
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val |= sc->frac.mode_sel; /* Select integer mode */
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n = aw_clk_factor_get_value(&sc->n, best_n);
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m = aw_clk_factor_get_value(&sc->m, best_m);
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val &= ~sc->n.mask;
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val &= ~sc->m.mask;
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val |= n << sc->n.shift;
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val |= m << sc->m.shift;
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}
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/* Write the clock changes */
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WRITE4(clk, sc->offset, val);
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/* Enable clock now that we've change it */
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val |= 1 << sc->gate_shift;
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WRITE4(clk, sc->offset, val);
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DEVICE_UNLOCK(clk);
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for (retry = 0; retry < sc->lock_retries; retry++) {
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READ4(clk, sc->offset, &val);
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if ((val & (1 << sc->lock_shift)) != 0)
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break;
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DELAY(1000);
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}
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*fout = best;
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*stop = 1;
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return (0);
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}
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static int
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aw_clk_frac_recalc(struct clknode *clk, uint64_t *freq)
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{
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struct aw_clk_frac_sc *sc;
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uint32_t val, m, n;
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sc = clknode_get_softc(clk);
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DEVICE_LOCK(clk);
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READ4(clk, sc->offset, &val);
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DEVICE_UNLOCK(clk);
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if ((val & sc->frac.mode_sel) == 0) {
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if (val & sc->frac.freq_sel)
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*freq = sc->frac.freq1;
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else
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*freq = sc->frac.freq0;
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} else {
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m = aw_clk_get_factor(val, &sc->m);
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n = aw_clk_get_factor(val, &sc->n);
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*freq = *freq * n / m;
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}
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return (0);
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}
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static clknode_method_t aw_frac_clknode_methods[] = {
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/* Device interface */
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CLKNODEMETHOD(clknode_init, aw_clk_frac_init),
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CLKNODEMETHOD(clknode_set_gate, aw_clk_frac_set_gate),
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CLKNODEMETHOD(clknode_set_mux, aw_clk_frac_set_mux),
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CLKNODEMETHOD(clknode_recalc_freq, aw_clk_frac_recalc),
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CLKNODEMETHOD(clknode_set_freq, aw_clk_frac_set_freq),
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CLKNODEMETHOD_END
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};
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DEFINE_CLASS_1(aw_frac_clknode, aw_frac_clknode_class, aw_frac_clknode_methods,
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sizeof(struct aw_clk_frac_sc), clknode_class);
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int
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aw_clk_frac_register(struct clkdom *clkdom, struct aw_clk_frac_def *clkdef)
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{
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struct clknode *clk;
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struct aw_clk_frac_sc *sc;
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clk = clknode_create(clkdom, &aw_frac_clknode_class, &clkdef->clkdef);
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if (clk == NULL)
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return (1);
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sc = clknode_get_softc(clk);
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sc->offset = clkdef->offset;
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sc->m.shift = clkdef->m.shift;
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sc->m.width = clkdef->m.width;
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sc->m.mask = ((1 << sc->m.width) - 1) << sc->m.shift;
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sc->m.value = clkdef->m.value;
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sc->m.flags = clkdef->m.flags;
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sc->n.shift = clkdef->n.shift;
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sc->n.width = clkdef->n.width;
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sc->n.mask = ((1 << sc->n.width) - 1) << sc->n.shift;
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sc->n.value = clkdef->n.value;
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sc->n.flags = clkdef->n.flags;
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sc->frac.freq0 = clkdef->frac.freq0;
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sc->frac.freq1 = clkdef->frac.freq1;
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sc->frac.mode_sel = 1 << clkdef->frac.mode_sel;
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sc->frac.freq_sel = 1 << clkdef->frac.freq_sel;
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sc->mux_shift = clkdef->mux_shift;
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sc->mux_mask = ((1 << clkdef->mux_width) - 1) << sc->mux_shift;
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sc->gate_shift = clkdef->gate_shift;
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sc->lock_shift = clkdef->lock_shift;
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sc->lock_retries = clkdef->lock_retries;
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sc->flags = clkdef->flags;
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clknode_register(clkdom, clk);
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return (0);
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}
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52
sys/arm/allwinner/clkng/aw_clk_frac.h
Normal file
52
sys/arm/allwinner/clkng/aw_clk_frac.h
Normal file
@ -0,0 +1,52 @@
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/*-
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* Copyright (c) 2019 Emmanuel Vadot <manu@freebsd.org>
|
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*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
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*/
|
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#ifndef __AW_CLK_FRAC_H__
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#define __AW_CLK_FRAC_H__
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#include <dev/extres/clk/clk.h>
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struct aw_clk_frac_def {
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struct clknode_init_def clkdef;
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uint32_t offset;
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struct aw_clk_factor m;
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struct aw_clk_factor n;
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struct aw_clk_frac frac;
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|
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uint32_t mux_shift;
|
||||
uint32_t mux_width;
|
||||
uint32_t gate_shift;
|
||||
uint32_t lock_shift;
|
||||
uint32_t lock_retries;
|
||||
|
||||
uint32_t flags;
|
||||
};
|
||||
|
||||
int aw_clk_frac_register(struct clkdom *clkdom, struct aw_clk_frac_def *clkdef);
|
||||
|
||||
#endif /* __AW_CLK_FRAC_H__ */
|
||||
@ -36,6 +36,7 @@ arm/allwinner/aw_ccu.c standard
|
||||
arm/allwinner/aw_gmacclk.c standard
|
||||
|
||||
arm/allwinner/clkng/aw_ccung.c standard
|
||||
arm/allwinner/clkng/aw_clk_frac.c standard
|
||||
arm/allwinner/clkng/aw_clk_nkmp.c standard
|
||||
arm/allwinner/clkng/aw_clk_nm.c standard
|
||||
arm/allwinner/clkng/aw_clk_prediv_mux.c standard
|
||||
|
||||
@ -49,6 +49,7 @@ arm/allwinner/if_awg.c optional awg ext_resources syscon aw_sid nvmem fdt
|
||||
|
||||
# Allwinner clock driver
|
||||
arm/allwinner/clkng/aw_ccung.c optional aw_ccu fdt
|
||||
arm/allwinner/clkng/aw_clk_frac.c optional aw_ccu fdt
|
||||
arm/allwinner/clkng/aw_clk_nkmp.c optional aw_ccu fdt
|
||||
arm/allwinner/clkng/aw_clk_nm.c optional aw_ccu fdt
|
||||
arm/allwinner/clkng/aw_clk_prediv_mux.c optional aw_ccu fdt
|
||||
|
||||
Loading…
Reference in New Issue
Block a user