AMD64 on-CPU GART support.
This also applies to AMD64 HW running 'i386' OS. Submitted by: Jung-uk Kim <jkim@niksun.com> Integration by: obrien
This commit is contained in:
David E. O'Brien
parent
15720d822e
commit
3c749e3fb1
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=133852
@ -150,12 +150,8 @@ isa/psm.c optional psm
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isa/syscons_isa.c optional sc
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isa/vga_isa.c optional vga
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kern/link_elf_obj.c standard
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pci/agp_ali.c optional agp
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pci/agp_amd.c optional agp
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pci/agp_i810.c optional agp
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pci/agp_amd64.c optional agp
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pci/agp_intel.c optional agp
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pci/agp_sis.c optional agp
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pci/agp_via.c optional agp
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#
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# IA32 binary support
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#
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@ -415,6 +415,7 @@ libkern/udivdi3.c standard
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libkern/umoddi3.c standard
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pci/agp_ali.c optional agp
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pci/agp_amd.c optional agp
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pci/agp_amd64.c optional agp
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pci/agp_i810.c optional agp
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pci/agp_intel.c optional agp
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pci/agp_nvidia.c optional agp
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@ -162,3 +162,6 @@ IPR_LOG opt_i4b.h
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# Device options
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DEV_APIC opt_apic.h
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DEV_NPX opt_npx.h
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# agp options
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AGP_AMD64_GART opt_agp.h
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@ -87,7 +87,7 @@ static devclass_t agp_devclass;
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void
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agp_flush_cache()
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{
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#ifdef __i386__
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#if defined(__i386__) || defined(__amd64__)
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wbinvd();
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#endif
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#ifdef __alpha__
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311
sys/dev/agp/agp_amd64.c
Normal file
311
sys/dev/agp/agp_amd64.c
Normal file
@ -0,0 +1,311 @@
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/*-
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* Copyright (c) 2004 Jung-uk Kim
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_bus.h"
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#ifdef __i386__
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#include "opt_agp.h"
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#endif
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <pci/agppriv.h>
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#include <pci/agpreg.h>
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#include <vm/vm.h>
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#include <vm/vm_object.h>
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#include <vm/pmap.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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/* XXX */
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extern void pci_cfgregwrite(int, int, int, int, uint32_t, int);
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extern uint32_t pci_cfgregread(int, int, int, int, int);
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MALLOC_DECLARE(M_AGP);
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#define AMD64_MAX_MCTRL 8
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struct agp_amd64_softc {
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struct agp_softc agp;
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uint32_t initial_aperture; /* aperture size at startup */
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struct agp_gatt *gatt;
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int mctrl[AMD64_MAX_MCTRL];
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int n_mctrl;
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};
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static const char*
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agp_amd64_match(device_t dev)
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{
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if (pci_get_class(dev) != PCIC_BRIDGE
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|| pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
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return NULL;
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if (agp_find_caps(dev) == 0)
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return NULL;
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switch (pci_get_devid(dev)) {
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case 0x74541022:
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return ("AMD 8151 AGP graphics tunnel");
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case 0x10221039:
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return ("SiS 755 host to AGP bridge");
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case 0x02041106:
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return ("VIA 8380 host to PCI bridge");
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case 0x31881106:
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return ("VIA 8385 host to PCI bridge");
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};
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return NULL;
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}
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static int
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agp_amd64_probe(device_t dev)
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{
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const char *desc;
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if (resource_disabled("agp", device_get_unit(dev)))
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return ENXIO;
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if ((desc = agp_amd64_match(dev))) {
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device_verbose(dev);
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device_set_desc(dev, desc);
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return 0;
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}
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return ENXIO;
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}
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static int
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agp_amd64_attach(device_t dev)
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{
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struct agp_amd64_softc *sc = device_get_softc(dev);
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struct agp_gatt *gatt;
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int i, n, error;
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for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++)
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if (pci_cfgregread(0, i, 3, 0, 4) == 0x11031022) {
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sc->mctrl[n] = i;
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n++;
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}
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if (n == 0)
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return ENXIO;
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sc->n_mctrl = n;
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if (bootverbose)
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printf("AMD64: %d Misc. Control unit(s) found.\n", sc->n_mctrl);
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if ((error = agp_generic_attach(dev)))
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return error;
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sc->initial_aperture = AGP_GET_APERTURE(dev);
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for (;;) {
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gatt = agp_alloc_gatt(dev);
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if (gatt)
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break;
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/*
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* Probably contigmalloc failure. Try reducing the
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* aperture so that the gatt size reduces.
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*/
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if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
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agp_generic_detach(dev);
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return ENOMEM;
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}
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}
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sc->gatt = gatt;
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/* Install the gatt and enable aperture. */
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for (i = 0; i < sc->n_mctrl; i++) {
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pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE,
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(uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK,
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4);
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pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
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(pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) |
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AGP_AMD64_APCTRL_GARTEN) &
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~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO),
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4);
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}
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agp_flush_cache();
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return 0;
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}
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static int
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agp_amd64_detach(device_t dev)
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{
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struct agp_amd64_softc *sc = device_get_softc(dev);
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int i, error;
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if ((error = agp_generic_detach(dev)))
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return error;
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for (i = 0; i < sc->n_mctrl; i++)
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pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
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pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) &
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~AGP_AMD64_APCTRL_GARTEN, 4);
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AGP_SET_APERTURE(dev, sc->initial_aperture);
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agp_free_gatt(sc->gatt);
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return 0;
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}
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static uint32_t agp_amd64_table[] = {
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0x02000000, /* 32 MB */
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0x04000000, /* 64 MB */
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0x08000000, /* 128 MB */
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0x10000000, /* 256 MB */
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0x20000000, /* 512 MB */
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0x40000000, /* 1024 MB */
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0x80000000, /* 2048 MB */
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};
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#define AGP_AMD64_TABLE_SIZE \
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(sizeof(agp_amd64_table) / sizeof(agp_amd64_table[0]))
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static uint32_t
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agp_amd64_get_aperture(device_t dev)
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{
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struct agp_amd64_softc *sc = device_get_softc(dev);
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uint32_t i;
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i = (pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) &
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AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
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if (i >= AGP_AMD64_TABLE_SIZE)
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return 0;
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return (agp_amd64_table[i]);
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}
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static int
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agp_amd64_set_aperture(device_t dev, uint32_t aperture)
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{
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struct agp_amd64_softc *sc = device_get_softc(dev);
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uint32_t i;
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int j;
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for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
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if (agp_amd64_table[i] == aperture)
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break;
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if (i == AGP_AMD64_TABLE_SIZE)
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return EINVAL;
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for (j = 0; j < sc->n_mctrl; j++)
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pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL,
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(pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) &
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~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4);
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return 0;
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}
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static int
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agp_amd64_bind_page(device_t dev, int offset, vm_offset_t physical)
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{
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struct agp_amd64_softc *sc = device_get_softc(dev);
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if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
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return EINVAL;
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sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical;
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return 0;
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}
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static int
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agp_amd64_unbind_page(device_t dev, int offset)
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{
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struct agp_amd64_softc *sc = device_get_softc(dev);
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if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
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return EINVAL;
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sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
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return 0;
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}
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static void
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agp_amd64_flush_tlb(device_t dev)
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{
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struct agp_amd64_softc *sc = device_get_softc(dev);
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int i;
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for (i = 0; i < sc->n_mctrl; i++)
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pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL,
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pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) |
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AGP_AMD64_CACHECTRL_INVGART, 4);
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}
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static device_method_t agp_amd64_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, agp_amd64_probe),
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DEVMETHOD(device_attach, agp_amd64_attach),
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DEVMETHOD(device_detach, agp_amd64_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_resume, bus_generic_resume),
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/* AGP interface */
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DEVMETHOD(agp_get_aperture, agp_amd64_get_aperture),
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DEVMETHOD(agp_set_aperture, agp_amd64_set_aperture),
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DEVMETHOD(agp_bind_page, agp_amd64_bind_page),
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DEVMETHOD(agp_unbind_page, agp_amd64_unbind_page),
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DEVMETHOD(agp_flush_tlb, agp_amd64_flush_tlb),
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DEVMETHOD(agp_enable, agp_generic_enable),
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DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
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DEVMETHOD(agp_free_memory, agp_generic_free_memory),
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DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
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DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
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{ 0, 0 }
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};
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static driver_t agp_amd64_driver = {
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"agp",
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agp_amd64_methods,
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sizeof(struct agp_amd64_softc),
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};
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static devclass_t agp_devclass;
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DRIVER_MODULE(agp_amd64, pci, agp_amd64_driver, agp_devclass, 0, 0);
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MODULE_DEPEND(agp_amd64, agp, 1, 1, 1);
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MODULE_DEPEND(agp_amd64, pci, 1, 1, 1);
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@ -28,6 +28,7 @@
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__FBSDID("$FreeBSD$");
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#include "opt_bus.h"
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#include "opt_agp.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -105,6 +106,10 @@ agp_sis_match(device_t dev)
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return ("SiS 746 host to AGP bridge");
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case 0x07601039:
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return ("SiS 760 host to AGP bridge");
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#if defined(__amd64__) || defined(AGP_AMD64_GART)
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case 0x10221039: /* AMD64 */
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return NULL;
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#endif
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};
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if (pci_get_vendor(dev) == 0x1039)
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@ -28,6 +28,7 @@
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__FBSDID("$FreeBSD$");
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#include "opt_bus.h"
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#include "opt_agp.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -88,7 +89,11 @@ agp_via_match(device_t dev)
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case 0x06911106:
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return ("VIA 82C691 (Apollo Pro) host to PCI bridge");
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case 0x31881106:
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#if defined(__amd64__) || defined(AGP_AMD64_GART)
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return NULL;
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#else
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return ("VIA 8385 host to PCI bridge");
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#endif
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case 0x31891106:
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return ("VIA 8377 (Apollo KT400/KT400A/KT600) host to PCI bridge");
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};
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@ -125,7 +130,9 @@ agp_via_attach(device_t dev)
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u_int32_t agpsel;
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switch (pci_get_devid(dev)) {
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#ifdef AGP_NO_AMD64_GART
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case 0x31881106:
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#endif
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case 0x31891106:
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/* The newer VIA chipsets will select the AGP version based on
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* what AGP versions the card supports. We still have to
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@ -245,4 +245,21 @@
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#define AGP_NVIDIA_3_APBASE 0x50
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#define AGP_NVIDIA_3_APLIMIT 0x54
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/*
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* AMD64 GART registers
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*/
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#define AGP_AMD64_APCTRL 0x90
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#define AGP_AMD64_APBASE 0x94
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#define AGP_AMD64_ATTBASE 0x98
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#define AGP_AMD64_CACHECTRL 0x9c
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#define AGP_AMD64_APCTRL_GARTEN 0x00000001
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#define AGP_AMD64_APCTRL_SIZE_MASK 0x0000000e
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#define AGP_AMD64_APCTRL_DISGARTCPU 0x00000010
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#define AGP_AMD64_APCTRL_DISGARTIO 0x00000020
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#define AGP_AMD64_APCTRL_DISWLKPRB 0x00000040
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#define AGP_AMD64_APBASE_MASK 0x00007fff
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#define AGP_AMD64_ATTBASE_MASK 0xfffffff0
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#define AGP_AMD64_CACHECTRL_INVGART 0x00000001
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#define AGP_AMD64_CACHECTRL_PTEERR 0x00000002
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#endif /* !_PCI_AGPREG_H_ */
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@ -350,6 +350,7 @@ device pci
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#
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# AGP GART support
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device agp
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options AGP_AMD64_GART # Included GART code for AMD64 machines.
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#####################################################################
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@ -375,6 +375,8 @@ _sppp= sppp
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.endif
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.if ${MACHINE_ARCH} == "amd64"
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_agp= agp
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_drm= drm
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_io= io
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#_ndis= ndis
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.endif
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@ -6,11 +6,14 @@ KMOD= agp
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SRCS= agp.c agp_if.c
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.if ${MACHINE_ARCH} == "i386"
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SRCS+= agp_i810.c agp_intel.c agp_via.c agp_sis.c agp_ali.c agp_amd.c \
|
||||
agp_nvidia.c
|
||||
agp_amd64.c agp_nvidia.c opt_agp.h
|
||||
.endif
|
||||
.if ${MACHINE_ARCH} == "alpha"
|
||||
SRCS+= agp_amd.c
|
||||
.endif
|
||||
.if ${MACHINE_ARCH} == "amd64"
|
||||
SRCS+= agp_amd64.c
|
||||
.endif
|
||||
SRCS+= device_if.h bus_if.h agp_if.h pci_if.h
|
||||
SRCS+= opt_bdg.h opt_bus.h
|
||||
MFILES= kern/device_if.m kern/bus_if.m pci/agp_if.m dev/pci/pci_if.m
|
||||
|
||||
@ -87,7 +87,7 @@ static devclass_t agp_devclass;
|
||||
void
|
||||
agp_flush_cache()
|
||||
{
|
||||
#ifdef __i386__
|
||||
#if defined(__i386__) || defined(__amd64__)
|
||||
wbinvd();
|
||||
#endif
|
||||
#ifdef __alpha__
|
||||
|
||||
311
sys/pci/agp_amd64.c
Normal file
311
sys/pci/agp_amd64.c
Normal file
@ -0,0 +1,311 @@
|
||||
/*-
|
||||
* Copyright (c) 2004 Jung-uk Kim
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include "opt_bus.h"
|
||||
#ifdef __i386__
|
||||
#include "opt_agp.h"
|
||||
#endif
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/lock.h>
|
||||
#include <sys/mutex.h>
|
||||
#include <sys/proc.h>
|
||||
|
||||
#include <dev/pci/pcivar.h>
|
||||
#include <dev/pci/pcireg.h>
|
||||
#include <pci/agppriv.h>
|
||||
#include <pci/agpreg.h>
|
||||
|
||||
#include <vm/vm.h>
|
||||
#include <vm/vm_object.h>
|
||||
#include <vm/pmap.h>
|
||||
#include <machine/bus.h>
|
||||
#include <machine/resource.h>
|
||||
#include <sys/rman.h>
|
||||
|
||||
/* XXX */
|
||||
extern void pci_cfgregwrite(int, int, int, int, uint32_t, int);
|
||||
extern uint32_t pci_cfgregread(int, int, int, int, int);
|
||||
|
||||
MALLOC_DECLARE(M_AGP);
|
||||
|
||||
#define AMD64_MAX_MCTRL 8
|
||||
|
||||
struct agp_amd64_softc {
|
||||
struct agp_softc agp;
|
||||
uint32_t initial_aperture; /* aperture size at startup */
|
||||
struct agp_gatt *gatt;
|
||||
int mctrl[AMD64_MAX_MCTRL];
|
||||
int n_mctrl;
|
||||
};
|
||||
|
||||
static const char*
|
||||
agp_amd64_match(device_t dev)
|
||||
{
|
||||
if (pci_get_class(dev) != PCIC_BRIDGE
|
||||
|| pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
|
||||
return NULL;
|
||||
|
||||
if (agp_find_caps(dev) == 0)
|
||||
return NULL;
|
||||
|
||||
switch (pci_get_devid(dev)) {
|
||||
case 0x74541022:
|
||||
return ("AMD 8151 AGP graphics tunnel");
|
||||
case 0x10221039:
|
||||
return ("SiS 755 host to AGP bridge");
|
||||
case 0x02041106:
|
||||
return ("VIA 8380 host to PCI bridge");
|
||||
case 0x31881106:
|
||||
return ("VIA 8385 host to PCI bridge");
|
||||
};
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int
|
||||
agp_amd64_probe(device_t dev)
|
||||
{
|
||||
const char *desc;
|
||||
|
||||
if (resource_disabled("agp", device_get_unit(dev)))
|
||||
return ENXIO;
|
||||
if ((desc = agp_amd64_match(dev))) {
|
||||
device_verbose(dev);
|
||||
device_set_desc(dev, desc);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return ENXIO;
|
||||
}
|
||||
|
||||
static int
|
||||
agp_amd64_attach(device_t dev)
|
||||
{
|
||||
struct agp_amd64_softc *sc = device_get_softc(dev);
|
||||
struct agp_gatt *gatt;
|
||||
int i, n, error;
|
||||
|
||||
for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++)
|
||||
if (pci_cfgregread(0, i, 3, 0, 4) == 0x11031022) {
|
||||
sc->mctrl[n] = i;
|
||||
n++;
|
||||
}
|
||||
|
||||
if (n == 0)
|
||||
return ENXIO;
|
||||
|
||||
sc->n_mctrl = n;
|
||||
|
||||
if (bootverbose)
|
||||
printf("AMD64: %d Misc. Control unit(s) found.\n", sc->n_mctrl);
|
||||
|
||||
if ((error = agp_generic_attach(dev)))
|
||||
return error;
|
||||
|
||||
sc->initial_aperture = AGP_GET_APERTURE(dev);
|
||||
|
||||
for (;;) {
|
||||
gatt = agp_alloc_gatt(dev);
|
||||
if (gatt)
|
||||
break;
|
||||
|
||||
/*
|
||||
* Probably contigmalloc failure. Try reducing the
|
||||
* aperture so that the gatt size reduces.
|
||||
*/
|
||||
if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
|
||||
agp_generic_detach(dev);
|
||||
return ENOMEM;
|
||||
}
|
||||
}
|
||||
sc->gatt = gatt;
|
||||
|
||||
/* Install the gatt and enable aperture. */
|
||||
for (i = 0; i < sc->n_mctrl; i++) {
|
||||
pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE,
|
||||
(uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK,
|
||||
4);
|
||||
pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
|
||||
(pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) |
|
||||
AGP_AMD64_APCTRL_GARTEN) &
|
||||
~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO),
|
||||
4);
|
||||
}
|
||||
|
||||
agp_flush_cache();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
agp_amd64_detach(device_t dev)
|
||||
{
|
||||
struct agp_amd64_softc *sc = device_get_softc(dev);
|
||||
int i, error;
|
||||
|
||||
if ((error = agp_generic_detach(dev)))
|
||||
return error;
|
||||
|
||||
for (i = 0; i < sc->n_mctrl; i++)
|
||||
pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
|
||||
pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) &
|
||||
~AGP_AMD64_APCTRL_GARTEN, 4);
|
||||
|
||||
AGP_SET_APERTURE(dev, sc->initial_aperture);
|
||||
agp_free_gatt(sc->gatt);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint32_t agp_amd64_table[] = {
|
||||
0x02000000, /* 32 MB */
|
||||
0x04000000, /* 64 MB */
|
||||
0x08000000, /* 128 MB */
|
||||
0x10000000, /* 256 MB */
|
||||
0x20000000, /* 512 MB */
|
||||
0x40000000, /* 1024 MB */
|
||||
0x80000000, /* 2048 MB */
|
||||
};
|
||||
|
||||
#define AGP_AMD64_TABLE_SIZE \
|
||||
(sizeof(agp_amd64_table) / sizeof(agp_amd64_table[0]))
|
||||
|
||||
static uint32_t
|
||||
agp_amd64_get_aperture(device_t dev)
|
||||
{
|
||||
struct agp_amd64_softc *sc = device_get_softc(dev);
|
||||
uint32_t i;
|
||||
|
||||
i = (pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) &
|
||||
AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
|
||||
|
||||
if (i >= AGP_AMD64_TABLE_SIZE)
|
||||
return 0;
|
||||
|
||||
return (agp_amd64_table[i]);
|
||||
}
|
||||
|
||||
static int
|
||||
agp_amd64_set_aperture(device_t dev, uint32_t aperture)
|
||||
{
|
||||
struct agp_amd64_softc *sc = device_get_softc(dev);
|
||||
uint32_t i;
|
||||
int j;
|
||||
|
||||
for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
|
||||
if (agp_amd64_table[i] == aperture)
|
||||
break;
|
||||
if (i == AGP_AMD64_TABLE_SIZE)
|
||||
return EINVAL;
|
||||
|
||||
for (j = 0; j < sc->n_mctrl; j++)
|
||||
pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL,
|
||||
(pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) &
|
||||
~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
agp_amd64_bind_page(device_t dev, int offset, vm_offset_t physical)
|
||||
{
|
||||
struct agp_amd64_softc *sc = device_get_softc(dev);
|
||||
|
||||
if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
|
||||
return EINVAL;
|
||||
|
||||
sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
agp_amd64_unbind_page(device_t dev, int offset)
|
||||
{
|
||||
struct agp_amd64_softc *sc = device_get_softc(dev);
|
||||
|
||||
if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
|
||||
return EINVAL;
|
||||
|
||||
sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
agp_amd64_flush_tlb(device_t dev)
|
||||
{
|
||||
struct agp_amd64_softc *sc = device_get_softc(dev);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < sc->n_mctrl; i++)
|
||||
pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL,
|
||||
pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) |
|
||||
AGP_AMD64_CACHECTRL_INVGART, 4);
|
||||
}
|
||||
|
||||
static device_method_t agp_amd64_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, agp_amd64_probe),
|
||||
DEVMETHOD(device_attach, agp_amd64_attach),
|
||||
DEVMETHOD(device_detach, agp_amd64_detach),
|
||||
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
||||
DEVMETHOD(device_suspend, bus_generic_suspend),
|
||||
DEVMETHOD(device_resume, bus_generic_resume),
|
||||
|
||||
/* AGP interface */
|
||||
DEVMETHOD(agp_get_aperture, agp_amd64_get_aperture),
|
||||
DEVMETHOD(agp_set_aperture, agp_amd64_set_aperture),
|
||||
DEVMETHOD(agp_bind_page, agp_amd64_bind_page),
|
||||
DEVMETHOD(agp_unbind_page, agp_amd64_unbind_page),
|
||||
DEVMETHOD(agp_flush_tlb, agp_amd64_flush_tlb),
|
||||
DEVMETHOD(agp_enable, agp_generic_enable),
|
||||
DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
|
||||
DEVMETHOD(agp_free_memory, agp_generic_free_memory),
|
||||
DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
|
||||
DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
|
||||
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static driver_t agp_amd64_driver = {
|
||||
"agp",
|
||||
agp_amd64_methods,
|
||||
sizeof(struct agp_amd64_softc),
|
||||
};
|
||||
|
||||
static devclass_t agp_devclass;
|
||||
|
||||
DRIVER_MODULE(agp_amd64, pci, agp_amd64_driver, agp_devclass, 0, 0);
|
||||
MODULE_DEPEND(agp_amd64, agp, 1, 1, 1);
|
||||
MODULE_DEPEND(agp_amd64, pci, 1, 1, 1);
|
||||
@ -28,6 +28,7 @@
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include "opt_bus.h"
|
||||
#include "opt_agp.h"
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
@ -105,6 +106,10 @@ agp_sis_match(device_t dev)
|
||||
return ("SiS 746 host to AGP bridge");
|
||||
case 0x07601039:
|
||||
return ("SiS 760 host to AGP bridge");
|
||||
#if defined(__amd64__) || defined(AGP_AMD64_GART)
|
||||
case 0x10221039: /* AMD64 */
|
||||
return NULL;
|
||||
#endif
|
||||
};
|
||||
|
||||
if (pci_get_vendor(dev) == 0x1039)
|
||||
|
||||
@ -28,6 +28,7 @@
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include "opt_bus.h"
|
||||
#include "opt_agp.h"
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
@ -88,7 +89,11 @@ agp_via_match(device_t dev)
|
||||
case 0x06911106:
|
||||
return ("VIA 82C691 (Apollo Pro) host to PCI bridge");
|
||||
case 0x31881106:
|
||||
#if defined(__amd64__) || defined(AGP_AMD64_GART)
|
||||
return NULL;
|
||||
#else
|
||||
return ("VIA 8385 host to PCI bridge");
|
||||
#endif
|
||||
case 0x31891106:
|
||||
return ("VIA 8377 (Apollo KT400/KT400A/KT600) host to PCI bridge");
|
||||
};
|
||||
@ -125,7 +130,9 @@ agp_via_attach(device_t dev)
|
||||
u_int32_t agpsel;
|
||||
|
||||
switch (pci_get_devid(dev)) {
|
||||
#ifdef AGP_NO_AMD64_GART
|
||||
case 0x31881106:
|
||||
#endif
|
||||
case 0x31891106:
|
||||
/* The newer VIA chipsets will select the AGP version based on
|
||||
* what AGP versions the card supports. We still have to
|
||||
|
||||
@ -245,4 +245,21 @@
|
||||
#define AGP_NVIDIA_3_APBASE 0x50
|
||||
#define AGP_NVIDIA_3_APLIMIT 0x54
|
||||
|
||||
/*
|
||||
* AMD64 GART registers
|
||||
*/
|
||||
#define AGP_AMD64_APCTRL 0x90
|
||||
#define AGP_AMD64_APBASE 0x94
|
||||
#define AGP_AMD64_ATTBASE 0x98
|
||||
#define AGP_AMD64_CACHECTRL 0x9c
|
||||
#define AGP_AMD64_APCTRL_GARTEN 0x00000001
|
||||
#define AGP_AMD64_APCTRL_SIZE_MASK 0x0000000e
|
||||
#define AGP_AMD64_APCTRL_DISGARTCPU 0x00000010
|
||||
#define AGP_AMD64_APCTRL_DISGARTIO 0x00000020
|
||||
#define AGP_AMD64_APCTRL_DISWLKPRB 0x00000040
|
||||
#define AGP_AMD64_APBASE_MASK 0x00007fff
|
||||
#define AGP_AMD64_ATTBASE_MASK 0xfffffff0
|
||||
#define AGP_AMD64_CACHECTRL_INVGART 0x00000001
|
||||
#define AGP_AMD64_CACHECTRL_PTEERR 0x00000002
|
||||
|
||||
#endif /* !_PCI_AGPREG_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user