From 3cc771c38b7e03980eed45842d86f096686ac590 Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Fri, 11 Nov 2016 21:01:45 +0000 Subject: [PATCH] Pull in r263169 from upstream llvm trunk (by Tim Northover): AArch64: only try to use scaled fcvt ops on legal vector types. Before we ended up calling getSimpleVectorType on a <3 x float>, which asserted. This fixes an assertion when building the print/ghostscript9-agpl-base port for AArch64. PR: 213865 MFC after: 3 days --- contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 29fbed1b5880..e67a233bbd6b 100644 --- a/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -7581,7 +7581,8 @@ static SDValue performFpToIntCombine(SDNode *N, SelectionDAG &DAG, return SDValue(); SDValue Op = N->getOperand(0); - if (!Op.getValueType().isVector() || Op.getOpcode() != ISD::FMUL) + if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() || + Op.getOpcode() != ISD::FMUL) return SDValue(); SDValue ConstVec = Op->getOperand(1);