Import DTS includes from 4.19
This was missed in r340337 MFC after: 3 days
This commit is contained in:
commit
3dd1a009cd
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=342935
@ -15,6 +15,8 @@
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/* SmartReflex sysc found on 36xx and later */
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#define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26)
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#define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4)
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/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */
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#define SYSC_IDLE_FORCE 0
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#define SYSC_IDLE_NO 1
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|
118
sys/gnu/dts/include/dt-bindings/clock/actions,s700-cmu.h
Normal file
118
sys/gnu/dts/include/dt-bindings/clock/actions,s700-cmu.h
Normal file
@ -0,0 +1,118 @@
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/* SPDX-License-Identifier: GPL-2.0
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*
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* Device Tree binding constants for Actions Semi S700 Clock Management Unit
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*
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* Copyright (c) 2014 Actions Semi Inc.
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* Author: David Liu <liuwei@actions-semi.com>
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*
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* Author: Pathiban Nallathambi <pn@denx.de>
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* Author: Saravanan Sekar <sravanhome@gmail.com>
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*/
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#ifndef __DT_BINDINGS_CLOCK_S700_H
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#define __DT_BINDINGS_CLOCK_S700_H
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#define CLK_NONE 0
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/* pll clocks */
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#define CLK_CORE_PLL 1
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#define CLK_DEV_PLL 2
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#define CLK_DDR_PLL 3
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#define CLK_NAND_PLL 4
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#define CLK_DISPLAY_PLL 5
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#define CLK_TVOUT_PLL 6
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#define CLK_CVBS_PLL 7
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#define CLK_AUDIO_PLL 8
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#define CLK_ETHERNET_PLL 9
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/* system clock */
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#define CLK_CPU 10
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#define CLK_DEV 11
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#define CLK_AHB 12
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#define CLK_APB 13
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#define CLK_DMAC 14
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#define CLK_NOC0_CLK_MUX 15
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#define CLK_NOC1_CLK_MUX 16
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#define CLK_HP_CLK_MUX 17
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#define CLK_HP_CLK_DIV 18
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#define CLK_NOC1_CLK_DIV 19
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#define CLK_NOC0 20
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#define CLK_NOC1 21
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#define CLK_SENOR_SRC 22
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/* peripheral device clock */
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#define CLK_GPIO 23
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#define CLK_TIMER 24
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#define CLK_DSI 25
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#define CLK_CSI 26
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#define CLK_SI 27
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#define CLK_DE 28
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#define CLK_HDE 29
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#define CLK_VDE 30
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#define CLK_VCE 31
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#define CLK_NAND 32
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#define CLK_SD0 33
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#define CLK_SD1 34
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#define CLK_SD2 35
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#define CLK_UART0 36
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#define CLK_UART1 37
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#define CLK_UART2 38
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#define CLK_UART3 39
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#define CLK_UART4 40
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#define CLK_UART5 41
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#define CLK_UART6 42
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#define CLK_PWM0 43
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#define CLK_PWM1 44
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#define CLK_PWM2 45
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#define CLK_PWM3 46
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#define CLK_PWM4 47
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#define CLK_PWM5 48
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#define CLK_GPU3D 49
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#define CLK_I2C0 50
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#define CLK_I2C1 51
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#define CLK_I2C2 52
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#define CLK_I2C3 53
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#define CLK_SPI0 54
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#define CLK_SPI1 55
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#define CLK_SPI2 56
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#define CLK_SPI3 57
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#define CLK_USB3_480MPLL0 58
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#define CLK_USB3_480MPHY0 59
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#define CLK_USB3_5GPHY 60
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#define CLK_USB3_CCE 61
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#define CLK_USB3_MAC 62
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#define CLK_LCD 63
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#define CLK_HDMI_AUDIO 64
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#define CLK_I2SRX 65
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#define CLK_I2STX 66
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#define CLK_SENSOR0 67
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#define CLK_SENSOR1 68
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#define CLK_HDMI_DEV 69
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#define CLK_ETHERNET 70
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#define CLK_RMII_REF 71
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#define CLK_USB2H0_PLLEN 72
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#define CLK_USB2H0_PHY 73
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#define CLK_USB2H0_CCE 74
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#define CLK_USB2H1_PLLEN 75
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#define CLK_USB2H1_PHY 76
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#define CLK_USB2H1_CCE 77
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#define CLK_TVOUT 78
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#define CLK_THERMAL_SENSOR 79
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#define CLK_IRC_SWITCH 80
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#define CLK_PCM1 81
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#define CLK_NR_CLKS (CLK_PCM1 + 1)
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#endif /* __DT_BINDINGS_CLOCK_S700_H */
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@ -25,7 +25,7 @@
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#define ASPEED_CLK_GATE_RSACLK 19
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#define ASPEED_CLK_GATE_UART3CLK 20
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#define ASPEED_CLK_GATE_UART4CLK 21
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#define ASPEED_CLK_GATE_SDCLKCLK 22
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#define ASPEED_CLK_GATE_SDCLK 22
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#define ASPEED_CLK_GATE_LHCCLK 23
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#define ASPEED_CLK_HPLL 24
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#define ASPEED_CLK_AHB 25
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|
94
sys/gnu/dts/include/dt-bindings/clock/axg-audio-clkc.h
Normal file
94
sys/gnu/dts/include/dt-bindings/clock/axg-audio-clkc.h
Normal file
@ -0,0 +1,94 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Copyright (c) 2018 Baylibre SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
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#define __AXG_AUDIO_CLKC_BINDINGS_H
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#define AUD_CLKID_SLV_SCLK0 9
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#define AUD_CLKID_SLV_SCLK1 10
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#define AUD_CLKID_SLV_SCLK2 11
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#define AUD_CLKID_SLV_SCLK3 12
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#define AUD_CLKID_SLV_SCLK4 13
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#define AUD_CLKID_SLV_SCLK5 14
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#define AUD_CLKID_SLV_SCLK6 15
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#define AUD_CLKID_SLV_SCLK7 16
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#define AUD_CLKID_SLV_SCLK8 17
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#define AUD_CLKID_SLV_SCLK9 18
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#define AUD_CLKID_SLV_LRCLK0 19
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#define AUD_CLKID_SLV_LRCLK1 20
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#define AUD_CLKID_SLV_LRCLK2 21
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#define AUD_CLKID_SLV_LRCLK3 22
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#define AUD_CLKID_SLV_LRCLK4 23
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#define AUD_CLKID_SLV_LRCLK5 24
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#define AUD_CLKID_SLV_LRCLK6 25
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#define AUD_CLKID_SLV_LRCLK7 26
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#define AUD_CLKID_SLV_LRCLK8 27
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#define AUD_CLKID_SLV_LRCLK9 28
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#define AUD_CLKID_DDR_ARB 29
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#define AUD_CLKID_PDM 30
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#define AUD_CLKID_TDMIN_A 31
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#define AUD_CLKID_TDMIN_B 32
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#define AUD_CLKID_TDMIN_C 33
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#define AUD_CLKID_TDMIN_LB 34
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#define AUD_CLKID_TDMOUT_A 35
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#define AUD_CLKID_TDMOUT_B 36
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#define AUD_CLKID_TDMOUT_C 37
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#define AUD_CLKID_FRDDR_A 38
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#define AUD_CLKID_FRDDR_B 39
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#define AUD_CLKID_FRDDR_C 40
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#define AUD_CLKID_TODDR_A 41
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#define AUD_CLKID_TODDR_B 42
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#define AUD_CLKID_TODDR_C 43
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#define AUD_CLKID_LOOPBACK 44
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#define AUD_CLKID_SPDIFIN 45
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#define AUD_CLKID_SPDIFOUT 46
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#define AUD_CLKID_RESAMPLE 47
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#define AUD_CLKID_POWER_DETECT 48
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#define AUD_CLKID_MST_A_MCLK 49
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#define AUD_CLKID_MST_B_MCLK 50
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#define AUD_CLKID_MST_C_MCLK 51
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#define AUD_CLKID_MST_D_MCLK 52
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#define AUD_CLKID_MST_E_MCLK 53
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#define AUD_CLKID_MST_F_MCLK 54
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#define AUD_CLKID_SPDIFOUT_CLK 55
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#define AUD_CLKID_SPDIFIN_CLK 56
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#define AUD_CLKID_PDM_DCLK 57
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#define AUD_CLKID_PDM_SYSCLK 58
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#define AUD_CLKID_MST_A_SCLK 79
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#define AUD_CLKID_MST_B_SCLK 80
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#define AUD_CLKID_MST_C_SCLK 81
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#define AUD_CLKID_MST_D_SCLK 82
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#define AUD_CLKID_MST_E_SCLK 83
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#define AUD_CLKID_MST_F_SCLK 84
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#define AUD_CLKID_MST_A_LRCLK 86
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#define AUD_CLKID_MST_B_LRCLK 87
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#define AUD_CLKID_MST_C_LRCLK 88
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#define AUD_CLKID_MST_D_LRCLK 89
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#define AUD_CLKID_MST_E_LRCLK 90
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#define AUD_CLKID_MST_F_LRCLK 91
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#define AUD_CLKID_TDMIN_A_SCLK_SEL 116
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#define AUD_CLKID_TDMIN_B_SCLK_SEL 117
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#define AUD_CLKID_TDMIN_C_SCLK_SEL 118
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#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119
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#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120
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#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121
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#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122
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#define AUD_CLKID_TDMIN_A_SCLK 123
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#define AUD_CLKID_TDMIN_B_SCLK 124
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#define AUD_CLKID_TDMIN_C_SCLK 125
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#define AUD_CLKID_TDMIN_LB_SCLK 126
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#define AUD_CLKID_TDMOUT_A_SCLK 127
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#define AUD_CLKID_TDMOUT_B_SCLK 128
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#define AUD_CLKID_TDMOUT_C_SCLK 129
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#define AUD_CLKID_TDMIN_A_LRCLK 130
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#define AUD_CLKID_TDMIN_B_LRCLK 131
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#define AUD_CLKID_TDMIN_C_LRCLK 132
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#define AUD_CLKID_TDMIN_LB_LRCLK 133
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#define AUD_CLKID_TDMOUT_A_LRCLK 134
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#define AUD_CLKID_TDMOUT_B_LRCLK 135
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#define AUD_CLKID_TDMOUT_C_LRCLK 136
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#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
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@ -68,5 +68,9 @@
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#define CLKID_SD_EMMC_B_CLK0 59
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#define CLKID_SD_EMMC_C_CLK0 60
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#define CLKID_HIFI_PLL 69
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#define CLKID_PCIE_CML_EN0 79
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#define CLKID_PCIE_CML_EN1 80
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#define CLKID_MIPI_ENABLE 81
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#define CLKID_GEN_CLK 84
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#endif /* __AXG_CLKC_H */
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@ -168,5 +168,6 @@
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#define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
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#define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
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#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
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#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
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#endif
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@ -1,44 +0,0 @@
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/*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* Author: Andrzej Hajda <a.hajda@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Device Tree binding constants for Exynos5440 clock controller.
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*/
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5440_H
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#define _DT_BINDINGS_CLOCK_EXYNOS_5440_H
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#define CLK_XTAL 1
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#define CLK_ARM_CLK 2
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#define CLK_CPLLA 3
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#define CLK_CPLLB 4
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#define CLK_SPI_BAUD 16
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#define CLK_PB0_250 17
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#define CLK_PR0_250 18
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#define CLK_PR1_250 19
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#define CLK_B_250 20
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#define CLK_B_125 21
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#define CLK_B_200 22
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#define CLK_SATA 23
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#define CLK_USB 24
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#define CLK_GMAC0 25
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#define CLK_CS250 26
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#define CLK_PB0_250_O 27
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#define CLK_PR0_250_O 28
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#define CLK_PR1_250_O 29
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#define CLK_B_250_O 30
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#define CLK_B_125_O 31
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#define CLK_B_200_O 32
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#define CLK_SATA_O 33
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#define CLK_USB_O 34
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#define CLK_GMAC0_O 35
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#define CLK_CS250_O 36
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/* must be greater than maximal clock id */
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#define CLK_NR_CLKS 37
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5440_H */
|
@ -127,5 +127,6 @@
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#define CLKID_VAPB 140
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#define CLKID_VDEC_1 153
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#define CLKID_VDEC_HEVC 156
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#define CLKID_GEN_CLK 159
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#endif /* __GXBB_CLKC_H */
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|
@ -197,6 +197,13 @@
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#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171
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#define IMX6SLL_CLK_EXTERN_AUDIO 172
|
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#define IMX6SLL_CLK_END 173
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#define IMX6SLL_CLK_GPIO1 173
|
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#define IMX6SLL_CLK_GPIO2 174
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#define IMX6SLL_CLK_GPIO3 175
|
||||
#define IMX6SLL_CLK_GPIO4 176
|
||||
#define IMX6SLL_CLK_GPIO5 177
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#define IMX6SLL_CLK_GPIO6 178
|
||||
|
||||
#define IMX6SLL_CLK_END 179
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */
|
||||
|
@ -254,6 +254,12 @@
|
||||
#define IMX6UL_CLK_CKO2_PODF 241
|
||||
#define IMX6UL_CLK_CKO2 242
|
||||
#define IMX6UL_CLK_CKO 243
|
||||
#define IMX6UL_CLK_END 244
|
||||
#define IMX6UL_CLK_GPIO1 244
|
||||
#define IMX6UL_CLK_GPIO2 245
|
||||
#define IMX6UL_CLK_GPIO3 246
|
||||
#define IMX6UL_CLK_GPIO4 247
|
||||
#define IMX6UL_CLK_GPIO5 248
|
||||
|
||||
#define IMX6UL_CLK_END 249
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
|
||||
|
18
sys/gnu/dts/include/dt-bindings/clock/maxim,max9485.h
Normal file
18
sys/gnu/dts/include/dt-bindings/clock/maxim,max9485.h
Normal file
@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Daniel Mack
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_MAX9485_CLK_H
|
||||
#define __DT_BINDINGS_MAX9485_CLK_H
|
||||
|
||||
#define MAX9485_MCLKOUT 0
|
||||
#define MAX9485_CLKOUT 1
|
||||
#define MAX9485_CLKOUT1 2
|
||||
#define MAX9485_CLKOUT2 3
|
||||
|
||||
#endif /* __DT_BINDINGS_MAX9485_CLK_H */
|
389
sys/gnu/dts/include/dt-bindings/clock/px30-cru.h
Normal file
389
sys/gnu/dts/include/dt-bindings/clock/px30-cru.h
Normal file
@ -0,0 +1,389 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
|
||||
|
||||
/* core clocks */
|
||||
#define PLL_APLL 1
|
||||
#define PLL_DPLL 2
|
||||
#define PLL_CPLL 3
|
||||
#define PLL_NPLL 4
|
||||
#define APLL_BOOST_H 5
|
||||
#define APLL_BOOST_L 6
|
||||
#define ARMCLK 7
|
||||
|
||||
/* sclk gates (special clocks) */
|
||||
#define USB480M 14
|
||||
#define SCLK_PDM 15
|
||||
#define SCLK_I2S0_TX 16
|
||||
#define SCLK_I2S0_TX_OUT 17
|
||||
#define SCLK_I2S0_RX 18
|
||||
#define SCLK_I2S0_RX_OUT 19
|
||||
#define SCLK_I2S1 20
|
||||
#define SCLK_I2S1_OUT 21
|
||||
#define SCLK_I2S2 22
|
||||
#define SCLK_I2S2_OUT 23
|
||||
#define SCLK_UART1 24
|
||||
#define SCLK_UART2 25
|
||||
#define SCLK_UART3 26
|
||||
#define SCLK_UART4 27
|
||||
#define SCLK_UART5 28
|
||||
#define SCLK_I2C0 29
|
||||
#define SCLK_I2C1 30
|
||||
#define SCLK_I2C2 31
|
||||
#define SCLK_I2C3 32
|
||||
#define SCLK_I2C4 33
|
||||
#define SCLK_PWM0 34
|
||||
#define SCLK_PWM1 35
|
||||
#define SCLK_SPI0 36
|
||||
#define SCLK_SPI1 37
|
||||
#define SCLK_TIMER0 38
|
||||
#define SCLK_TIMER1 39
|
||||
#define SCLK_TIMER2 40
|
||||
#define SCLK_TIMER3 41
|
||||
#define SCLK_TIMER4 42
|
||||
#define SCLK_TIMER5 43
|
||||
#define SCLK_TSADC 44
|
||||
#define SCLK_SARADC 45
|
||||
#define SCLK_OTP 46
|
||||
#define SCLK_OTP_USR 47
|
||||
#define SCLK_CRYPTO 48
|
||||
#define SCLK_CRYPTO_APK 49
|
||||
#define SCLK_DDRC 50
|
||||
#define SCLK_ISP 51
|
||||
#define SCLK_CIF_OUT 52
|
||||
#define SCLK_RGA_CORE 53
|
||||
#define SCLK_VOPB_PWM 54
|
||||
#define SCLK_NANDC 55
|
||||
#define SCLK_SDIO 56
|
||||
#define SCLK_EMMC 57
|
||||
#define SCLK_SFC 58
|
||||
#define SCLK_SDMMC 59
|
||||
#define SCLK_OTG_ADP 60
|
||||
#define SCLK_GMAC_SRC 61
|
||||
#define SCLK_GMAC 62
|
||||
#define SCLK_GMAC_RX_TX 63
|
||||
#define SCLK_MAC_REF 64
|
||||
#define SCLK_MAC_REFOUT 65
|
||||
#define SCLK_MAC_OUT 66
|
||||
#define SCLK_SDMMC_DRV 67
|
||||
#define SCLK_SDMMC_SAMPLE 68
|
||||
#define SCLK_SDIO_DRV 69
|
||||
#define SCLK_SDIO_SAMPLE 70
|
||||
#define SCLK_EMMC_DRV 71
|
||||
#define SCLK_EMMC_SAMPLE 72
|
||||
#define SCLK_GPU 73
|
||||
#define SCLK_PVTM 74
|
||||
#define SCLK_CORE_VPU 75
|
||||
#define SCLK_GMAC_RMII 76
|
||||
#define SCLK_UART2_SRC 77
|
||||
#define SCLK_NANDC_DIV 78
|
||||
#define SCLK_NANDC_DIV50 79
|
||||
#define SCLK_SDIO_DIV 80
|
||||
#define SCLK_SDIO_DIV50 81
|
||||
#define SCLK_EMMC_DIV 82
|
||||
#define SCLK_EMMC_DIV50 83
|
||||
#define SCLK_DDRCLK 84
|
||||
#define SCLK_UART1_SRC 85
|
||||
|
||||
/* dclk gates */
|
||||
#define DCLK_VOPB 150
|
||||
#define DCLK_VOPL 151
|
||||
|
||||
/* aclk gates */
|
||||
#define ACLK_GPU 170
|
||||
#define ACLK_BUS_PRE 171
|
||||
#define ACLK_CRYPTO 172
|
||||
#define ACLK_VI_PRE 173
|
||||
#define ACLK_VO_PRE 174
|
||||
#define ACLK_VPU 175
|
||||
#define ACLK_PERI_PRE 176
|
||||
#define ACLK_GMAC 178
|
||||
#define ACLK_CIF 179
|
||||
#define ACLK_ISP 180
|
||||
#define ACLK_VOPB 181
|
||||
#define ACLK_VOPL 182
|
||||
#define ACLK_RGA 183
|
||||
#define ACLK_GIC 184
|
||||
#define ACLK_DCF 186
|
||||
#define ACLK_DMAC 187
|
||||
#define ACLK_BUS_SRC 188
|
||||
#define ACLK_PERI_SRC 189
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_BUS_PRE 240
|
||||
#define HCLK_CRYPTO 241
|
||||
#define HCLK_VI_PRE 242
|
||||
#define HCLK_VO_PRE 243
|
||||
#define HCLK_VPU 244
|
||||
#define HCLK_PERI_PRE 245
|
||||
#define HCLK_MMC_NAND 246
|
||||
#define HCLK_SDMMC 247
|
||||
#define HCLK_USB 248
|
||||
#define HCLK_CIF 249
|
||||
#define HCLK_ISP 250
|
||||
#define HCLK_VOPB 251
|
||||
#define HCLK_VOPL 252
|
||||
#define HCLK_RGA 253
|
||||
#define HCLK_NANDC 254
|
||||
#define HCLK_SDIO 255
|
||||
#define HCLK_EMMC 256
|
||||
#define HCLK_SFC 257
|
||||
#define HCLK_OTG 258
|
||||
#define HCLK_HOST 259
|
||||
#define HCLK_HOST_ARB 260
|
||||
#define HCLK_PDM 261
|
||||
#define HCLK_I2S0 262
|
||||
#define HCLK_I2S1 263
|
||||
#define HCLK_I2S2 264
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_BUS_PRE 320
|
||||
#define PCLK_DDR 321
|
||||
#define PCLK_VO_PRE 322
|
||||
#define PCLK_GMAC 323
|
||||
#define PCLK_MIPI_DSI 324
|
||||
#define PCLK_MIPIDSIPHY 325
|
||||
#define PCLK_MIPICSIPHY 326
|
||||
#define PCLK_USB_GRF 327
|
||||
#define PCLK_DCF 328
|
||||
#define PCLK_UART1 329
|
||||
#define PCLK_UART2 330
|
||||
#define PCLK_UART3 331
|
||||
#define PCLK_UART4 332
|
||||
#define PCLK_UART5 333
|
||||
#define PCLK_I2C0 334
|
||||
#define PCLK_I2C1 335
|
||||
#define PCLK_I2C2 336
|
||||
#define PCLK_I2C3 337
|
||||
#define PCLK_I2C4 338
|
||||
#define PCLK_PWM0 339
|
||||
#define PCLK_PWM1 340
|
||||
#define PCLK_SPI0 341
|
||||
#define PCLK_SPI1 342
|
||||
#define PCLK_SARADC 343
|
||||
#define PCLK_TSADC 344
|
||||
#define PCLK_TIMER 345
|
||||
#define PCLK_OTP_NS 346
|
||||
#define PCLK_WDT_NS 347
|
||||
#define PCLK_GPIO1 348
|
||||
#define PCLK_GPIO2 349
|
||||
#define PCLK_GPIO3 350
|
||||
#define PCLK_ISP 351
|
||||
#define PCLK_CIF 352
|
||||
#define PCLK_OTP_PHY 353
|
||||
|
||||
#define CLK_NR_CLKS (PCLK_OTP_PHY + 1)
|
||||
|
||||
/* pmu-clocks indices */
|
||||
|
||||
#define PLL_GPLL 1
|
||||
|
||||
#define SCLK_RTC32K_PMU 4
|
||||
#define SCLK_WIFI_PMU 5
|
||||
#define SCLK_UART0_PMU 6
|
||||
#define SCLK_PVTM_PMU 7
|
||||
#define PCLK_PMU_PRE 8
|
||||
#define SCLK_REF24M_PMU 9
|
||||
#define SCLK_USBPHY_REF 10
|
||||
#define SCLK_MIPIDSIPHY_REF 11
|
||||
|
||||
#define XIN24M_DIV 12
|
||||
|
||||
#define PCLK_GPIO0_PMU 20
|
||||
#define PCLK_UART0_PMU 21
|
||||
|
||||
#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_CORE0_PO 0
|
||||
#define SRST_CORE1_PO 1
|
||||
#define SRST_CORE2_PO 2
|
||||
#define SRST_CORE3_PO 3
|
||||
#define SRST_CORE0 4
|
||||
#define SRST_CORE1 5
|
||||
#define SRST_CORE2 6
|
||||
#define SRST_CORE3 7
|
||||
#define SRST_CORE0_DBG 8
|
||||
#define SRST_CORE1_DBG 9
|
||||
#define SRST_CORE2_DBG 10
|
||||
#define SRST_CORE3_DBG 11
|
||||
#define SRST_TOPDBG 12
|
||||
#define SRST_CORE_NOC 13
|
||||
#define SRST_STRC_A 14
|
||||
#define SRST_L2C 15
|
||||
|
||||
#define SRST_DAP 16
|
||||
#define SRST_CORE_PVTM 17
|
||||
#define SRST_GPU 18
|
||||
#define SRST_GPU_NIU 19
|
||||
#define SRST_UPCTL2 20
|
||||
#define SRST_UPCTL2_A 21
|
||||
#define SRST_UPCTL2_P 22
|
||||
#define SRST_MSCH 23
|
||||
#define SRST_MSCH_P 24
|
||||
#define SRST_DDRMON_P 25
|
||||
#define SRST_DDRSTDBY_P 26
|
||||
#define SRST_DDRSTDBY 27
|
||||
#define SRST_DDRGRF_p 28
|
||||
#define SRST_AXI_SPLIT_A 29
|
||||
#define SRST_AXI_CMD_A 30
|
||||
#define SRST_AXI_CMD_P 31
|
||||
|
||||
#define SRST_DDRPHY 32
|
||||
#define SRST_DDRPHYDIV 33
|
||||
#define SRST_DDRPHY_P 34
|
||||
#define SRST_VPU_A 36
|
||||
#define SRST_VPU_NIU_A 37
|
||||
#define SRST_VPU_H 38
|
||||
#define SRST_VPU_NIU_H 39
|
||||
#define SRST_VI_NIU_A 40
|
||||
#define SRST_VI_NIU_H 41
|
||||
#define SRST_ISP_H 42
|
||||
#define SRST_ISP 43
|
||||
#define SRST_CIF_A 44
|
||||
#define SRST_CIF_H 45
|
||||
#define SRST_CIF_PCLKIN 46
|
||||
#define SRST_MIPICSIPHY_P 47
|
||||
|
||||
#define SRST_VO_NIU_A 48
|
||||
#define SRST_VO_NIU_H 49
|
||||
#define SRST_VO_NIU_P 50
|
||||
#define SRST_VOPB_A 51
|
||||
#define SRST_VOPB_H 52
|
||||
#define SRST_VOPB 53
|
||||
#define SRST_PWM_VOPB 54
|
||||
#define SRST_VOPL_A 55
|
||||
#define SRST_VOPL_H 56
|
||||
#define SRST_VOPL 57
|
||||
#define SRST_RGA_A 58
|
||||
#define SRST_RGA_H 59
|
||||
#define SRST_RGA 60
|
||||
#define SRST_MIPIDSI_HOST_P 61
|
||||
#define SRST_MIPIDSIPHY_P 62
|
||||
#define SRST_VPU_CORE 63
|
||||
|
||||
#define SRST_PERI_NIU_A 64
|
||||
#define SRST_USB_NIU_H 65
|
||||
#define SRST_USB2OTG_H 66
|
||||
#define SRST_USB2OTG 67
|
||||
#define SRST_USB2OTG_ADP 68
|
||||
#define SRST_USB2HOST_H 69
|
||||
#define SRST_USB2HOST_ARB_H 70
|
||||
#define SRST_USB2HOST_AUX_H 71
|
||||
#define SRST_USB2HOST_EHCI 72
|
||||
#define SRST_USB2HOST 73
|
||||
#define SRST_USBPHYPOR 74
|
||||
#define SRST_USBPHY_OTG_PORT 75
|
||||
#define SRST_USBPHY_HOST_PORT 76
|
||||
#define SRST_USBPHY_GRF 77
|
||||
#define SRST_CPU_BOOST_P 78
|
||||
#define SRST_CPU_BOOST 79
|
||||
|
||||
#define SRST_MMC_NAND_NIU_H 80
|
||||
#define SRST_SDIO_H 81
|
||||
#define SRST_EMMC_H 82
|
||||
#define SRST_SFC_H 83
|
||||
#define SRST_SFC 84
|
||||
#define SRST_SDCARD_NIU_H 85
|
||||
#define SRST_SDMMC_H 86
|
||||
#define SRST_NANDC_H 89
|
||||
#define SRST_NANDC 90
|
||||
#define SRST_GMAC_NIU_A 92
|
||||
#define SRST_GMAC_NIU_P 93
|
||||
#define SRST_GMAC_A 94
|
||||
|
||||
#define SRST_PMU_NIU_P 96
|
||||
#define SRST_PMU_SGRF_P 97
|
||||
#define SRST_PMU_GRF_P 98
|
||||
#define SRST_PMU 99
|
||||
#define SRST_PMU_MEM_P 100
|
||||
#define SRST_PMU_GPIO0_P 101
|
||||
#define SRST_PMU_UART0_P 102
|
||||
#define SRST_PMU_CRU_P 103
|
||||
#define SRST_PMU_PVTM 104
|
||||
#define SRST_PMU_UART 105
|
||||
#define SRST_PMU_NIU_H 106
|
||||
#define SRST_PMU_DDR_FAIL_SAVE 107
|
||||
#define SRST_PMU_CORE_PERF_A 108
|
||||
#define SRST_PMU_CORE_GRF_P 109
|
||||
#define SRST_PMU_GPU_PERF_A 110
|
||||
#define SRST_PMU_GPU_GRF_P 111
|
||||
|
||||
#define SRST_CRYPTO_NIU_A 112
|
||||
#define SRST_CRYPTO_NIU_H 113
|
||||
#define SRST_CRYPTO_A 114
|
||||
#define SRST_CRYPTO_H 115
|
||||
#define SRST_CRYPTO 116
|
||||
#define SRST_CRYPTO_APK 117
|
||||
#define SRST_BUS_NIU_H 120
|
||||
#define SRST_USB_NIU_P 121
|
||||
#define SRST_BUS_TOP_NIU_P 122
|
||||
#define SRST_INTMEM_A 123
|
||||
#define SRST_GIC_A 124
|
||||
#define SRST_ROM_H 126
|
||||
#define SRST_DCF_A 127
|
||||
|
||||
#define SRST_DCF_P 128
|
||||
#define SRST_PDM_H 129
|
||||
#define SRST_PDM 130
|
||||
#define SRST_I2S0_H 131
|
||||
#define SRST_I2S0_TX 132
|
||||
#define SRST_I2S1_H 133
|
||||
#define SRST_I2S1 134
|
||||
#define SRST_I2S2_H 135
|
||||
#define SRST_I2S2 136
|
||||
#define SRST_UART1_P 137
|
||||
#define SRST_UART1 138
|
||||
#define SRST_UART2_P 139
|
||||
#define SRST_UART2 140
|
||||
#define SRST_UART3_P 141
|
||||
#define SRST_UART3 142
|
||||
#define SRST_UART4_P 143
|
||||
|
||||
#define SRST_UART4 144
|
||||
#define SRST_UART5_P 145
|
||||
#define SRST_UART5 146
|
||||
#define SRST_I2C0_P 147
|
||||
#define SRST_I2C0 148
|
||||
#define SRST_I2C1_P 149
|
||||
#define SRST_I2C1 150
|
||||
#define SRST_I2C2_P 151
|
||||
#define SRST_I2C2 152
|
||||
#define SRST_I2C3_P 153
|
||||
#define SRST_I2C3 154
|
||||
#define SRST_PWM0_P 157
|
||||
#define SRST_PWM0 158
|
||||
#define SRST_PWM1_P 159
|
||||
|
||||
#define SRST_PWM1 160
|
||||
#define SRST_SPI0_P 161
|
||||
#define SRST_SPI0 162
|
||||
#define SRST_SPI1_P 163
|
||||
#define SRST_SPI1 164
|
||||
#define SRST_SARADC_P 165
|
||||
#define SRST_SARADC 166
|
||||
#define SRST_TSADC_P 167
|
||||
#define SRST_TSADC 168
|
||||
#define SRST_TIMER_P 169
|
||||
#define SRST_TIMER0 170
|
||||
#define SRST_TIMER1 171
|
||||
#define SRST_TIMER2 172
|
||||
#define SRST_TIMER3 173
|
||||
#define SRST_TIMER4 174
|
||||
#define SRST_TIMER5 175
|
||||
|
||||
#define SRST_OTP_NS_P 176
|
||||
#define SRST_OTP_NS_SBPI 177
|
||||
#define SRST_OTP_NS_USR 178
|
||||
#define SRST_OTP_PHY_P 179
|
||||
#define SRST_OTP_PHY 180
|
||||
#define SRST_WDT_NS_P 181
|
||||
#define SRST_GPIO1_P 182
|
||||
#define SRST_GPIO2_P 183
|
||||
#define SRST_GPIO3_P 184
|
||||
#define SRST_SGRF_P 185
|
||||
#define SRST_GRF_P 186
|
||||
#define SRST_I2S0_RX 191
|
||||
|
||||
#endif
|
@ -72,6 +72,7 @@
|
||||
#define CLK_USIM 58
|
||||
#define CLK_USIM1 59
|
||||
#define CLK_USMI0 60
|
||||
#define CLK_MAX 61
|
||||
#define CLK_OSC32k768 61
|
||||
#define CLK_MAX 62
|
||||
|
||||
#endif
|
||||
|
45
sys/gnu/dts/include/dt-bindings/clock/qcom,dispcc-sdm845.h
Normal file
45
sys/gnu/dts/include/dt-bindings/clock/qcom,dispcc-sdm845.h
Normal file
@ -0,0 +1,45 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
|
||||
#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
|
||||
|
||||
/* DISP_CC clock registers */
|
||||
#define DISP_CC_MDSS_AHB_CLK 0
|
||||
#define DISP_CC_MDSS_AXI_CLK 1
|
||||
#define DISP_CC_MDSS_BYTE0_CLK 2
|
||||
#define DISP_CC_MDSS_BYTE0_CLK_SRC 3
|
||||
#define DISP_CC_MDSS_BYTE0_INTF_CLK 4
|
||||
#define DISP_CC_MDSS_BYTE1_CLK 5
|
||||
#define DISP_CC_MDSS_BYTE1_CLK_SRC 6
|
||||
#define DISP_CC_MDSS_BYTE1_INTF_CLK 7
|
||||
#define DISP_CC_MDSS_ESC0_CLK 8
|
||||
#define DISP_CC_MDSS_ESC0_CLK_SRC 9
|
||||
#define DISP_CC_MDSS_ESC1_CLK 10
|
||||
#define DISP_CC_MDSS_ESC1_CLK_SRC 11
|
||||
#define DISP_CC_MDSS_MDP_CLK 12
|
||||
#define DISP_CC_MDSS_MDP_CLK_SRC 13
|
||||
#define DISP_CC_MDSS_MDP_LUT_CLK 14
|
||||
#define DISP_CC_MDSS_PCLK0_CLK 15
|
||||
#define DISP_CC_MDSS_PCLK0_CLK_SRC 16
|
||||
#define DISP_CC_MDSS_PCLK1_CLK 17
|
||||
#define DISP_CC_MDSS_PCLK1_CLK_SRC 18
|
||||
#define DISP_CC_MDSS_ROT_CLK 19
|
||||
#define DISP_CC_MDSS_ROT_CLK_SRC 20
|
||||
#define DISP_CC_MDSS_RSCC_AHB_CLK 21
|
||||
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 22
|
||||
#define DISP_CC_MDSS_VSYNC_CLK 23
|
||||
#define DISP_CC_MDSS_VSYNC_CLK_SRC 24
|
||||
#define DISP_CC_PLL0 25
|
||||
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26
|
||||
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27
|
||||
|
||||
/* DISP_CC Reset */
|
||||
#define DISP_CC_MDSS_RSCC_BCR 0
|
||||
|
||||
/* DISP_CC GDSCR */
|
||||
#define MDSS_GDSC 0
|
||||
|
||||
#endif
|
@ -192,6 +192,8 @@
|
||||
#define GCC_VS_CTRL_CLK_SRC 182
|
||||
#define GCC_VSENSOR_CLK_SRC 183
|
||||
#define GPLL4 184
|
||||
#define GCC_CPUSS_DVM_BUS_CLK 185
|
||||
#define GCC_CPUSS_GNOC_CLK 186
|
||||
|
||||
/* GCC Resets */
|
||||
#define GCC_MMSS_BCR 0
|
||||
|
148
sys/gnu/dts/include/dt-bindings/clock/r9a06g032-sysctrl.h
Normal file
148
sys/gnu/dts/include/dt-bindings/clock/r9a06g032-sysctrl.h
Normal file
@ -0,0 +1,148 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* R9A06G032 sysctrl IDs
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Europe Limited
|
||||
*
|
||||
* Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__
|
||||
#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__
|
||||
|
||||
#define R9A06G032_CLK_PLL_USB 1
|
||||
#define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */
|
||||
#define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */
|
||||
#define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */
|
||||
#define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */
|
||||
#define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */
|
||||
#define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */
|
||||
#define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */
|
||||
#define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */
|
||||
#define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */
|
||||
#define R9A06G032_CLK_25_PG4 26
|
||||
#define R9A06G032_CLK_25_PG5 27
|
||||
#define R9A06G032_CLK_25_PG6 28
|
||||
#define R9A06G032_CLK_25_PG7 29
|
||||
#define R9A06G032_CLK_25_PG8 30
|
||||
#define R9A06G032_CLK_ADC 31
|
||||
#define R9A06G032_CLK_ECAT100 32
|
||||
#define R9A06G032_CLK_HSR100 33
|
||||
#define R9A06G032_CLK_I2C0 34
|
||||
#define R9A06G032_CLK_I2C1 35
|
||||
#define R9A06G032_CLK_MII_REF 36
|
||||
#define R9A06G032_CLK_NAND 37
|
||||
#define R9A06G032_CLK_NOUSBP2_PG6 38
|
||||
#define R9A06G032_CLK_P1_PG2 39
|
||||
#define R9A06G032_CLK_P1_PG3 40
|
||||
#define R9A06G032_CLK_P1_PG4 41
|
||||
#define R9A06G032_CLK_P4_PG3 42
|
||||
#define R9A06G032_CLK_P4_PG4 43
|
||||
#define R9A06G032_CLK_P6_PG1 44
|
||||
#define R9A06G032_CLK_P6_PG2 45
|
||||
#define R9A06G032_CLK_P6_PG3 46
|
||||
#define R9A06G032_CLK_P6_PG4 47
|
||||
#define R9A06G032_CLK_PCI_USB 48
|
||||
#define R9A06G032_CLK_QSPI0 49
|
||||
#define R9A06G032_CLK_QSPI1 50
|
||||
#define R9A06G032_CLK_RGMII_REF 51
|
||||
#define R9A06G032_CLK_RMII_REF 52
|
||||
#define R9A06G032_CLK_SDIO0 53
|
||||
#define R9A06G032_CLK_SDIO1 54
|
||||
#define R9A06G032_CLK_SERCOS100 55
|
||||
#define R9A06G032_CLK_SLCD 56
|
||||
#define R9A06G032_CLK_SPI0 57
|
||||
#define R9A06G032_CLK_SPI1 58
|
||||
#define R9A06G032_CLK_SPI2 59
|
||||
#define R9A06G032_CLK_SPI3 60
|
||||
#define R9A06G032_CLK_SPI4 61
|
||||
#define R9A06G032_CLK_SPI5 62
|
||||
#define R9A06G032_CLK_SWITCH 63
|
||||
#define R9A06G032_HCLK_ECAT125 65
|
||||
#define R9A06G032_HCLK_PINCONFIG 66
|
||||
#define R9A06G032_HCLK_SERCOS 67
|
||||
#define R9A06G032_HCLK_SGPIO2 68
|
||||
#define R9A06G032_HCLK_SGPIO3 69
|
||||
#define R9A06G032_HCLK_SGPIO4 70
|
||||
#define R9A06G032_HCLK_TIMER0 71
|
||||
#define R9A06G032_HCLK_TIMER1 72
|
||||
#define R9A06G032_HCLK_USBF 73
|
||||
#define R9A06G032_HCLK_USBH 74
|
||||
#define R9A06G032_HCLK_USBPM 75
|
||||
#define R9A06G032_CLK_48_PG_F 76
|
||||
#define R9A06G032_CLK_48_PG4 77
|
||||
#define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */
|
||||
#define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */
|
||||
#define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */
|
||||
#define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */
|
||||
#define R9A06G032_HCLK_CAN0 85
|
||||
#define R9A06G032_HCLK_CAN1 86
|
||||
#define R9A06G032_HCLK_DELTASIGMA 87
|
||||
#define R9A06G032_HCLK_PWMPTO 88
|
||||
#define R9A06G032_HCLK_RSV 89
|
||||
#define R9A06G032_HCLK_SGPIO0 90
|
||||
#define R9A06G032_HCLK_SGPIO1 91
|
||||
#define R9A06G032_RTOS_MDC 92
|
||||
#define R9A06G032_CLK_CM3 93
|
||||
#define R9A06G032_CLK_DDRC 94
|
||||
#define R9A06G032_CLK_ECAT25 95
|
||||
#define R9A06G032_CLK_HSR50 96
|
||||
#define R9A06G032_CLK_HW_RTOS 97
|
||||
#define R9A06G032_CLK_SERCOS50 98
|
||||
#define R9A06G032_HCLK_ADC 99
|
||||
#define R9A06G032_HCLK_CM3 100
|
||||
#define R9A06G032_HCLK_CRYPTO_EIP150 101
|
||||
#define R9A06G032_HCLK_CRYPTO_EIP93 102
|
||||
#define R9A06G032_HCLK_DDRC 103
|
||||
#define R9A06G032_HCLK_DMA0 104
|
||||
#define R9A06G032_HCLK_DMA1 105
|
||||
#define R9A06G032_HCLK_GMAC0 106
|
||||
#define R9A06G032_HCLK_GMAC1 107
|
||||
#define R9A06G032_HCLK_GPIO0 108
|
||||
#define R9A06G032_HCLK_GPIO1 109
|
||||
#define R9A06G032_HCLK_GPIO2 110
|
||||
#define R9A06G032_HCLK_HSR 111
|
||||
#define R9A06G032_HCLK_I2C0 112
|
||||
#define R9A06G032_HCLK_I2C1 113
|
||||
#define R9A06G032_HCLK_LCD 114
|
||||
#define R9A06G032_HCLK_MSEBI_M 115
|
||||
#define R9A06G032_HCLK_MSEBI_S 116
|
||||
#define R9A06G032_HCLK_NAND 117
|
||||
#define R9A06G032_HCLK_PG_I 118
|
||||
#define R9A06G032_HCLK_PG19 119
|
||||
#define R9A06G032_HCLK_PG20 120
|
||||
#define R9A06G032_HCLK_PG3 121
|
||||
#define R9A06G032_HCLK_PG4 122
|
||||
#define R9A06G032_HCLK_QSPI0 123
|
||||
#define R9A06G032_HCLK_QSPI1 124
|
||||
#define R9A06G032_HCLK_ROM 125
|
||||
#define R9A06G032_HCLK_RTC 126
|
||||
#define R9A06G032_HCLK_SDIO0 127
|
||||
#define R9A06G032_HCLK_SDIO1 128
|
||||
#define R9A06G032_HCLK_SEMAP 129
|
||||
#define R9A06G032_HCLK_SPI0 130
|
||||
#define R9A06G032_HCLK_SPI1 131
|
||||
#define R9A06G032_HCLK_SPI2 132
|
||||
#define R9A06G032_HCLK_SPI3 133
|
||||
#define R9A06G032_HCLK_SPI4 134
|
||||
#define R9A06G032_HCLK_SPI5 135
|
||||
#define R9A06G032_HCLK_SWITCH 136
|
||||
#define R9A06G032_HCLK_SWITCH_RG 137
|
||||
#define R9A06G032_HCLK_UART0 138
|
||||
#define R9A06G032_HCLK_UART1 139
|
||||
#define R9A06G032_HCLK_UART2 140
|
||||
#define R9A06G032_HCLK_UART3 141
|
||||
#define R9A06G032_HCLK_UART4 142
|
||||
#define R9A06G032_HCLK_UART5 143
|
||||
#define R9A06G032_HCLK_UART6 144
|
||||
#define R9A06G032_HCLK_UART7 145
|
||||
#define R9A06G032_CLK_UART0 146
|
||||
#define R9A06G032_CLK_UART1 147
|
||||
#define R9A06G032_CLK_UART2 148
|
||||
#define R9A06G032_CLK_UART3 149
|
||||
#define R9A06G032_CLK_UART4 150
|
||||
#define R9A06G032_CLK_UART5 151
|
||||
#define R9A06G032_CLK_UART6 152
|
||||
#define R9A06G032_CLK_UART7 153
|
||||
|
||||
#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */
|
56
sys/gnu/dts/include/dt-bindings/clock/rk3399-ddr.h
Normal file
56
sys/gnu/dts/include/dt-bindings/clock/rk3399-ddr.h
Normal file
@ -0,0 +1,56 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
|
||||
#ifndef DT_BINDINGS_DDR_H
|
||||
#define DT_BINDINGS_DDR_H
|
||||
|
||||
/*
|
||||
* DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for
|
||||
* each corresponding bin.
|
||||
*/
|
||||
|
||||
/* DDR3-800 (5-5-5) */
|
||||
#define DDR3_800D 0
|
||||
/* DDR3-800 (6-6-6) */
|
||||
#define DDR3_800E 1
|
||||
/* DDR3-1066 (6-6-6) */
|
||||
#define DDR3_1066E 2
|
||||
/* DDR3-1066 (7-7-7) */
|
||||
#define DDR3_1066F 3
|
||||
/* DDR3-1066 (8-8-8) */
|
||||
#define DDR3_1066G 4
|
||||
/* DDR3-1333 (7-7-7) */
|
||||
#define DDR3_1333F 5
|
||||
/* DDR3-1333 (8-8-8) */
|
||||
#define DDR3_1333G 6
|
||||
/* DDR3-1333 (9-9-9) */
|
||||
#define DDR3_1333H 7
|
||||
/* DDR3-1333 (10-10-10) */
|
||||
#define DDR3_1333J 8
|
||||
/* DDR3-1600 (8-8-8) */
|
||||
#define DDR3_1600G 9
|
||||
/* DDR3-1600 (9-9-9) */
|
||||
#define DDR3_1600H 10
|
||||
/* DDR3-1600 (10-10-10) */
|
||||
#define DDR3_1600J 11
|
||||
/* DDR3-1600 (11-11-11) */
|
||||
#define DDR3_1600K 12
|
||||
/* DDR3-1600 (10-10-10) */
|
||||
#define DDR3_1866J 13
|
||||
/* DDR3-1866 (11-11-11) */
|
||||
#define DDR3_1866K 14
|
||||
/* DDR3-1866 (12-12-12) */
|
||||
#define DDR3_1866L 15
|
||||
/* DDR3-1866 (13-13-13) */
|
||||
#define DDR3_1866M 16
|
||||
/* DDR3-2133 (11-11-11) */
|
||||
#define DDR3_2133K 17
|
||||
/* DDR3-2133 (12-12-12) */
|
||||
#define DDR3_2133L 18
|
||||
/* DDR3-2133 (13-13-13) */
|
||||
#define DDR3_2133M 19
|
||||
/* DDR3-2133 (14-14-14) */
|
||||
#define DDR3_2133N 20
|
||||
/* DDR3 ATF default */
|
||||
#define DDR3_DEFAULT 21
|
||||
|
||||
#endif
|
@ -43,6 +43,10 @@
|
||||
#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_
|
||||
#define _DT_BINDINGS_CLK_SUN8I_R40_H_
|
||||
|
||||
#define CLK_PLL_VIDEO0 7
|
||||
|
||||
#define CLK_PLL_VIDEO1 16
|
||||
|
||||
#define CLK_CPU 24
|
||||
|
||||
#define CLK_BUS_MIPI_DSI 29
|
||||
|
11
sys/gnu/dts/include/dt-bindings/clock/sun8i-tcon-top.h
Normal file
11
sys/gnu/dts/include/dt-bindings/clock/sun8i-tcon-top.h
Normal file
@ -0,0 +1,11 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/* Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
|
||||
#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
|
||||
|
||||
#define CLK_TCON_TOP_TV0 0
|
||||
#define CLK_TCON_TOP_TV1 1
|
||||
#define CLK_TCON_TOP_DSI 2
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */
|
49
sys/gnu/dts/include/dt-bindings/dma/jz4780-dma.h
Normal file
49
sys/gnu/dts/include/dt-bindings/dma/jz4780-dma.h
Normal file
@ -0,0 +1,49 @@
|
||||
#ifndef __DT_BINDINGS_DMA_JZ4780_DMA_H__
|
||||
#define __DT_BINDINGS_DMA_JZ4780_DMA_H__
|
||||
|
||||
/*
|
||||
* Request type numbers for the JZ4780 DMA controller (written to the DRTn
|
||||
* register for the channel).
|
||||
*/
|
||||
#define JZ4780_DMA_I2S1_TX 0x4
|
||||
#define JZ4780_DMA_I2S1_RX 0x5
|
||||
#define JZ4780_DMA_I2S0_TX 0x6
|
||||
#define JZ4780_DMA_I2S0_RX 0x7
|
||||
#define JZ4780_DMA_AUTO 0x8
|
||||
#define JZ4780_DMA_SADC_RX 0x9
|
||||
#define JZ4780_DMA_UART4_TX 0xc
|
||||
#define JZ4780_DMA_UART4_RX 0xd
|
||||
#define JZ4780_DMA_UART3_TX 0xe
|
||||
#define JZ4780_DMA_UART3_RX 0xf
|
||||
#define JZ4780_DMA_UART2_TX 0x10
|
||||
#define JZ4780_DMA_UART2_RX 0x11
|
||||
#define JZ4780_DMA_UART1_TX 0x12
|
||||
#define JZ4780_DMA_UART1_RX 0x13
|
||||
#define JZ4780_DMA_UART0_TX 0x14
|
||||
#define JZ4780_DMA_UART0_RX 0x15
|
||||
#define JZ4780_DMA_SSI0_TX 0x16
|
||||
#define JZ4780_DMA_SSI0_RX 0x17
|
||||
#define JZ4780_DMA_SSI1_TX 0x18
|
||||
#define JZ4780_DMA_SSI1_RX 0x19
|
||||
#define JZ4780_DMA_MSC0_TX 0x1a
|
||||
#define JZ4780_DMA_MSC0_RX 0x1b
|
||||
#define JZ4780_DMA_MSC1_TX 0x1c
|
||||
#define JZ4780_DMA_MSC1_RX 0x1d
|
||||
#define JZ4780_DMA_MSC2_TX 0x1e
|
||||
#define JZ4780_DMA_MSC2_RX 0x1f
|
||||
#define JZ4780_DMA_PCM0_TX 0x20
|
||||
#define JZ4780_DMA_PCM0_RX 0x21
|
||||
#define JZ4780_DMA_SMB0_TX 0x24
|
||||
#define JZ4780_DMA_SMB0_RX 0x25
|
||||
#define JZ4780_DMA_SMB1_TX 0x26
|
||||
#define JZ4780_DMA_SMB1_RX 0x27
|
||||
#define JZ4780_DMA_SMB2_TX 0x28
|
||||
#define JZ4780_DMA_SMB2_RX 0x29
|
||||
#define JZ4780_DMA_SMB3_TX 0x2a
|
||||
#define JZ4780_DMA_SMB3_RX 0x2b
|
||||
#define JZ4780_DMA_SMB4_TX 0x2c
|
||||
#define JZ4780_DMA_SMB4_RX 0x2d
|
||||
#define JZ4780_DMA_DES_TX 0x2e
|
||||
#define JZ4780_DMA_DES_RX 0x2f
|
||||
|
||||
#endif /* __DT_BINDINGS_DMA_JZ4780_DMA_H__ */
|
44
sys/gnu/dts/include/dt-bindings/gce/mt8173-gce.h
Normal file
44
sys/gnu/dts/include/dt-bindings/gce/mt8173-gce.h
Normal file
@ -0,0 +1,44 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2018 MediaTek Inc.
|
||||
* Author: Houlong Wei <houlong.wei@mediatek.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_GCE_MT8173_H
|
||||
#define _DT_BINDINGS_GCE_MT8173_H
|
||||
|
||||
/* GCE HW thread priority */
|
||||
#define CMDQ_THR_PRIO_LOWEST 0
|
||||
#define CMDQ_THR_PRIO_HIGHEST 1
|
||||
|
||||
/* GCE SUBSYS */
|
||||
#define SUBSYS_1400XXXX 1
|
||||
#define SUBSYS_1401XXXX 2
|
||||
#define SUBSYS_1402XXXX 3
|
||||
|
||||
/* GCE HW EVENT */
|
||||
#define CMDQ_EVENT_DISP_OVL0_SOF 11
|
||||
#define CMDQ_EVENT_DISP_OVL1_SOF 12
|
||||
#define CMDQ_EVENT_DISP_RDMA0_SOF 13
|
||||
#define CMDQ_EVENT_DISP_RDMA1_SOF 14
|
||||
#define CMDQ_EVENT_DISP_RDMA2_SOF 15
|
||||
#define CMDQ_EVENT_DISP_WDMA0_SOF 16
|
||||
#define CMDQ_EVENT_DISP_WDMA1_SOF 17
|
||||
#define CMDQ_EVENT_DISP_OVL0_EOF 39
|
||||
#define CMDQ_EVENT_DISP_OVL1_EOF 40
|
||||
#define CMDQ_EVENT_DISP_RDMA0_EOF 41
|
||||
#define CMDQ_EVENT_DISP_RDMA1_EOF 42
|
||||
#define CMDQ_EVENT_DISP_RDMA2_EOF 43
|
||||
#define CMDQ_EVENT_DISP_WDMA0_EOF 44
|
||||
#define CMDQ_EVENT_DISP_WDMA1_EOF 45
|
||||
#define CMDQ_EVENT_MUTEX0_STREAM_EOF 53
|
||||
#define CMDQ_EVENT_MUTEX1_STREAM_EOF 54
|
||||
#define CMDQ_EVENT_MUTEX2_STREAM_EOF 55
|
||||
#define CMDQ_EVENT_MUTEX3_STREAM_EOF 56
|
||||
#define CMDQ_EVENT_MUTEX4_STREAM_EOF 57
|
||||
#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 63
|
||||
#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 64
|
||||
#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 65
|
||||
|
||||
#endif
|
16
sys/gnu/dts/include/dt-bindings/iio/adc/at91-sama5d2_adc.h
Normal file
16
sys/gnu/dts/include/dt-bindings/iio/adc/at91-sama5d2_adc.h
Normal file
@ -0,0 +1,16 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* This header provides constants for configuring the AT91 SAMA5D2 ADC
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_IIO_ADC_AT91_SAMA5D2_ADC_H
|
||||
#define _DT_BINDINGS_IIO_ADC_AT91_SAMA5D2_ADC_H
|
||||
|
||||
/* X relative position channel index */
|
||||
#define AT91_SAMA5D2_ADC_X_CHANNEL 24
|
||||
/* Y relative position channel index */
|
||||
#define AT91_SAMA5D2_ADC_Y_CHANNEL 25
|
||||
/* pressure channel index */
|
||||
#define AT91_SAMA5D2_ADC_P_CHANNEL 26
|
||||
|
||||
#endif
|
95
sys/gnu/dts/include/dt-bindings/memory/mt2712-larb-port.h
Normal file
95
sys/gnu/dts/include/dt-bindings/memory/mt2712-larb-port.h
Normal file
@ -0,0 +1,95 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Yong Wu <yong.wu@mediatek.com>
|
||||
*/
|
||||
#ifndef __DTS_IOMMU_PORT_MT2712_H
|
||||
#define __DTS_IOMMU_PORT_MT2712_H
|
||||
|
||||
#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
|
||||
|
||||
#define M4U_LARB0_ID 0
|
||||
#define M4U_LARB1_ID 1
|
||||
#define M4U_LARB2_ID 2
|
||||
#define M4U_LARB3_ID 3
|
||||
#define M4U_LARB4_ID 4
|
||||
#define M4U_LARB5_ID 5
|
||||
#define M4U_LARB6_ID 6
|
||||
#define M4U_LARB7_ID 7
|
||||
#define M4U_LARB8_ID 8
|
||||
#define M4U_LARB9_ID 9
|
||||
|
||||
/* larb0 */
|
||||
#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
|
||||
#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1)
|
||||
#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)
|
||||
#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3)
|
||||
#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4)
|
||||
#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
|
||||
#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6)
|
||||
#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 7)
|
||||
|
||||
/* larb1 */
|
||||
#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0)
|
||||
#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1)
|
||||
#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2)
|
||||
#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3)
|
||||
#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4)
|
||||
#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5)
|
||||
#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6)
|
||||
#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7)
|
||||
#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8)
|
||||
#define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9)
|
||||
#define M4U_PORT_HW_IMG_RESZ_EXT MTK_M4U_ID(M4U_LARB1_ID, 10)
|
||||
|
||||
/* larb2 */
|
||||
#define M4U_PORT_CAM_DMA0 MTK_M4U_ID(M4U_LARB2_ID, 0)
|
||||
#define M4U_PORT_CAM_DMA1 MTK_M4U_ID(M4U_LARB2_ID, 1)
|
||||
#define M4U_PORT_CAM_DMA2 MTK_M4U_ID(M4U_LARB2_ID, 2)
|
||||
|
||||
/* larb3 */
|
||||
#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0)
|
||||
#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1)
|
||||
#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2)
|
||||
#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3)
|
||||
#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4)
|
||||
#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 5)
|
||||
#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 6)
|
||||
#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 7)
|
||||
#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 8)
|
||||
|
||||
/* larb4 */
|
||||
#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0)
|
||||
#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1)
|
||||
#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 2)
|
||||
#define M4U_PORT_DISP_OD1_R MTK_M4U_ID(M4U_LARB4_ID, 3)
|
||||
#define M4U_PORT_DISP_OD1_W MTK_M4U_ID(M4U_LARB4_ID, 4)
|
||||
#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 5)
|
||||
#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 6)
|
||||
|
||||
/* larb5 */
|
||||
#define M4U_PORT_DISP_OVL2 MTK_M4U_ID(M4U_LARB5_ID, 0)
|
||||
#define M4U_PORT_DISP_WDMA2 MTK_M4U_ID(M4U_LARB5_ID, 1)
|
||||
#define M4U_PORT_MDP_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 2)
|
||||
#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB5_ID, 3)
|
||||
|
||||
/* larb6 */
|
||||
#define M4U_PORT_JPGDEC_WDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 0)
|
||||
#define M4U_PORT_JPGDEC_WDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 1)
|
||||
#define M4U_PORT_JPGDEC_BSDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 2)
|
||||
#define M4U_PORT_JPGDEC_BSDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 3)
|
||||
|
||||
/* larb7 */
|
||||
#define M4U_PORT_MDP_RDMA3 MTK_M4U_ID(M4U_LARB7_ID, 0)
|
||||
#define M4U_PORT_MDP_WROT2 MTK_M4U_ID(M4U_LARB7_ID, 1)
|
||||
|
||||
/* larb8 */
|
||||
#define M4U_PORT_VDO MTK_M4U_ID(M4U_LARB8_ID, 0)
|
||||
#define M4U_PORT_NR MTK_M4U_ID(M4U_LARB8_ID, 1)
|
||||
#define M4U_PORT_WR_CHANNEL0 MTK_M4U_ID(M4U_LARB8_ID, 2)
|
||||
|
||||
/* larb9 */
|
||||
#define M4U_PORT_TVD MTK_M4U_ID(M4U_LARB9_ID, 0)
|
||||
#define M4U_PORT_WR_CHANNEL1 MTK_M4U_ID(M4U_LARB9_ID, 1)
|
||||
|
||||
#endif
|
@ -39,4 +39,8 @@
|
||||
#define AT91_PERIPH_C 3
|
||||
#define AT91_PERIPH_D 4
|
||||
|
||||
#define ATMEL_PIO_DRVSTR_LO 1
|
||||
#define ATMEL_PIO_DRVSTR_ME 2
|
||||
#define ATMEL_PIO_DRVSTR_HI 3
|
||||
|
||||
#endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */
|
||||
|
@ -1,13 +1,10 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Samsung's Exynos pinctrl bindings
|
||||
*
|
||||
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
* Author: Krzysztof Kozlowski <krzk@kernel.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__
|
||||
|
@ -1,10 +1,7 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2014 Google, Inc
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Device Tree binding constants for the Maxim 77802 PMIC regulators
|
||||
*/
|
||||
|
||||
|
@ -0,0 +1,36 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
|
||||
|
||||
#ifndef __QCOM_RPMH_REGULATOR_H
|
||||
#define __QCOM_RPMH_REGULATOR_H
|
||||
|
||||
/*
|
||||
* These mode constants may be used to specify modes for various RPMh regulator
|
||||
* device tree properties (e.g. regulator-initial-mode). Each type of regulator
|
||||
* supports a subset of the possible modes.
|
||||
*
|
||||
* %RPMH_REGULATOR_MODE_RET: Retention mode in which only an extremely small
|
||||
* load current is allowed. This mode is supported
|
||||
* by LDO and SMPS type regulators.
|
||||
* %RPMH_REGULATOR_MODE_LPM: Low power mode in which a small load current is
|
||||
* allowed. This mode corresponds to PFM for SMPS
|
||||
* and BOB type regulators. This mode is supported
|
||||
* by LDO, HFSMPS, BOB, and PMIC4 FTSMPS type
|
||||
* regulators.
|
||||
* %RPMH_REGULATOR_MODE_AUTO: Auto mode in which the regulator hardware
|
||||
* automatically switches between LPM and HPM based
|
||||
* upon the real-time load current. This mode is
|
||||
* supported by HFSMPS, BOB, and PMIC4 FTSMPS type
|
||||
* regulators.
|
||||
* %RPMH_REGULATOR_MODE_HPM: High power mode in which the full rated current
|
||||
* of the regulator is allowed. This mode
|
||||
* corresponds to PWM for SMPS and BOB type
|
||||
* regulators. This mode is supported by all types
|
||||
* of regulators.
|
||||
*/
|
||||
#define RPMH_REGULATOR_MODE_RET 0
|
||||
#define RPMH_REGULATOR_MODE_LPM 1
|
||||
#define RPMH_REGULATOR_MODE_AUTO 2
|
||||
#define RPMH_REGULATOR_MODE_HPM 3
|
||||
|
||||
#endif
|
@ -0,0 +1,17 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
*
|
||||
* Copyright (c) 2018 Baylibre SAS.
|
||||
* Author: Jerome Brunet <jbrunet@baylibre.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H
|
||||
#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H
|
||||
|
||||
#define AXG_ARB_TODDR_A 0
|
||||
#define AXG_ARB_TODDR_B 1
|
||||
#define AXG_ARB_TODDR_C 2
|
||||
#define AXG_ARB_FRDDR_A 3
|
||||
#define AXG_ARB_FRDDR_B 4
|
||||
#define AXG_ARB_FRDDR_C 5
|
||||
|
||||
#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */
|
17
sys/gnu/dts/include/dt-bindings/reset/qcom,sdm845-aoss.h
Normal file
17
sys/gnu/dts/include/dt-bindings/reset/qcom,sdm845-aoss.h
Normal file
@ -0,0 +1,17 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018 The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H
|
||||
#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
|
||||
|
||||
#define AOSS_CC_MSS_RESTART 0
|
||||
#define AOSS_CC_CAMSS_RESTART 1
|
||||
#define AOSS_CC_VENUS_RESTART 2
|
||||
#define AOSS_CC_GPU_RESTART 3
|
||||
#define AOSS_CC_DISPSS_RESTART 4
|
||||
#define AOSS_CC_WCSS_RESTART 5
|
||||
#define AOSS_CC_LPASS_RESTART 6
|
||||
|
||||
#endif
|
14
sys/gnu/dts/include/dt-bindings/soc/qcom,rpmh-rsc.h
Normal file
14
sys/gnu/dts/include/dt-bindings/soc/qcom,rpmh-rsc.h
Normal file
@ -0,0 +1,14 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __DT_QCOM_RPMH_RSC_H__
|
||||
#define __DT_QCOM_RPMH_RSC_H__
|
||||
|
||||
#define SLEEP_TCS 0
|
||||
#define WAKE_TCS 1
|
||||
#define ACTIVE_TCS 2
|
||||
#define CONTROL_TCS 3
|
||||
|
||||
#endif /* __DT_QCOM_RPMH_RSC_H__ */
|
62
sys/gnu/dts/include/dt-bindings/usb/pd.h
Normal file
62
sys/gnu/dts/include/dt-bindings/usb/pd.h
Normal file
@ -0,0 +1,62 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __DT_POWER_DELIVERY_H
|
||||
#define __DT_POWER_DELIVERY_H
|
||||
|
||||
/* Power delivery Power Data Object definitions */
|
||||
#define PDO_TYPE_FIXED 0
|
||||
#define PDO_TYPE_BATT 1
|
||||
#define PDO_TYPE_VAR 2
|
||||
#define PDO_TYPE_APDO 3
|
||||
|
||||
#define PDO_TYPE_SHIFT 30
|
||||
#define PDO_TYPE_MASK 0x3
|
||||
|
||||
#define PDO_TYPE(t) ((t) << PDO_TYPE_SHIFT)
|
||||
|
||||
#define PDO_VOLT_MASK 0x3ff
|
||||
#define PDO_CURR_MASK 0x3ff
|
||||
#define PDO_PWR_MASK 0x3ff
|
||||
|
||||
#define PDO_FIXED_DUAL_ROLE (1 << 29) /* Power role swap supported */
|
||||
#define PDO_FIXED_SUSPEND (1 << 28) /* USB Suspend supported (Source) */
|
||||
#define PDO_FIXED_HIGHER_CAP (1 << 28) /* Requires more than vSafe5V (Sink) */
|
||||
#define PDO_FIXED_EXTPOWER (1 << 27) /* Externally powered */
|
||||
#define PDO_FIXED_USB_COMM (1 << 26) /* USB communications capable */
|
||||
#define PDO_FIXED_DATA_SWAP (1 << 25) /* Data role swap supported */
|
||||
#define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */
|
||||
#define PDO_FIXED_CURR_SHIFT 0 /* 10mA units */
|
||||
|
||||
#define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT)
|
||||
#define PDO_FIXED_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT)
|
||||
|
||||
#define PDO_FIXED(mv, ma, flags) \
|
||||
(PDO_TYPE(PDO_TYPE_FIXED) | (flags) | \
|
||||
PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma))
|
||||
|
||||
#define VSAFE5V 5000 /* mv units */
|
||||
|
||||
#define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */
|
||||
#define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */
|
||||
#define PDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */
|
||||
|
||||
#define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT)
|
||||
#define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT)
|
||||
#define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT)
|
||||
|
||||
#define PDO_BATT(min_mv, max_mv, max_mw) \
|
||||
(PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) | \
|
||||
PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw))
|
||||
|
||||
#define PDO_VAR_MAX_VOLT_SHIFT 20 /* 50mV units */
|
||||
#define PDO_VAR_MIN_VOLT_SHIFT 10 /* 50mV units */
|
||||
#define PDO_VAR_MAX_CURR_SHIFT 0 /* 10mA units */
|
||||
|
||||
#define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT)
|
||||
#define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT)
|
||||
#define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT)
|
||||
|
||||
#define PDO_VAR(min_mv, max_mv, max_ma) \
|
||||
(PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) | \
|
||||
PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma))
|
||||
|
||||
#endif /* __DT_POWER_DELIVERY_H */
|
Loading…
Reference in New Issue
Block a user