Revert r225875, r225877:
It is reported that on some chips (e.g. the 970MP) behavior of POW bit set simultaneously with modifying other bits is undefined and may cause hangs. The race should be handled in some other way, but for now just get back. Reported by: nwitehorn
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parent
b2e855ac7a
commit
3ddd7d96bb
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=225953
@ -65,7 +65,6 @@
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#include <sys/cpu.h>
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#include <sys/kernel.h>
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#include <sys/proc.h>
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#include <sys/sched.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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@ -554,11 +553,6 @@ cpu_idle_60x(void)
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vers = mfpvr() >> 16;
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#ifdef AIM
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mtmsr(msr & ~PSL_EE);
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if (sched_runnable()) {
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mtmsr(msr);
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return;
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}
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switch (vers) {
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case IBM970:
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case IBM970FX:
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@ -589,11 +583,6 @@ cpu_idle_e500(void)
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msr = mfmsr();
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#ifdef E500
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mtmsr(msr & ~PSL_EE);
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if (sched_runnable()) {
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mtmsr(msr);
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return;
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}
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/* Freescale E500 core RM section 6.4.1. */
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__asm __volatile("msync; mtmsr %0; isync" ::
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"r" (msr | PSL_WE));
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