Fix grabbing of tegra uart.

An attempt to write to FCR register may corrupt transmit FIFO,
so we should wait for the FIFO to be empty before we can modify it.

MFC after:	1 week
This commit is contained in:
Michal Meloun 2020-06-11 12:53:22 +00:00
parent 433d61a573
commit 3e13ea16a6
Notes: svn2git 2020-12-20 02:59:44 +00:00
svn path=/head/; revision=362053

View File

@ -102,6 +102,10 @@ tegra_uart_grab(struct uart_softc *sc)
uart_lock(sc->sc_hwmtx);
ier = uart_getreg(bas, REG_IER);
uart_setreg(bas, REG_IER, ier & ns8250->ier_mask);
while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0)
;
uart_setreg(bas, REG_FCR, 0);
uart_barrier(bas);
uart_unlock(sc->sc_hwmtx);