d/freebsd-dev
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add support for the ASC3550 AdvanSys SCSI Host Controller (aka 940UW).

Browse Source
This commit is contained in:
gibbs 1998-10-07 03:20:52 +00:00
parent 2451509b71
commit 3ea6566db5
9 changed files with 3533 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
sys/conf/files
View File

@ -87,6 +87,9 @@ ddb/db_write_cmd.c optional ddb
dev/advansys/advansys.c optional adv device-driver
dev/advansys/advlib.c optional adv device-driver
dev/advansys/advmcode.c optional adv device-driver
dev/advansys/adwcam.c optional adw device-driver
dev/advansys/adwlib.c optional adw device-driver
dev/advansys/adwmcode.c optional adw device-driver
dev/aha/aha.c optional aha device-driver
dev/aic7xxx/aic7xxx.c optional ahc device-driver \
dependency "aic7xxx_{reg,seq}.h"
@ -499,6 +502,7 @@ pccard/pccard_beep.c optional card
pccard/pcic.c optional pcic device-driver
pci/pcic_p.c optional pcic device-driver
pci/adv_pci.c optional adv device-driver
pci/adw_pci.c optional adw device-driver
pci/ahc_pci.c optional ahc device-driver \
dependency "aic7xxx_reg.h $S/pci/ahc_pci.c"
pci/brooktree848.c optional bktr device-driver

185
sys/dev/advansys/adw_pci.c Normal file
View File

@ -0,0 +1,185 @@
/*
* Device probe and attach routines for the following
* Advanced Systems Inc. SCSI controllers:
*
* ABP940UW - Bus-Master PCI Ultra-Wide (240 CDB)
*
* Copyright (c) 1998 Justin Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id$
*/
#include <pci.h>
#if NPCI > 0
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <machine/bus_pio.h>
#include <machine/bus.h>
#include <pci/pcireg.h>
#include <pci/pcivar.h>
#include <cam/cam.h>
#include <cam/scsi/scsi_all.h>
#include <dev/advansys/adwvar.h>
#include <dev/advansys/adwlib.h>
#include <dev/advansys/adwmcode.h>
#define PCI_BASEADR0 PCI_MAP_REG_START /* I/O Address */
#define PCI_BASEADR1 PCI_MAP_REG_START + 4 /* Mem I/O Address */
#define PCI_DEVICE_ID_ADVANSYS_3550 0x230010CD
#define ADW_PCI_MAX_DMA_ADDR (0xFFFFFFFFUL)
#define ADW_PCI_MAX_DMA_COUNT (0xFFFFFFFFUL)
static char* adwpciprobe(pcici_t tag, pcidi_t type);
static void adwpciattach(pcici_t config_id, int unit);
static struct pci_device adw_pci_driver = {
"adw",
adwpciprobe,
adwpciattach,
&adw_unit,
NULL
};
DATA_SET (pcidevice_set, adw_pci_driver);
static char*
adwpciprobe(pcici_t tag, pcidi_t type)
{
switch (type) {
case PCI_DEVICE_ID_ADVANSYS_3550:
return ("AdvanSys ASC3550 SCSI controller");
default:
break;
}
return (NULL);
}
static void
adwpciattach(pcici_t config_id, int unit)
{
u_int32_t id;
u_int32_t command;
vm_offset_t vaddr;
vm_offset_t paddr;
u_int16_t io_port;
bus_space_tag_t tag;
bus_space_handle_t bsh;
struct adw_softc *adw;
int error;
/*
* Determine the chip version.
*/
id = pci_cfgread(config_id, PCI_ID_REG, /*bytes*/4);
command = pci_cfgread(config_id, PCIR_COMMAND, /*bytes*/1);
/*
* These cards do not allow memory mapped accesses, so we must
* ensure that I/O accesses are available or we won't be able
* to talk to them.
*/
vaddr = 0;
#ifdef ADW_ALLOW_MEMIO
if ((command & PCI_COMMAND_MEM_ENABLE) == 0
|| (pci_map_mem(config_id, PCI_BASEADR1, &vaddr, &paddr)) == 0)
#endif
if ((command & PCI_COMMAND_IO_ENABLE) == 0
|| (pci_map_port(config_id, PCI_BASEADR0, &io_port)) == 0)
return;
/* XXX Should be passed in by parent bus */
/* XXX Why isn't the 0x10 offset incorporated into the reg defs? */
if (vaddr != 0) {
tag = I386_BUS_SPACE_MEM;
bsh = vaddr;
} else {
tag = I386_BUS_SPACE_IO;
bsh = io_port;
}
if (adw_find_signature(tag, bsh) == 0)
return;
adw = adw_alloc(unit, tag, bsh);
if (adw == NULL)
return;
/* Allocate a dmatag for our transfer DMA maps */
/* XXX Should be a child of the PCI bus dma tag */
error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/0,
/*boundary*/0,
/*lowaddr*/ADW_PCI_MAX_DMA_ADDR,
/*highaddr*/BUS_SPACE_MAXADDR,
/*filter*/NULL, /*filterarg*/NULL,
/*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
/*nsegments*/BUS_SPACE_UNRESTRICTED,
/*maxsegsz*/ADW_PCI_MAX_DMA_COUNT,
/*flags*/0,
&adw->parent_dmat);
adw->init_level++;
if (error != 0) {
printf("%s: Could not allocate DMA tag - error %d\n",
adw_name(adw), error);
adw_free(adw);
return;
}
adw->init_level++;
if (adw_init(adw) != 0) {
adw_free(adw);
return;
}
/*
* If the PCI Configuration Command Register "Parity Error Response
* Control" Bit was clear (0), then set the microcode variable
* 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
* to ignore DMA parity errors.
*/
if ((command & PCIM_CMD_PERRESPEN) == 0)
adw_lram_write_16(adw, ADW_MC_CONTROL_FLAG,
adw_lram_read_16(adw, ADW_MC_CONTROL_FLAG)
| ADW_MC_CONTROL_IGN_PERR);
if ((pci_map_int(config_id, adw_intr, (void *)adw, &cam_imask)) == 0) {
adw_free(adw);
return;
}
adw_attach(adw);
}
#endif /* NPCI > 0 */

1366
sys/dev/advansys/adwcam.c Normal file
View File

File diff suppressed because it is too large Load Diff

563
sys/dev/advansys/adwlib.c Normal file
View File

@ -0,0 +1,563 @@
/*
* Low level routines for Second Generation
* Advanced Systems Inc. SCSI controllers chips
*
* Copyright (c) 1998 Justin Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id$
*/
/*
* Ported from:
* advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
*
* Copyright (c) 1995-1998 Advanced System Products, Inc.
* All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that redistributions of source
* code retain the above copyright notice and this comment without
* modification.
*/
#include <sys/queue.h>
#include <sys/systm.h>
#include <machine/bus_pio.h>
#include <machine/bus_memio.h>
#include <machine/bus.h>
#include <machine/clock.h>
#include <cam/cam.h>
#include <cam/scsi/scsi_all.h>
#include <dev/advansys/adwlib.h>
struct adw_eeprom adw_default_eeprom = {
ADW_EEPROM_BIOS_ENABLE, /* cfg_lsw */
0x0000, /* cfg_msw */
0xFFFF, /* disc_enable */
0xFFFF, /* wdtr_able */
0xFFFF, /* sdtr_able */
0xFFFF, /* start_motor */
0xFFFF, /* tagqng_able */
0xFFFF, /* bios_scan */
0, /* scam_tolerant */
7, /* adapter_scsi_id */
0, /* bios_boot_delay */
3, /* scsi_reset_delay */
0, /* bios_id_lun */
0, /* termination */
0, /* reserved1 */
{ /* Bios Ctrl */
1, 1, 1, 1, 1,
1, 1, 1, 1, 1,
},
0xFFFF, /* ultra_able */
0, /* reserved2 */
ADW_DEF_MAX_HOST_QNG, /* max_host_qng */
ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
0, /* dvc_cntl */
0, /* bug_fix */
{ 0, 0, 0 }, /* serial_number */
0, /* check_sum */
{ /* oem_name[16] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0
},
0, /* dvc_err_code */
0, /* adv_err_code */
0, /* adv_err_addr */
0, /* saved_dvc_err_code */
0, /* saved_adv_err_code */
0, /* saved_adv_err_addr */
0 /* num_of_err */
};
static u_int16_t adw_eeprom_read_16(struct adw_softc *adw, int addr);
static void adw_eeprom_write_16(struct adw_softc *adw, int addr,
u_int data);
static void adw_eeprom_wait(struct adw_softc *adw);
int
adw_find_signature(bus_space_tag_t tag, bus_space_handle_t bsh)
{
if (bus_space_read_1(tag, bsh, ADW_SIGNATURE_BYTE) == ADW_CHIP_ID_BYTE
&& bus_space_read_2(tag, bsh, ADW_SIGNATURE_WORD) == ADW_CHIP_ID_WORD)
return (1);
return (0);
}
/*
* Reset Chip.
*/
void
adw_reset_chip(struct adw_softc *adw)
{
adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_RESET);
DELAY(100);
adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_WR_IO_REG);
/*
* Initialize Chip registers.
*/
adw_outb(adw, ADW_MEM_CFG,
adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_8KB);
adw_outw(adw, ADW_SCSI_CFG1,
adw_inw(adw, ADW_SCSI_CFG1) & ~ADW_SCSI_CFG1_BIG_ENDIAN);
/*
* Setting the START_CTL_EM_FU 3:2 bits sets a FIFO threshold
* of 128 bytes. This register is only accessible to the host.
*/
adw_outb(adw, ADW_DMA_CFG0,
ADW_DMA_CFG0_START_CTL_EM_FU|ADW_DMA_CFG0_READ_CMD_MRM);
}
/*
* Read the specified EEPROM location
*/
static u_int16_t
adw_eeprom_read_16(struct adw_softc *adw, int addr)
{
adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_READ | addr);
adw_eeprom_wait(adw);
return (adw_inw(adw, ADW_EEP_DATA));
}
static void
adw_eeprom_write_16(struct adw_softc *adw, int addr, u_int data)
{
adw_outw(adw, ADW_EEP_DATA, data);
adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE | addr);
adw_eeprom_wait(adw);
}
/*
* Wait for and EEPROM command to complete
*/
static void
adw_eeprom_wait(struct adw_softc *adw)
{
int i;
for (i = 0; i < ADW_EEP_DELAY_MS; i++) {
if ((adw_inw(adw, ADW_EEP_CMD) & ADW_EEP_CMD_DONE) != 0)
break;
DELAY(1000);
}
if (i == ADW_EEP_DELAY_MS)
panic("%s: Timedout Reading EEPROM", adw_name(adw));
}
/*
* Read EEPROM configuration into the specified buffer.
*
* Return a checksum based on the EEPROM configuration read.
*/
u_int16_t
adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *eep_buf)
{
u_int16_t *wbuf;
u_int16_t wval;
u_int16_t chksum;
int eep_addr;
wbuf = (u_int16_t *)eep_buf;
chksum = 0;
for (eep_addr = ADW_EEP_DVC_CFG_BEGIN;
eep_addr < ADW_EEP_DVC_CFG_END;
eep_addr++, wbuf++) {
wval = adw_eeprom_read_16(adw, eep_addr);
chksum += wval;
*wbuf = wval;
}
/* checksum field is not counted in the checksum */
*wbuf = adw_eeprom_read_16(adw, eep_addr);
wbuf++;
/* Driver seeprom variables are not included in the checksum */
for (eep_addr = ADW_EEP_DVC_CTL_BEGIN;
eep_addr < ADW_EEP_MAX_WORD_ADDR;
eep_addr++, wbuf++)
*wbuf = adw_eeprom_read_16(adw, eep_addr);
return (chksum);
}
void
adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *eep_buf)
{
u_int16_t *wbuf;
u_int16_t addr;
u_int16_t chksum;
wbuf = (u_int16_t *)eep_buf;
chksum = 0;
adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_ABLE);
adw_eeprom_wait(adw);
/*
* Write EEPROM until checksum.
*/
for (addr = ADW_EEP_DVC_CFG_BEGIN;
addr < ADW_EEP_DVC_CFG_END; addr++, wbuf++) {
chksum += *wbuf;
adw_eeprom_write_16(adw, addr, *wbuf);
}
/*
* Write calculated EEPROM checksum
*/
adw_eeprom_write_16(adw, addr, chksum);
/* skip over buffer's checksum */
wbuf++;
/*
* Write the rest.
*/
for (addr = ADW_EEP_DVC_CTL_BEGIN;
addr < ADW_EEP_MAX_WORD_ADDR; addr++, wbuf++)
adw_eeprom_write_16(adw, addr, *wbuf);
adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_DISABLE);
adw_eeprom_wait(adw);
}
int
adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1)
{
u_int8_t biosmem[ADW_MC_BIOSLEN];
u_int16_t *mcodebuf;
u_int addr;
u_int end_addr;
u_int checksum;
u_int scsicfg1;
u_int i;
/*
* Save the RISC memory BIOS region before writing the microcode.
* The BIOS may already be loaded and using its RISC LRAM region
* so its region must be saved and restored.
*/
for (addr = 0; addr < ADW_MC_BIOSLEN; addr++)
biosmem[addr] = adw_lram_read_8(adw, ADW_MC_BIOSMEM + addr);
/*
* Load the Microcode. Casting here was less work than
* reformatting the supplied microcode into an array of
* 16bit values...
*/
mcodebuf = (u_int16_t *)adw_mcode;
adw_outw(adw, ADW_RAM_ADDR, 0);
for (addr = 0; addr < adw_mcode_size/2; addr++)
adw_outw(adw, ADW_RAM_DATA, mcodebuf[addr]);
/*
* Clear the rest of LRAM.
*/
for (; addr < ADW_CONDOR_MEMSIZE/2; addr++)
adw_outw(adw, ADW_RAM_DATA, 0);
/*
* Verify the microcode checksum.
*/
checksum = 0;
adw_outw(adw, ADW_RAM_ADDR, 0);
for (addr = 0; addr < adw_mcode_size/2; addr++)
checksum += adw_inw(adw, ADW_RAM_DATA);
if (checksum != adw_mcode_chksum) {
printf("%s: Firmware load failed!\n", adw_name(adw));
return (-1);
}
/*
* Restore the RISC memory BIOS region.
*/
for (addr = 0; addr < ADW_MC_BIOSLEN; addr++)
adw_lram_write_8(adw, addr + ADW_MC_BIOSLEN, biosmem[addr]);
/*
* Calculate and write the microcode code checksum to
* the microcode code checksum location.
*/
addr = adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR) / 2;
end_addr = adw_lram_read_16(adw, ADW_MC_CODE_END_ADDR) / 2;
checksum = 0;
for (; addr < end_addr; addr++)
checksum += mcodebuf[addr];
adw_lram_write_16(adw, ADW_MC_CODE_CHK_SUM, checksum);
/*
* Initialize microcode operating variables
*/
adw_lram_write_16(adw, ADW_MC_ADAPTER_SCSI_ID, adw->initiator_id);
/*
* Leave WDTR and SDTR negotiation disabled until the XPT has
* informed us of device capabilities, but do set the ultra mask
* in case we receive an SDTR request from the target before we
* negotiate. We turn on tagged queuing at the microcode level
* for all devices, and modulate this on a per command basis.
*/
adw_lram_write_16(adw, ADW_MC_ULTRA_ABLE, adw->user_ultra);
adw_lram_write_16(adw, ADW_MC_DISC_ENABLE, adw->user_discenb);
adw_lram_write_16(adw, ADW_MC_TAGQNG_ABLE, ~0);
/*
* Set SCSI_CFG0 Microcode Default Value.
*
* The microcode will set the SCSI_CFG0 register using this value
* after it is started.
*/
adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG0,
ADW_SCSI_CFG0_PARITY_EN|ADW_SCSI_CFG0_SEL_TMO_LONG|
ADW_SCSI_CFG0_OUR_ID_EN|adw->initiator_id);
/*
* Determine SCSI_CFG1 Microcode Default Value.
*
* The microcode will set the SCSI_CFG1 register using this value
* after it is started below.
*/
scsicfg1 = adw_inw(adw, ADW_SCSI_CFG1);
/*
* If all three connectors are in use, return an error.
*/
if ((scsicfg1 & ADW_SCSI_CFG1_ILLEGAL_CABLE_CONF_A_MASK) == 0
|| (scsicfg1 & ADW_SCSI_CFG1_ILLEGAL_CABLE_CONF_B_MASK) == 0) {
printf("%s: Illegal Cable Config!\n", adw_name(adw));
printf("%s: Only Two Ports may be used at a time!\n",
adw_name(adw));
return (-1);
}
/*
* If the internal narrow cable is reversed all of the SCSI_CTRL
* register signals will be set. Check for and return an error if
* this condition is found.
*/
if ((adw_inw(adw, ADW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
printf("%s: Illegal Cable Config!\n", adw_name(adw));
printf("%s: Internal cable is reversed!\n", adw_name(adw));
return (-1);
}
/*
* If this is a differential board and a single-ended device
* is attached to one of the connectors, return an error.
*/
if ((scsicfg1 & ADW_SCSI_CFG1_DIFF_MODE) != 0
&& (scsicfg1 & ADW_SCSI_CFG1_DIFF_SENSE) == 0) {
printf("%s: A Single Ended Device is attached to our "
"differential bus!\n", adw_name(adw));
return (-1);
}
/*
* Perform automatic termination control if desired.
*/
if (term_scsicfg1 == 0) {
switch(scsicfg1 & ADW_SCSI_CFG1_CABLE_DETECT) {
case (ADW_SCSI_CFG1_INT16_MASK|ADW_SCSI_CFG1_INT8_MASK):
case (ADW_SCSI_CFG1_INT16_MASK|
ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_EXT8_MASK):
case (ADW_SCSI_CFG1_INT16_MASK|
ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_EXT16_MASK):
case (ADW_SCSI_CFG1_INT16_MASK|
ADW_SCSI_CFG1_EXT8_MASK|ADW_SCSI_CFG1_EXT16_MASK):
case (ADW_SCSI_CFG1_INT8_MASK|
ADW_SCSI_CFG1_EXT8_MASK|ADW_SCSI_CFG1_EXT16_MASK):
case (ADW_SCSI_CFG1_INT16_MASK|ADW_SCSI_CFG1_INT8_MASK|
ADW_SCSI_CFG1_EXT8_MASK|ADW_SCSI_CFG1_EXT16_MASK):
/* Two out of three cables missing. Both on. */
term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_L
| ADW_SCSI_CFG1_TERM_CTL_H;
break;
case (ADW_SCSI_CFG1_INT16_MASK):
case (ADW_SCSI_CFG1_INT16_MASK|ADW_SCSI_CFG1_EXT8_MASK):
case (ADW_SCSI_CFG1_INT16_MASK|ADW_SCSI_CFG1_EXT16_MASK):
case (ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_EXT16_MASK):
case (ADW_SCSI_CFG1_EXT8_MASK|ADW_SCSI_CFG1_EXT16_MASK):
/* No two 16bit cables present. High on. */
term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
break;
case (ADW_SCSI_CFG1_INT8_MASK):
case (ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_EXT8_MASK):
/* Wide -> Wide or Narrow -> Wide. Both off */
break;
}
}
/* Tell the user about our decission */
switch (term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) {
case ADW_SCSI_CFG1_TERM_CTL_MASK:
printf("High & Low Termination Enabled, ");
break;
case ADW_SCSI_CFG1_TERM_CTL_H:
printf("High Termination Enabled, ");
break;
case ADW_SCSI_CFG1_TERM_CTL_L:
printf("Low Termination Enabled, ");
break;
default:
break;
}
/*
* Invert the TERM_CTL_H and TERM_CTL_L bits and then
* set 'scsicfg1'. The TERM_POL bit does not need to be
* referenced, because the hardware internally inverts
* the Termination High and Low bits if TERM_POL is set.
*/
term_scsicfg1 = ~term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK;
scsicfg1 &= ~ADW_SCSI_CFG1_TERM_CTL_MASK;
scsicfg1 |= term_scsicfg1 | ADW_SCSI_CFG1_TERM_CTL_MANUAL;
/*
* Set SCSI_CFG1 Microcode Default Value
*
* Set filter value and possibly modified termination control
* bits in the Microcode SCSI_CFG1 Register Value.
*
* The microcode will set the SCSI_CFG1 register using this value
* after it is started below.
*/
adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG1,
scsicfg1 | ADW_SCSI_CFG1_FLTR_11_TO_20NS);
/*
* Only accept selections on our initiator target id.
* This may change in target mode scenarios...
*/
adw_lram_write_16(adw, ADW_MC_DEFAULT_SEL_MASK,
(0x01 << adw->initiator_id));
/*
* Link all the RISC Queue Lists together in a doubly-linked
* NULL terminated list.
*
* Skip the NULL (0) queue which is not used.
*/
for (i = 1, addr = ADW_MC_RISC_Q_LIST_BASE + ADW_MC_RISC_Q_LIST_SIZE;
i < ADW_MC_RISC_Q_TOTAL_CNT;
i++, addr += ADW_MC_RISC_Q_LIST_SIZE) {
/*
* Set the current RISC Queue List's
* RQL_FWD and RQL_BWD pointers in a
* one word write and set the state
* (RQL_STATE) to free.
*/
adw_lram_write_16(adw, addr, ((i + 1) | ((i - 1) << 8)));
adw_lram_write_8(adw, addr + RQL_STATE, ADW_MC_QS_FREE);
}
/*
* Set the Host and RISC Queue List pointers.
*
* Both sets of pointers are initialized with the same values:
* ADW_MC_RISC_Q_FIRST(0x01) and ADW_MC_RISC_Q_LAST (0xFF).
*/
adw_lram_write_8(adw, ADW_MC_HOST_NEXT_READY, ADW_MC_RISC_Q_FIRST);
adw_lram_write_8(adw, ADW_MC_HOST_NEXT_DONE, ADW_MC_RISC_Q_LAST);
adw_lram_write_8(adw, ADW_MC_RISC_NEXT_READY, ADW_MC_RISC_Q_FIRST);
adw_lram_write_8(adw, ADW_MC_RISC_NEXT_DONE, ADW_MC_RISC_Q_LAST);
/*
* Set up the last RISC Queue List (255) with a NULL forward pointer.
*/
adw_lram_write_16(adw, addr, (ADW_MC_NULL_Q + ((i - 1) << 8)));
adw_lram_write_8(adw, addr + RQL_STATE, ADW_MC_QS_FREE);
adw_outb(adw, ADW_INTR_ENABLES,
ADW_INTR_ENABLE_HOST_INTR|ADW_INTR_ENABLE_GLOBAL_INTR);
adw_outw(adw, ADW_PC, adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR));
return (0);
}
/*
* Send an idle command to the chip and optionally wait for completion.
*/
void
adw_idle_cmd_send(struct adw_softc *adw, adw_idle_cmd_t cmd, u_int parameter)
{
int s;
adw->idle_command_cmp = 0;
s = splcam();
if (adw->idle_cmd != ADW_IDLE_CMD_COMPLETED)
printf("%s: Warning! Overlapped Idle Commands Attempted\n",
adw_name(adw));
adw->idle_cmd = cmd;
adw->idle_cmd_param = parameter;
/*
* Write the idle command value after the idle command parameter
* has been written to avoid a race condition. If the order is not
* followed, the microcode may process the idle command before the
* parameters have been written to LRAM.
*/
adw_lram_write_16(adw, ADW_MC_IDLE_PARA_STAT, parameter);
adw_lram_write_16(adw, ADW_MC_IDLE_CMD, cmd);
splx(s);
}
/* Wait for an idle command to complete */
adw_idle_cmd_status_t
adw_idle_cmd_wait(struct adw_softc *adw)
{
u_int timeout;
adw_idle_cmd_status_t status;
int s;
/* Wait for up to 10 seconds for the command to complete */
timeout = 10000;
while (--timeout) {
if (adw->idle_command_cmp != 0)
break;
DELAY(1000);
}
if (timeout == 0)
panic("%s: Idle Command Timed Out!\n", adw_name(adw));
s = splcam();
status = adw_lram_read_16(adw, ADW_MC_IDLE_PARA_STAT);
splx(s);
return (status);
}

605
sys/dev/advansys/adwlib.h Normal file
View File

@ -0,0 +1,605 @@
/*
* Definitions for low level routines and data structures
* for the Advanced Systems Inc. SCSI controllers chips.
*
* Copyright (c) 1998 Justin T. Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id$
*/
/*
* Ported from:
* advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
*
* Copyright (c) 1995-1998 Advanced System Products, Inc.
* All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that redistributions of source
* code retain the above copyright notice and this comment without
* modification.
*/
#ifndef _ADWLIB_H_
#define _ADWLIB_H_
#include "opt_adw.h"
#include <stddef.h> /* for offsetof */
#include <dev/advansys/adwmcode.h>
#define ADW_DEF_MAX_HOST_QNG 253
#define ADW_DEF_MIN_HOST_QNG 16
#define ADW_DEF_MAX_DVC_QNG 63
#define ADW_DEF_MIN_DVC_QNG 4
#define ADW_MAX_TID 15
#define ADW_MAX_LUN 7
/*
* Board Register offsets.
*/
#define ADW_INTR_STATUS_REG 0x0000
#define ADW_INTR_STATUS_INTRA 0x01
#define ADW_INTR_STATUS_INTRB 0x02
#define ADW_INTR_STATUS_INTRC 0x04
#define ADW_SIGNATURE_WORD 0x0000
#define ADW_CHIP_ID_WORD 0x04C1
#define ADW_SIGNATURE_BYTE 0x0001
#define ADW_CHIP_ID_BYTE 0x25
#define ADW_INTR_ENABLES 0x0002 /*8 bit */
#define ADW_INTR_ENABLE_HOST_INTR 0x01
#define ADW_INTR_ENABLE_SEL_INTR 0x02
#define ADW_INTR_ENABLE_DPR_INTR 0x04
#define ADW_INTR_ENABLE_RTA_INTR 0x08
#define ADW_INTR_ENABLE_RMA_INTR 0x10
#define ADW_INTR_ENABLE_RST_INTR 0x20
#define ADW_INTR_ENABLE_DPE_INTR 0x40
#define ADW_INTR_ENABLE_GLOBAL_INTR 0x80
#define ADW_CTRL_REG 0x0002 /*16 bit*/
#define ADW_CTRL_REG_HOST_INTR 0x0100
#define ADW_CTRL_REG_SEL_INTR 0x0200
#define ADW_CTRL_REG_DPR_INTR 0x0400
#define ADW_CTRL_REG_RTA_INTR 0x0800
#define ADW_CTRL_REG_RMA_INTR 0x1000
#define ADW_CTRL_REG_RES_BIT14 0x2000
#define ADW_CTRL_REG_DPE_INTR 0x4000
#define ADW_CTRL_REG_POWER_DONE 0x8000
#define ADW_CTRL_REG_ANY_INTR 0xFF00
#define ADW_CTRL_REG_CMD_RESET 0x00C6
#define ADW_CTRL_REG_CMD_WR_IO_REG 0x00C5
#define ADW_CTRL_REG_CMD_RD_IO_REG 0x00C4
#define ADW_CTRL_REG_CMD_WR_PCI_CFG 0x00C3
#define ADW_CTRL_REG_CMD_RD_PCI_CFG 0x00C2
#define ADW_RAM_ADDR 0x0004
#define ADW_RAM_DATA 0x0006
#define ADW_RISC_CSR 0x000A
#define ADW_RISC_CSR_STOP 0x0000
#define ADW_RISC_TEST_COND 0x2000
#define ADW_RISC_CSR_RUN 0x4000
#define ADW_RISC_CSR_SINGLE_STEP 0x8000
#define ADW_SCSI_CFG0 0x000C
#define ADW_SCSI_CFG0_TIMER_MODEAB 0xC000 /*
* Watchdog, Second,
* and Selto timer CFG
*/
#define ADW_SCSI_CFG0_PARITY_EN 0x2000
#define ADW_SCSI_CFG0_EVEN_PARITY 0x1000
#define ADW_SCSI_CFG0_WD_LONG 0x0800 /*
* Watchdog Interval,
* 1: 57 min, 0: 13 sec
*/
#define ADW_SCSI_CFG0_QUEUE_128 0x0400 /*
* Queue Size,
* 1: 128 byte,
* 0: 64 byte
*/
#define ADW_SCSI_CFG0_PRIM_MODE 0x0100
#define ADW_SCSI_CFG0_SCAM_EN 0x0080
#define ADW_SCSI_CFG0_SEL_TMO_LONG 0x0040 /*
* Sel/Resel Timeout,
* 1: 400 ms,
* 0: 1.6 ms
*/
#define ADW_SCSI_CFG0_CFRM_ID 0x0020 /* SCAM id sel. */
#define ADW_SCSI_CFG0_OUR_ID_EN 0x0010
#define ADW_SCSI_CFG0_OUR_ID 0x000F
#define ADW_SCSI_CFG1 0x000E
#define ADW_SCSI_CFG1_BIG_ENDIAN 0x8000
#define ADW_SCSI_CFG1_TERM_POL 0x2000
#define ADW_SCSI_CFG1_SLEW_RATE 0x1000
#define ADW_SCSI_CFG1_FILTER_MASK 0x0C00
#define ADW_SCSI_CFG1_FLTR_DISABLE 0x0000
#define ADW_SCSI_CFG1_FLTR_11_TO_20NS 0x0800
#define ADW_SCSI_CFG1_FLTR_21_TO_39NS 0x0C00
#define ADW_SCSI_CFG1_DIS_ACTIVE_NEG 0x0200
#define ADW_SCSI_CFG1_DIFF_MODE 0x0100
#define ADW_SCSI_CFG1_DIFF_SENSE 0x0080
#define ADW_SCSI_CFG1_TERM_CTL_MANUAL 0x0040 /* Global Term Switch */
#define ADW_SCSI_CFG1_TERM_CTL_MASK 0x0030
#define ADW_SCSI_CFG1_TERM_CTL_H 0x0020 /* Enable SCSI-H */
#define ADW_SCSI_CFG1_TERM_CTL_L 0x0010 /* Enable SCSI-L */
#define ADW_SCSI_CFG1_CABLE_DETECT 0x000F
#define ADW_SCSI_CFG1_EXT16_MASK 0x0008 /* Ext16 cable pres */
#define ADW_SCSI_CFG1_EXT8_MASK 0x0004 /* Ext8 cable pres */
#define ADW_SCSI_CFG1_INT8_MASK 0x0002 /* Int8 cable pres */
#define ADW_SCSI_CFG1_INT16_MASK 0x0001 /* Int16 cable pres */
#define ADW_SCSI_CFG1_ILLEGAL_CABLE_CONF_A_MASK \
(ADW_SCSI_CFG1_EXT16_MASK|ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_INT16_MASK)
#define ADW_SCSI_CFG1_ILLEGAL_CABLE_CONF_B_MASK \
(ADW_SCSI_CFG1_EXT8_MASK|ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_INT16_MASK)
#define ADW_MEM_CFG 0x0010
#define ADW_MEM_CFG_BIOS_EN 0x40
#define ADW_MEM_CFG_FAST_EE_CLK 0x20 /* Diagnostic Bit */
#define ADW_MEM_CFG_RAM_SZ_MASK 0x1C /* RISC RAM Size */
#define ADW_MEM_CFG_RAM_SZ_2KB 0x00
#define ADW_MEM_CFG_RAM_SZ_4KB 0x04
#define ADW_MEM_CFG_RAM_SZ_8KB 0x08
#define ADW_MEM_CFG_RAM_SZ_16KB 0x0C
#define ADW_MEM_CFG_RAM_SZ_32KB 0x10
#define ADW_MEM_CFG_RAM_SZ_64KB 0x14
#define ADW_EEP_CMD 0x001A
#define ADW_EEP_CMD_READ 0x0080 /* or in address */
#define ADW_EEP_CMD_WRITE 0x0040 /* or in address */
#define ADW_EEP_CMD_WRITE_ABLE 0x0030
#define ADW_EEP_CMD_WRITE_DISABLE 0x0000
#define ADW_EEP_CMD_DONE 0x0200
#define ADW_EEP_CMD_DONE_ERR 0x0001
#define ADW_EEP_DELAY_MS 100
#define ADW_EEP_DATA 0x001C
#define ADW_DMA_CFG0 0x0020
#define ADW_DMA_CFG0_BC_THRESH_ENB 0x80
#define ADW_DMA_CFG0_FIFO_THRESH 0x70
#define ADW_DMA_CFG0_FIFO_THRESH_16B 0x00
#define ADW_DMA_CFG0_FIFO_THRESH_32B 0x20
#define ADW_DMA_CFG0_IFO_THRESH_48B 0x30
#define ADW_DMA_CFG0_IFO_THRESH_64B 0x40
#define ADW_DMA_CFG0_IFO_THRESH_80B 0x50
#define ADW_DMA_CFG0_IFO_THRESH_96B 0x60
#define ADW_DMA_CFG0_IFO_THRESH_112B 0x70
#define ADW_DMA_CFG0_START_CTL_MASK 0x0C
#define ADW_DMA_CFG0_START_CTL_TH 0x00 /* Start on thresh */
#define ADW_DMA_CFG0_START_CTL_IDLE 0x04 /* Start when idle */
#define ADW_DMA_CFG0_START_CTL_TH_IDLE 0x08 /* Either */
#define ADW_DMA_CFG0_START_CTL_EM_FU 0x0C /* Start on full/empty */
#define ADW_DMA_CFG0_READ_CMD_MASK 0x03
#define ADW_DMA_CFG0_READ_CMD_MR 0x00
#define ADW_DMA_CFG0_READ_CMD_MRL 0x02
#define ADW_DMA_CFG0_READ_CMD_MRM 0x03
/* Program Counter */
#define ADW_PC 0x2A
#define ADW_SCSI_CTRL 0x0034
#define ADW_SCSI_CTRL_RSTOUT 0x2000
#define ADW_SCSI_RESET_HOLD_TIME_US 60
/* LRAM Constants */
#define ADW_CONDOR_MEMSIZE 0x2000 /* 8 KB Internal Memory */
#define ADW_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
#define ADW_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
/* ====================== SCSI Request Structures =========================== */
#define ADW_NO_OF_SG_PER_BLOCK 15
/*
* Although the adapter can deal with S/G lists of indefinite size,
* we limit the list to 30 to conserve space as the kernel can only send
* us buffers of at most 64KB currently.
*/
#define ADW_SG_BLOCKCNT 2
#define ADW_SGSIZE (ADW_NO_OF_SG_PER_BLOCK * ADW_SG_BLOCKCNT)
struct adw_sg_elm {
u_int32_t sg_addr;
u_int32_t sg_count;
};
/* sg block structure used by the microcode */
struct adw_sg_block {
u_int8_t reserved1;
u_int8_t reserved2;
u_int8_t first_entry_no; /* starting entry number */
u_int8_t last_entry_no; /* last entry number */
u_int32_t sg_busaddr_next; /* link to the next sg block */
struct adw_sg_elm sg_list[ADW_NO_OF_SG_PER_BLOCK];
};
/* Structure representing a single allocation block of adw sg blocks */
struct sg_map_node {
bus_dmamap_t sg_dmamap;
bus_addr_t sg_physaddr;
struct adw_sg_block* sg_vaddr;
SLIST_ENTRY(sg_map_node) links;
};
typedef enum {
QHSTA_NO_ERROR = 0x00,
QHSTA_M_SEL_TIMEOUT = 0x11,
QHSTA_M_DATA_OVER_RUN = 0x12,
QHSTA_M_UNEXPECTED_BUS_FREE = 0x13,
QHSTA_M_QUEUE_ABORTED = 0x15,
QHSTA_M_SXFR_SDMA_ERR = 0x16, /* SCSI DMA Error */
QHSTA_M_SXFR_SXFR_PERR = 0x17, /* SCSI Bus Parity Error */
QHSTA_M_RDMA_PERR = 0x18, /* RISC PCI DMA parity error */
QHSTA_M_SXFR_OFF_UFLW = 0x19, /* Offset Underflow */
QHSTA_M_SXFR_OFF_OFLW = 0x20, /* Offset Overflow */
QHSTA_M_SXFR_WD_TMO = 0x21, /* Watchdog Timeout */
QHSTA_M_SXFR_DESELECTED = 0x22, /* Deselected */
QHSTA_M_SXFR_XFR_PH_ERR = 0x24, /* Transfer Phase Error */
QHSTA_M_SXFR_UNKNOWN_ERROR = 0x25, /* SXFR_STATUS Unknown Error */
QHSTA_M_WTM_TIMEOUT = 0x41,
QHSTA_M_BAD_CMPL_STATUS_IN = 0x42,
QHSTA_M_NO_AUTO_REQ_SENSE = 0x43,
QHSTA_M_AUTO_REQ_SENSE_FAIL = 0x44,
QHSTA_M_INVALID_DEVICE = 0x45 /* Bad target ID */
} host_status_t;
typedef enum {
QD_NO_STATUS = 0x00, /* Request not completed yet. */
QD_NO_ERROR = 0x01,
QD_ABORTED_BY_HOST = 0x02,
QD_WITH_ERROR = 0x04
} done_status_t;
/*
* Microcode request structure
*
* All fields in this structure are used by the microcode so their
* size and ordering cannot be changed.
*/
struct adw_scsi_req_q {
u_int8_t cntl; /* Ucode flags and state. */
u_int8_t sg_entry_cnt; /* SG element count. Zero for no SG. */
u_int8_t target_id; /* Device target identifier. */
u_int8_t target_lun; /* Device target logical unit number. */
u_int32_t data_addr; /* Data buffer physical address. */
u_int32_t data_cnt; /* Data count. Ucode sets to residual. */
u_int32_t sense_addr; /* Sense buffer physical address. */
u_int32_t srb_ptr; /* Driver request pointer. */
u_int8_t a_flag; /* Adv Library flag field. */
u_int8_t sense_len; /* Auto-sense length. Residual on complete. */
u_int8_t cdb_len; /* SCSI CDB length. */
u_int8_t tag_code; /* SCSI-2 Tag Queue Code: 00, 20-22. */
u_int8_t done_status; /* Completion status. */
u_int8_t scsi_status; /* SCSI status byte. */
u_int8_t host_status; /* Ucode host status. */
u_int8_t ux_sg_ix; /* Ucode working SG variable. */
u_int8_t cdb[12]; /* SCSI command block. */
u_int32_t sg_real_addr; /* SG list physical address. */
u_int32_t free_scsiq_link;/* Unused */
u_int32_t ux_wk_data_cnt; /* Saved data count at disconnection. */
u_int32_t scsi_req_baddr; /* Bus address of this request. */
u_int32_t sg_block_index; /* sg_block tag (Unused) */
};
typedef enum {
ACB_FREE = 0x00,
ACB_ACTIVE = 0x01,
ACB_RELEASE_SIMQ = 0x02
} acb_state;
struct acb {
struct adw_scsi_req_q queue;
bus_dmamap_t dmamap;
acb_state state;
union ccb *ccb;
struct adw_sg_block* sg_blocks;
bus_addr_t sg_busaddr;
struct scsi_sense_data sense_data;
SLIST_ENTRY(acb) links;
};
typedef struct {
u_int16_t bios_init_dis :1,/* don't act as initiator. */
bios_ext_trans :1,/* > 1 GB support */
bios_more_2disk :1,/* > 2 Disk Support */
bios_no_removable:1,/* don't support removables */
bios_cd_boot :1,/* support bootable CD */
:1,
bios_multi_lun :1,/* support multiple LUNs */
bios_message :1,/* display BIOS message */
:1,
bios_reset_sb :1,/* Reset SCSI bus during init. */
:1,
bios_quiet :1,/* No verbose initialization. */
bios_scsi_par_en :1,/* SCSI parity enabled */
:3;
} adw_bios_ctrl;
/*
* EEPROM configuration format
*
* Field naming convention:
*
* *_enable indicates the field enables or disables the feature. The
* value is never reset.
*
* *_able indicates both whether a feature should be enabled or disabled
* and whether a device is capable of the feature. At initialization
* this field may be set, but later if a device is found to be incapable
* of the feature, the field is cleared.
*
* Default values are maintained in a_init.c in the structure
* Default_EEPROM_Config.
*/
struct adw_eeprom
{
u_int16_t cfg_lsw; /* 00 power up initialization */
#define ADW_EEPROM_BIG_ENDIAN 0x8000
#define ADW_EEPROM_BIOS_ENABLE 0x4000
#define ADW_EEPROM_TERM_POL 0x2000
/* bit 13 set - Term Polarity Control */
/* bit 14 set - BIOS Enable */
/* bit 15 set - Big Endian Mode */
u_int16_t cfg_msw; /* unused */
u_int16_t disc_enable;
u_int16_t wdtr_able;
u_int16_t sdtr_able;
u_int16_t start_motor;
u_int16_t tagqng_able;
u_int16_t bios_scan;
u_int16_t scam_tolerant;
u_int8_t adapter_scsi_id;
u_int8_t bios_boot_delay;
u_int8_t scsi_reset_delay;
u_int8_t bios_id_lun; /* high nibble is lun */
/* low nibble is scsi id */
u_int8_t termination; /* 0 - automatic */
#define ADW_EEPROM_TERM_AUTO 0
#define ADW_EEPROM_TERM_OFF 1
#define ADW_EEPROM_TERM_HIGH_ON 2
#define ADW_EEPROM_TERM_BOTH_ON 3
u_int8_t reserved1; /* reserved byte (not used) */
adw_bios_ctrl bios_ctrl;
u_int16_t ultra_able; /* 13 ULTRA speed able */
u_int16_t reserved2; /* 14 reserved */
u_int8_t max_host_qng; /* 15 maximum host queuing */
u_int8_t max_dvc_qng; /* maximum per device queuing */
u_int16_t dvc_cntl; /* 16 control bit for driver */
u_int16_t bug_fix; /* 17 control bit for bug fix */
u_int16_t serial_number[3];
u_int16_t checksum;
u_int8_t oem_name[16];
u_int16_t dvc_err_code;
u_int16_t adv_err_code;
u_int16_t adv_err_addr;
u_int16_t saved_dvc_err_code;
u_int16_t saved_adv_err_code;
u_int16_t saved_adv_err_addr;
u_int16_t num_of_err;
};
/* EEProm Addresses */
#define ADW_EEP_DVC_CFG_BEGIN 0x00
#define ADW_EEP_DVC_CFG_END (offsetof(struct adw_eeprom, checksum)/2)
#define ADW_EEP_DVC_CTL_BEGIN (offsetof(struct adw_eeprom, oem_name)/2)
#define ADW_EEP_MAX_WORD_ADDR (sizeof(struct adw_eeprom)/2)
typedef enum {
ADW_STATE_NORMAL = 0x00,
ADW_RESOURCE_SHORTAGE = 0x01
} adw_state;
struct adw_softc
{
bus_space_tag_t tag;
bus_space_handle_t bsh;
adw_state state;
bus_dma_tag_t buffer_dmat;
struct acb *acbs;
LIST_HEAD(, ccb_hdr) pending_ccbs;
SLIST_HEAD(, acb) free_acb_list;
bus_dma_tag_t parent_dmat;
bus_dma_tag_t acb_dmat; /* dmat for our ccb array */
bus_dmamap_t acb_dmamap;
bus_dma_tag_t sg_dmat; /* dmat for our sg maps */
SLIST_HEAD(, sg_map_node) sg_maps;
bus_addr_t acb_busbase;
struct cam_path *path;
struct cam_sim *sim;
u_int max_acbs;
u_int num_acbs;
u_int initiator_id;
u_int init_level;
u_int unit;
char* name;
cam_status last_reset; /* Last reset type */
adw_bios_ctrl bios_ctrl;
adw_idle_cmd_t idle_cmd;
u_int idle_cmd_param;
volatile int idle_command_cmp;
u_int16_t user_wdtr;
u_int16_t user_sdtr;
u_int16_t user_ultra;
u_int16_t user_tagenb;
u_int16_t tagenb;
u_int16_t user_discenb;
u_int16_t serial_number[3];
};
extern struct adw_eeprom adw_default_eeprom;
#define adw_inb(adw, port) \
bus_space_read_1((adw)->tag, (adw)->bsh, port)
#define adw_inw(adw, port) \
bus_space_read_2((adw)->tag, (adw)->bsh, port)
#define adw_inl(adw, port) \
bus_space_read_4((adw)->tag, (adw)->bsh, port)
#define adw_outb(adw, port, value) \
bus_space_write_1((adw)->tag, (adw)->bsh, port, value)
#define adw_outw(adw, port, value) \
bus_space_write_2((adw)->tag, (adw)->bsh, port, value)
#define adw_outl(adw, port, value) \
bus_space_write_4((adw)->tag, (adw)->bsh, port, value)
static __inline const char* adw_name(struct adw_softc *adw);
static __inline u_int adw_lram_read_8(struct adw_softc *adw, u_int addr);
static __inline u_int adw_lram_read_16(struct adw_softc *adw, u_int addr);
static __inline u_int adw_lram_read_32(struct adw_softc *adw, u_int addr);
static __inline void adw_lram_write_8(struct adw_softc *adw, u_int addr,
u_int value);
static __inline void adw_lram_write_16(struct adw_softc *adw, u_int addr,
u_int value);
static __inline void adw_lram_write_32(struct adw_softc *adw, u_int addr,
u_int value);
static __inline const char*
adw_name(struct adw_softc *adw)
{
return (adw->name);
}
static __inline u_int
adw_lram_read_8(struct adw_softc *adw, u_int addr)
{
adw_outw(adw, ADW_RAM_ADDR, addr);
return (adw_inb(adw, ADW_RAM_DATA));
}
static __inline u_int
adw_lram_read_16(struct adw_softc *adw, u_int addr)
{
adw_outw(adw, ADW_RAM_ADDR, addr);
return (adw_inw(adw, ADW_RAM_DATA));
}
static __inline u_int
adw_lram_read_32(struct adw_softc *adw, u_int addr)
{
u_int retval;
adw_outw(adw, ADW_RAM_ADDR, addr);
retval = adw_inw(adw, ADW_RAM_DATA);
retval |= (adw_inw(adw, ADW_RAM_DATA) << 16);
return (retval);
}
static __inline void
adw_lram_write_8(struct adw_softc *adw, u_int addr, u_int value)
{
adw_outw(adw, ADW_RAM_ADDR, addr);
adw_outb(adw, ADW_RAM_DATA, value);
}
static __inline void
adw_lram_write_16(struct adw_softc *adw, u_int addr, u_int value)
{
adw_outw(adw, ADW_RAM_ADDR, addr);
adw_outw(adw, ADW_RAM_DATA, value);
}
static __inline void
adw_lram_write_32(struct adw_softc *adw, u_int addr, u_int value)
{
adw_outw(adw, ADW_RAM_ADDR, addr);
adw_outw(adw, ADW_RAM_DATA, value);
adw_outw(adw, ADW_RAM_DATA, value >> 16);
}
/* Intialization */
int adw_find_signature(bus_space_tag_t tag, bus_space_handle_t bsh);
void adw_reset_chip(struct adw_softc *adw);
u_int16_t adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *buf);
void adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *buf);
int adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1);
/* Idle Commands */
void adw_idle_cmd_send(struct adw_softc *adw, u_int cmd,
u_int parameter);
adw_idle_cmd_status_t adw_idle_cmd_wait(struct adw_softc *adw);
/* SCSI Transaction Processing */
static __inline void adw_send_acb(struct adw_softc *adw, struct acb *acb,
u_int32_t acb_baddr);
static __inline void
adw_send_acb(struct adw_softc *adw, struct acb *acb, u_int32_t acb_baddr)
{
u_int next_queue;
/* Determine the next free queue. */
next_queue = adw_lram_read_8(adw, ADW_MC_HOST_NEXT_READY);
next_queue = ADW_MC_RISC_Q_LIST_BASE
+ (next_queue * ADW_MC_RISC_Q_LIST_SIZE);
/*
* Write the physical address of the host Q to the free Q.
*/
adw_lram_write_32(adw, next_queue + RQL_PHYADDR, acb_baddr);
adw_lram_write_8(adw, next_queue + RQL_TID, acb->queue.target_id);
/*
* Set the ADW_MC_HOST_NEXT_READY (0x128) microcode variable to
* the 'next_queue' request forward pointer.
*
* Do this *before* changing the 'next_queue' queue to QS_READY.
* After the state is changed to QS_READY 'RQL_FWD' will be changed
* by the microcode.
*
*/
adw_lram_write_8(adw, ADW_MC_HOST_NEXT_READY,
adw_lram_read_8(adw, next_queue + RQL_FWD));
/*
* Change the state of 'next_queue' request from QS_FREE to
* QS_READY which will cause the microcode to pick it up and
* execute it.
*
* Can't reference 'next_queue' after changing the request
* state to QS_READY. The microcode now owns the request.
*/
adw_lram_write_8(adw, next_queue + RQL_STATE, ADW_MC_QS_READY);
}
#endif /* _ADWLIB_H_ */

443
sys/dev/advansys/adwmcode.c Normal file
View File

@ -0,0 +1,443 @@
/*
* Downloadable microcode for Second Generation
* Advanced Systems Inc. SCSI controllers
*
* $Id$
*
* Obtained from:
* advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
*
* Copyright (c) 1995-1998 Advanced System Products, Inc.
* All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that redistributions of source
* code retain the above copyright notice and this comment without
* modification.
*
*/
#include <sys/param.h>
u_int8_t adw_mcode[] =
{
0x9C, 0xF0, 0x80, 0x01, 0x00, 0xF0, 0x44, 0x0A, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x72, 0x01, 0xD6, 0x11,
0x00, 0x00, 0x70, 0x01, 0x30, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x90, 0x10, 0x2D, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0xF7, 0x70, 0x01,
0x0C, 0x1C, 0x06, 0xF7, 0x02, 0x00, 0x00, 0xF2, 0xD6, 0x0A, 0x04,
0xF7, 0x70, 0x01, 0x06, 0xF7, 0x02, 0x00, 0x3E, 0x57, 0x3C, 0x56,
0x0C, 0x1C, 0x00, 0xFC, 0xA6, 0x00, 0x01, 0x58, 0xAA, 0x13, 0x20,
0xF0, 0xA6, 0x03, 0x06, 0xEC, 0xB9, 0x00, 0x0E, 0x47, 0x03, 0xE6,
0x10, 0x00, 0xCE, 0x45, 0x02, 0x13, 0x3E, 0x57, 0x06, 0xEA, 0xB9,
0x00, 0x47, 0x4B, 0x03, 0xF6, 0xE0, 0x00, 0x00, 0xF2, 0x68, 0x0A,
0x01, 0x48, 0x4E, 0x12, 0x03, 0xF6, 0xC0, 0x00, 0x00, 0xF2, 0x68,
0x0A, 0x41, 0x58, 0x03, 0xF6, 0xD0, 0x00, 0x00, 0xF2, 0x68, 0x0A,
0x49, 0x44, 0x59, 0xF0, 0x0A, 0x02, 0x03, 0xF6, 0xE0, 0x00, 0x00,
0xF2, 0x68, 0x0A, 0x44, 0x58, 0x00, 0xF2, 0xE2, 0x0D, 0x02, 0xCC,
0x4A, 0xE4, 0x01, 0x00, 0x55, 0xF0, 0x08, 0x03, 0x45, 0xF4, 0x02,
0x00, 0x83, 0x5A, 0x04, 0xCC, 0x01, 0x4A, 0x12, 0x12, 0x00, 0xF2,
0xE2, 0x0D, 0x00, 0xCD, 0x48, 0xE4, 0x01, 0x00, 0xE9, 0x13, 0x00,
0xF2, 0xC6, 0x0F, 0xFA, 0x10, 0x0E, 0x47, 0x03, 0xE6, 0x10, 0x00,
0xCE, 0x45, 0x02, 0x13, 0x3E, 0x57, 0xCE, 0x47, 0x97, 0x13, 0x04,
0xEC, 0xB4, 0x00, 0x00, 0xF2, 0xE2, 0x0D, 0x00, 0xCD, 0x48, 0xE4,
0x00, 0x00, 0x12, 0x12, 0x3E, 0x57, 0x06, 0xCC, 0x45, 0xF4, 0x02,
0x00, 0x83, 0x5A, 0x00, 0xCC, 0x00, 0xEA, 0xB4, 0x00, 0x92, 0x10,
0x00, 0xF0, 0x8C, 0x01, 0x43, 0xF0, 0x5C, 0x02, 0x44, 0xF0, 0x60,
0x02, 0x45, 0xF0, 0x64, 0x02, 0x46, 0xF0, 0x68, 0x02, 0x47, 0xF0,
0x6E, 0x02, 0x48, 0xF0, 0x9E, 0x02, 0xB9, 0x54, 0x62, 0x10, 0x00,
0x1C, 0x5A, 0x10, 0x02, 0x1C, 0x56, 0x10, 0x1E, 0x1C, 0x52, 0x10,
0x00, 0xF2, 0x1E, 0x11, 0x50, 0x10, 0x06, 0xFC, 0xA8, 0x00, 0x03,
0xF6, 0xBE, 0x00, 0x00, 0xF2, 0x4E, 0x0A, 0x8C, 0x10, 0x01, 0xF6,
0x01, 0x00, 0x01, 0xFA, 0xA8, 0x00, 0x00, 0xF2, 0x2C, 0x0B, 0x06,
0x10, 0xB9, 0x54, 0x01, 0xFA, 0xA8, 0x00, 0x03, 0xF6, 0xBE, 0x00,
0x00, 0xF2, 0x58, 0x0A, 0x01, 0xFC, 0xA8, 0x00, 0x20, 0x10, 0x58,
0x1C, 0x00, 0xF2, 0x1C, 0x0B, 0x5A, 0x1C, 0x01, 0xF6, 0x01, 0x00,
0x38, 0x54, 0x00, 0xFA, 0xA6, 0x00, 0x01, 0xFA, 0xA8, 0x00, 0x20,
0x1C, 0x00, 0xF0, 0x72, 0x01, 0x01, 0xF6, 0x01, 0x00, 0x38, 0x54,
0x00, 0xFA, 0xA6, 0x00, 0x01, 0xFA, 0xA8, 0x00, 0x20, 0x1C, 0x00,
0xF0, 0x80, 0x01, 0x03, 0xF6, 0xE0, 0x00, 0x00, 0xF2, 0x68, 0x0A,
0x01, 0x48, 0x0A, 0x13, 0x00, 0xF2, 0x38, 0x10, 0x00, 0xF2, 0x54,
0x0F, 0x24, 0x10, 0x03, 0xF6, 0xC0, 0x00, 0x00, 0xF2, 0x68, 0x0A,
0x02, 0xF6, 0xD0, 0x00, 0x02, 0x57, 0x03, 0x59, 0x01, 0xCC, 0x49,
0x44, 0x5B, 0xF0, 0x04, 0x03, 0x00, 0xF2, 0x9C, 0x0F, 0x00, 0xF0,
0x80, 0x01, 0x00, 0xF2, 0x14, 0x10, 0x0C, 0x1C, 0x02, 0x4B, 0xBF,
0x57, 0x9E, 0x43, 0x77, 0x57, 0x07, 0x4B, 0x20, 0xF0, 0xA6, 0x03,
0x40, 0x1C, 0x1E, 0xF0, 0x30, 0x03, 0x26, 0xF0, 0x2C, 0x03, 0xA0,
0xF0, 0x1A, 0x03, 0x11, 0xF0, 0xA6, 0x03, 0x12, 0x10, 0x9F, 0xF0,
0x3E, 0x03, 0x46, 0x1C, 0x82, 0xE7, 0x05, 0x00, 0x9E, 0xE7, 0x11,
0x00, 0x00, 0xF0, 0x06, 0x0A, 0x0C, 0x1C, 0x48, 0x1C, 0x46, 0x1C,
0x38, 0x54, 0x00, 0xEC, 0xBA, 0x00, 0x08, 0x44, 0x00, 0xEA, 0xBA,
0x00, 0x03, 0xF6, 0xC0, 0x00, 0x00, 0xF2, 0x68, 0x0A, 0x08, 0x44,
0x00, 0x4C, 0x82, 0xE7, 0x02, 0x00, 0x00, 0xF2, 0x12, 0x11, 0x00,
0xF2, 0x12, 0x11, 0x85, 0xF0, 0x70, 0x03, 0x00, 0xF2, 0x60, 0x0B,
0x06, 0xF0, 0x80, 0x03, 0x09, 0xF0, 0x24, 0x09, 0x1E, 0xF0, 0xFC,
0x09, 0x00, 0xF0, 0x02, 0x0A, 0x00, 0xFC, 0xBE, 0x00, 0x98, 0x57,
0x55, 0xF0, 0xAC, 0x04, 0x01, 0xE6, 0x0C, 0x00, 0x00, 0xF2, 0x4E,
0x0D, 0x00, 0xF2, 0x12, 0x11, 0x00, 0xF2, 0xBC, 0x11, 0x00, 0xF2,
0xC8, 0x11, 0x01, 0xF0, 0x7C, 0x02, 0x00, 0xF0, 0x8A, 0x02, 0x46,
0x1C, 0x0C, 0x1C, 0x67, 0x1B, 0xBF, 0x57, 0x77, 0x57, 0x02, 0x4B,
0x48, 0x1C, 0x32, 0x1C, 0x00, 0xF2, 0x92, 0x0D, 0x30, 0x1C, 0x96,
0xF0, 0xBC, 0x03, 0xB1, 0xF0, 0xC0, 0x03, 0x1E, 0xF0, 0xFC, 0x09,
0x85, 0xF0, 0x02, 0x0A, 0x00, 0xFC, 0xBE, 0x00, 0x98, 0x57, 0x14,
0x12, 0x01, 0xE6, 0x0C, 0x00, 0x00, 0xF2, 0x4E, 0x0D, 0x00, 0xF2,
0x12, 0x11, 0x01, 0xF0, 0x7C, 0x02, 0x00, 0xF0, 0x8A, 0x02, 0x03,
0xF6, 0xE0, 0x00, 0x00, 0xF2, 0x68, 0x0A, 0x01, 0x48, 0x55, 0xF0,
0x98, 0x04, 0x03, 0x82, 0x03, 0xFC, 0xA0, 0x00, 0x9B, 0x57, 0x40,
0x12, 0x69, 0x18, 0x00, 0xF2, 0x12, 0x11, 0x85, 0xF0, 0x42, 0x04,
0x69, 0x08, 0x00, 0xF2, 0x12, 0x11, 0x85, 0xF0, 0x02, 0x0A, 0x68,
0x08, 0x4C, 0x44, 0x28, 0x12, 0x44, 0x48, 0x03, 0xF6, 0xE0, 0x00,
0x00, 0xF2, 0x68, 0x0A, 0x45, 0x58, 0x00, 0xF2, 0xF6, 0x0D, 0x00,
0xCC, 0x01, 0x48, 0x55, 0xF0, 0x98, 0x04, 0x4C, 0x44, 0xEF, 0x13,
0x00, 0xF2, 0xC6, 0x0F, 0x00, 0xF2, 0x14, 0x10, 0x08, 0x10, 0x68,
0x18, 0x45, 0x5A, 0x00, 0xF2, 0xF6, 0x0D, 0x04, 0x80, 0x18, 0xE4,
0x10, 0x00, 0x28, 0x12, 0x01, 0xE6, 0x06, 0x00, 0x04, 0x80, 0x18,
0xE4, 0x01, 0x00, 0x04, 0x12, 0x01, 0xE6, 0x0D, 0x00, 0x00, 0xF2,
0x4E, 0x0D, 0x00, 0xF2, 0x12, 0x11, 0x04, 0xE6, 0x02, 0x00, 0x9E,
0xE7, 0x15, 0x00, 0x01, 0xF0, 0x1C, 0x0A, 0x00, 0xF0, 0x02, 0x0A,
0x69, 0x08, 0x05, 0x80, 0x48, 0xE4, 0x00, 0x00, 0x0C, 0x12, 0x00,
0xE6, 0x11, 0x00, 0x00, 0xEA, 0xB8, 0x00, 0x00, 0xF2, 0xB6, 0x10,
0x82, 0xE7, 0x02, 0x00, 0x1C, 0x90, 0x40, 0x5C, 0x00, 0x16, 0x01,
0xE6, 0x06, 0x00, 0x00, 0xF2, 0x4E, 0x0D, 0x01, 0xF0, 0x80, 0x01,
0x1E, 0xF0, 0x80, 0x01, 0x00, 0xF0, 0xA0, 0x04, 0x42, 0x5B, 0x06,
0xF7, 0x03, 0x00, 0x46, 0x59, 0xBF, 0x57, 0x77, 0x57, 0x01, 0xE6,
0x80, 0x00, 0x07, 0x80, 0x31, 0x44, 0x04, 0x80, 0x18, 0xE4, 0x20,
0x00, 0x56, 0x13, 0x20, 0x80, 0x48, 0xE4, 0x03, 0x00, 0x4E, 0x12,
0x00, 0xFC, 0xA2, 0x00, 0x98, 0x57, 0x55, 0xF0, 0x1C, 0x05, 0x31,
0xE4, 0x40, 0x00, 0x00, 0xFC, 0xA0, 0x00, 0x98, 0x57, 0x36, 0x12,
0x4C, 0x1C, 0x00, 0xF2, 0x12, 0x11, 0x89, 0x48, 0x00, 0xF2, 0x12,
0x11, 0x86, 0xF0, 0x2E, 0x05, 0x82, 0xE7, 0x06, 0x00, 0x1B, 0x80,
0x48, 0xE4, 0x22, 0x00, 0x5B, 0xF0, 0x0C, 0x05, 0x48, 0xE4, 0x20,
0x00, 0x59, 0xF0, 0x10, 0x05, 0x00, 0xE6, 0x20, 0x00, 0x09, 0x48,
0x00, 0xF2, 0x12, 0x11, 0x86, 0xF0, 0x2E, 0x05, 0x83, 0x80, 0x04,
0x10, 0x00, 0xF2, 0xA2, 0x0D, 0x00, 0xE6, 0x01, 0x00, 0x00, 0xEA,
0x26, 0x01, 0x01, 0xEA, 0x27, 0x01, 0x04, 0x80, 0x18, 0xE4, 0x10,
0x00, 0x36, 0x12, 0xB9, 0x54, 0x00, 0xF2, 0xF6, 0x0E, 0x01, 0xE6,
0x06, 0x00, 0x04, 0x80, 0x18, 0xE4, 0x01, 0x00, 0x04, 0x12, 0x01,
0xE6, 0x0D, 0x00, 0x00, 0xF2, 0x4E, 0x0D, 0x00, 0xF2, 0x12, 0x11,
0x00, 0xF2, 0xBC, 0x11, 0x00, 0xF2, 0xC8, 0x11, 0x04, 0xE6, 0x02,
0x00, 0x9E, 0xE7, 0x15, 0x00, 0x01, 0xF0, 0x1C, 0x0A, 0x00, 0xF0,
0x02, 0x0A, 0x00, 0xFC, 0x20, 0x01, 0x98, 0x57, 0x34, 0x12, 0x00,
0xFC, 0x24, 0x01, 0x98, 0x57, 0x2C, 0x13, 0xB9, 0x54, 0x00, 0xF2,
0xF6, 0x0E, 0x86, 0xF0, 0xA8, 0x05, 0x03, 0xF6, 0x01, 0x00, 0x00,
0xF2, 0x8C, 0x0E, 0x85, 0xF0, 0x9E, 0x05, 0x82, 0xE7, 0x03, 0x00,
0x00, 0xF2, 0x60, 0x0B, 0x82, 0xE7, 0x02, 0x00, 0x00, 0xFC, 0x24,
0x01, 0xB0, 0x57, 0x00, 0xFA, 0x24, 0x01, 0x00, 0xFC, 0x9E, 0x00,
0x98, 0x57, 0x5A, 0x12, 0x00, 0xFC, 0xB6, 0x00, 0x98, 0x57, 0x52,
0x13, 0x03, 0xE6, 0x0C, 0x00, 0x00, 0xFC, 0x9C, 0x00, 0x98, 0x57,
0x04, 0x13, 0x03, 0xE6, 0x19, 0x00, 0x05, 0xE6, 0x08, 0x00, 0x00,
0xF6, 0x00, 0x01, 0x00, 0x57, 0x00, 0x57, 0x03, 0x58, 0x00, 0xDC,
0x18, 0xF4, 0x00, 0x80, 0x04, 0x13, 0x05, 0xE6, 0x0F, 0x00, 0xB9,
0x54, 0x00, 0xF2, 0xF6, 0x0E, 0x86, 0xF0, 0x0A, 0x06, 0x00, 0xF2,
0xBA, 0x0E, 0x85, 0xF0, 0x00, 0x06, 0x82, 0xE7, 0x03, 0x00, 0x00,
0xF2, 0x60, 0x0B, 0x82, 0xE7, 0x02, 0x00, 0x00, 0xFC, 0xB6, 0x00,
0xB0, 0x57, 0x00, 0xFA, 0xB6, 0x00, 0x01, 0xF6, 0x01, 0x00, 0x00,
0xF2, 0xF6, 0x0E, 0x9C, 0x32, 0x4E, 0x1C, 0x32, 0x1C, 0x00, 0xF2,
0x92, 0x0D, 0x30, 0x1C, 0x82, 0xE7, 0x04, 0x00, 0xB1, 0xF0, 0x22,
0x06, 0x0A, 0xF0, 0x3E, 0x06, 0x05, 0xF0, 0xD6, 0x06, 0x06, 0xF0,
0xDC, 0x06, 0x09, 0xF0, 0x24, 0x09, 0x1E, 0xF0, 0xFC, 0x09, 0x00,
0xF0, 0x02, 0x0A, 0x04, 0x80, 0x18, 0xE4, 0x20, 0x00, 0x30, 0x12,
0x09, 0xE7, 0x03, 0x00, 0x00, 0xF2, 0x12, 0x11, 0x21, 0x80, 0x18,
0xE4, 0xE0, 0x00, 0x09, 0x48, 0x00, 0xF2, 0x12, 0x11, 0x09, 0xE7,
0x00, 0x00, 0x00, 0xF2, 0x12, 0x11, 0x09, 0xE7, 0x00, 0x00, 0x00,
0xF2, 0x12, 0x11, 0x99, 0xA4, 0x00, 0xF2, 0x12, 0x11, 0x09, 0xE7,
0x00, 0x00, 0x9A, 0x10, 0x04, 0x80, 0x18, 0xE4, 0x02, 0x00, 0x34,
0x12, 0x09, 0xE7, 0x1B, 0x00, 0x00, 0xF2, 0x12, 0x11, 0x21, 0x80,
0x18, 0xE4, 0xE0, 0x00, 0x09, 0x48, 0x00, 0xF2, 0x12, 0x11, 0x09,
0xE7, 0x00, 0x00, 0x00, 0xF2, 0x12, 0x11, 0x09, 0xE7, 0x00, 0x00,
0x00, 0xF2, 0x12, 0x11, 0x09, 0xE7, 0x01, 0x00, 0x00, 0xF2, 0x12,
0x11, 0x09, 0xE7, 0x00, 0x00, 0x00, 0xF0, 0x0C, 0x09, 0xBB, 0x55,
0x9A, 0x81, 0x03, 0xF7, 0x20, 0x00, 0x09, 0x6F, 0x93, 0x45, 0x55,
0xF0, 0xE2, 0x06, 0xB1, 0xF0, 0xC2, 0x06, 0x0A, 0xF0, 0xBA, 0x06,
0x09, 0xF0, 0x24, 0x09, 0x1E, 0xF0, 0xFC, 0x09, 0x00, 0xF0, 0x02,
0x0A, 0x00, 0xF2, 0x60, 0x0B, 0x47, 0x10, 0x09, 0xE7, 0x08, 0x00,
0x41, 0x10, 0x05, 0x80, 0x48, 0xE4, 0x00, 0x00, 0x1E, 0x12, 0x00,
0xE6, 0x11, 0x00, 0x00, 0xEA, 0xB8, 0x00, 0x00, 0xF2, 0xB6, 0x10,
0x2C, 0x90, 0xAE, 0x90, 0x08, 0x50, 0x8A, 0x50, 0x38, 0x54, 0x1F,
0x40, 0x00, 0xF2, 0xB4, 0x0D, 0x08, 0x10, 0x08, 0x90, 0x8A, 0x90,
0x30, 0x50, 0xB2, 0x50, 0x9C, 0x32, 0x0C, 0x92, 0x8E, 0x92, 0x38,
0x54, 0x04, 0x80, 0x30, 0xE4, 0x08, 0x00, 0x04, 0x40, 0x0C, 0x1C,
0x00, 0xF6, 0x03, 0x00, 0xB1, 0xF0, 0x26, 0x07, 0x9E, 0xF0, 0x3A,
0x07, 0x01, 0x48, 0x55, 0xF0, 0xFC, 0x09, 0x0C, 0x1C, 0x10, 0x44,
0xED, 0x10, 0x0B, 0xF0, 0x5E, 0x07, 0x0C, 0xF0, 0x62, 0x07, 0x05,
0xF0, 0x52, 0x07, 0x06, 0xF0, 0x58, 0x07, 0x09, 0xF0, 0x24, 0x09,
0x00, 0xF0, 0x02, 0x0A, 0x00, 0xF2, 0x60, 0x0B, 0xCF, 0x10, 0x09,
0xE7, 0x08, 0x00, 0xC9, 0x10, 0x2E, 0x1C, 0x02, 0x10, 0x2C, 0x1C,
0xAA, 0xF0, 0x64, 0x07, 0xAC, 0xF0, 0x72, 0x07, 0x40, 0x10, 0x34,
0x1C, 0xF3, 0x10, 0xAD, 0xF0, 0x7C, 0x07, 0xC8, 0x10, 0x36, 0x1C,
0xE9, 0x10, 0x2B, 0xF0, 0x82, 0x08, 0x6B, 0x18, 0x18, 0xF4, 0x00,
0xFE, 0x20, 0x12, 0x01, 0x58, 0xD2, 0xF0, 0x82, 0x08, 0x76, 0x18,
0x18, 0xF4, 0x03, 0x00, 0xEC, 0x12, 0x00, 0xFC, 0x22, 0x01, 0x18,
0xF4, 0x01, 0x00, 0xE2, 0x12, 0x0B, 0xF0, 0x64, 0x07, 0x0C, 0xF0,
0x64, 0x07, 0x36, 0x1C, 0x34, 0x1C, 0xB7, 0x10, 0x38, 0x54, 0xB9,
0x54, 0x84, 0x80, 0x19, 0xE4, 0x20, 0x00, 0xB2, 0x13, 0x85, 0x80,
0x81, 0x48, 0x66, 0x12, 0x04, 0x80, 0x18, 0xE4, 0x08, 0x00, 0x58,
0x13, 0x1F, 0x80, 0x08, 0x44, 0xC8, 0x44, 0x9F, 0x12, 0x1F, 0x40,
0x34, 0x91, 0xB6, 0x91, 0x44, 0x55, 0xE5, 0x55, 0x02, 0xEC, 0xB8,
0x00, 0x02, 0x49, 0xBB, 0x55, 0x82, 0x81, 0xC0, 0x55, 0x48, 0xF4,
0x0F, 0x00, 0x5A, 0xF0, 0x1A, 0x08, 0x4A, 0xE4, 0x17, 0x00, 0xD5,
0xF0, 0xFA, 0x07, 0x02, 0xF6, 0x0F, 0x00, 0x02, 0xF4, 0x02, 0x00,
0x02, 0xEA, 0xB8, 0x00, 0x04, 0x91, 0x86, 0x91, 0x02, 0x4B, 0x2C,
0x90, 0x08, 0x50, 0x2E, 0x90, 0x0A, 0x50, 0x2C, 0x51, 0xAE, 0x51,
0x00, 0xF2, 0xB6, 0x10, 0x38, 0x54, 0x00, 0xF2, 0xB4, 0x0D, 0x56,
0x10, 0x34, 0x91, 0xB6, 0x91, 0x0C, 0x10, 0x04, 0x80, 0x18, 0xE4,
0x08, 0x00, 0x41, 0x12, 0x0C, 0x91, 0x8E, 0x91, 0x04, 0x80, 0x18,
0xE4, 0xF7, 0x00, 0x04, 0x40, 0x30, 0x90, 0xB2, 0x90, 0x36, 0x10,
0x02, 0x80, 0x48, 0xE4, 0x10, 0x00, 0x31, 0x12, 0x82, 0xE7, 0x10,
0x00, 0x84, 0x80, 0x19, 0xE4, 0x20, 0x00, 0x10, 0x13, 0x0C, 0x90,
0x8E, 0x90, 0x5D, 0xF0, 0x78, 0x07, 0x0C, 0x58, 0x8D, 0x58, 0x00,
0xF0, 0x64, 0x07, 0x38, 0x54, 0xB9, 0x54, 0x19, 0x80, 0xF1, 0x10,
0x3A, 0x55, 0x19, 0x81, 0xBB, 0x55, 0x10, 0x90, 0x92, 0x90, 0x10,
0x58, 0x91, 0x58, 0x14, 0x59, 0x95, 0x59, 0x00, 0xF0, 0x64, 0x07,
0x04, 0x80, 0x18, 0xE4, 0x20, 0x00, 0x06, 0x12, 0x6C, 0x19, 0x19,
0x41, 0x7C, 0x10, 0x6C, 0x19, 0x0C, 0x51, 0xED, 0x19, 0x8E, 0x51,
0x6B, 0x18, 0x18, 0xF4, 0x00, 0xFF, 0x02, 0x13, 0x6A, 0x10, 0x01,
0x58, 0xD2, 0xF0, 0xC0, 0x08, 0x76, 0x18, 0x18, 0xF4, 0x03, 0x00,
0x0A, 0x12, 0x00, 0xFC, 0x22, 0x01, 0x18, 0xF4, 0x01, 0x00, 0x06,
0x13, 0x9E, 0xE7, 0x16, 0x00, 0x4C, 0x10, 0xD1, 0xF0, 0xCA, 0x08,
0x9E, 0xE7, 0x17, 0x00, 0x42, 0x10, 0xD0, 0xF0, 0xD4, 0x08, 0x9E,
0xE7, 0x19, 0x00, 0x38, 0x10, 0xCF, 0xF0, 0xDE, 0x08, 0x9E, 0xE7,
0x20, 0x00, 0x2E, 0x10, 0xCE, 0xF0, 0xE8, 0x08, 0x9E, 0xE7, 0x21,
0x00, 0x24, 0x10, 0xCD, 0xF0, 0xF2, 0x08, 0x9E, 0xE7, 0x22, 0x00,
0x1A, 0x10, 0xCC, 0xF0, 0x04, 0x09, 0x84, 0x80, 0x19, 0xE4, 0x04,
0x00, 0x06, 0x12, 0x9E, 0xE7, 0x12, 0x00, 0x08, 0x10, 0xCB, 0xF0,
0x0C, 0x09, 0x9E, 0xE7, 0x24, 0x00, 0xB1, 0xF0, 0x0C, 0x09, 0x05,
0xF0, 0x1E, 0x09, 0x09, 0xF0, 0x24, 0x09, 0x1E, 0xF0, 0xFC, 0x09,
0xE4, 0x10, 0x00, 0xF2, 0x60, 0x0B, 0xE9, 0x10, 0x9C, 0x32, 0x82,
0xE7, 0x20, 0x00, 0x32, 0x1C, 0xE9, 0x09, 0x00, 0xF2, 0x12, 0x11,
0x85, 0xF0, 0x02, 0x0A, 0x69, 0x08, 0x01, 0xF0, 0x44, 0x09, 0x1E,
0xF0, 0xFC, 0x09, 0x00, 0xF0, 0x38, 0x09, 0x30, 0x44, 0x06, 0x12,
0x9E, 0xE7, 0x42, 0x00, 0xB8, 0x10, 0x04, 0xF6, 0x01, 0x00, 0xB3,
0x45, 0x74, 0x12, 0x04, 0x80, 0x18, 0xE4, 0x20, 0x00, 0x22, 0x13,
0x4B, 0xE4, 0x02, 0x00, 0x36, 0x12, 0x4B, 0xE4, 0x28, 0x00, 0xAC,
0x13, 0x00, 0xF2, 0xBC, 0x11, 0x00, 0xF2, 0xC8, 0x11, 0x03, 0xF6,
0xD0, 0x00, 0xFA, 0x14, 0x82, 0xE7, 0x01, 0x00, 0x00, 0xF0, 0x80,
0x01, 0x9E, 0xE7, 0x44, 0x00, 0x4B, 0xE4, 0x02, 0x00, 0x06, 0x12,
0x03, 0xE6, 0x02, 0x00, 0x76, 0x10, 0x00, 0xF2, 0xA2, 0x0D, 0x03,
0xE6, 0x02, 0x00, 0x6C, 0x10, 0x00, 0xF2, 0xA2, 0x0D, 0x19, 0x82,
0x34, 0x46, 0x0A, 0x13, 0x03, 0xE6, 0x02, 0x00, 0x9E, 0xE7, 0x43,
0x00, 0x68, 0x10, 0x04, 0x80, 0x30, 0xE4, 0x20, 0x00, 0x04, 0x40,
0x00, 0xF2, 0xBC, 0x11, 0x00, 0xF2, 0xC8, 0x11, 0x82, 0xE7, 0x01,
0x00, 0x06, 0xF7, 0x02, 0x00, 0x00, 0xF0, 0x08, 0x03, 0x04, 0x80,
0x18, 0xE4, 0x20, 0x00, 0x06, 0x12, 0x03, 0xE6, 0x02, 0x00, 0x3E,
0x10, 0x04, 0x80, 0x18, 0xE4, 0x02, 0x00, 0x3A, 0x12, 0x04, 0x80,
0x18, 0xE4, 0xFD, 0x00, 0x04, 0x40, 0x1C, 0x1C, 0x9D, 0xF0, 0xEA,
0x09, 0x1C, 0x1C, 0x9D, 0xF0, 0xF0, 0x09, 0xC1, 0x10, 0x9E, 0xE7,
0x13, 0x00, 0x0A, 0x10, 0x9E, 0xE7, 0x41, 0x00, 0x04, 0x10, 0x9E,
0xE7, 0x24, 0x00, 0x00, 0xFC, 0xBE, 0x00, 0x98, 0x57, 0xD5, 0xF0,
0x8A, 0x02, 0x04, 0xE6, 0x04, 0x00, 0x06, 0x10, 0x04, 0xE6, 0x04,
0x00, 0x9D, 0x41, 0x1C, 0x42, 0x9F, 0xE7, 0x00, 0x00, 0x06, 0xF7,
0x02, 0x00, 0x03, 0xF6, 0xE0, 0x00, 0x3C, 0x14, 0x44, 0x58, 0x45,
0x58, 0x00, 0xF2, 0xF6, 0x0D, 0x00, 0xF2, 0x7E, 0x10, 0x00, 0xF2,
0xC6, 0x0F, 0x3C, 0x14, 0x1E, 0x1C, 0x00, 0xF0, 0x80, 0x01, 0x12,
0x1C, 0x22, 0x1C, 0xD2, 0x14, 0x00, 0xF0, 0x72, 0x01, 0x83, 0x59,
0x03, 0xDC, 0x73, 0x57, 0x80, 0x5D, 0x00, 0x16, 0x83, 0x59, 0x03,
0xDC, 0x38, 0x54, 0x70, 0x57, 0x33, 0x54, 0x3B, 0x54, 0x80, 0x5D,
0x00, 0x16, 0x03, 0x57, 0x83, 0x59, 0x38, 0x54, 0x00, 0xCC, 0x00,
0x16, 0x03, 0x57, 0x83, 0x59, 0x00, 0x4C, 0x00, 0x16, 0x02, 0x80,
0x48, 0xE4, 0x01, 0x00, 0x0E, 0x12, 0x48, 0xE4, 0x05, 0x00, 0x08,
0x12, 0x00, 0xF2, 0xBC, 0x11, 0x00, 0xF2, 0xC8, 0x11, 0xC1, 0x5A,
0x3A, 0x55, 0x02, 0xEC, 0xB5, 0x00, 0x45, 0x59, 0x00, 0xF2, 0xF6,
0x0D, 0x83, 0x58, 0x30, 0xE7, 0x00, 0x00, 0x10, 0x4D, 0x30, 0xE7,
0x40, 0x00, 0x10, 0x4F, 0x38, 0x90, 0xBA, 0x90, 0x10, 0x5C, 0x80,
0x5C, 0x83, 0x5A, 0x10, 0x4E, 0x04, 0xEA, 0xB5, 0x00, 0x43, 0x5B,
0x03, 0xF4, 0xE0, 0x00, 0x83, 0x59, 0x04, 0xCC, 0x01, 0x4A, 0x0A,
0x12, 0x45, 0x5A, 0x00, 0xF2, 0xF6, 0x0D, 0x00, 0xF2, 0x38, 0x10,
0x00, 0x16, 0x08, 0x1C, 0x00, 0xFC, 0xAC, 0x00, 0x06, 0x58, 0x67,
0x18, 0x18, 0xF4, 0x8F, 0xE1, 0x01, 0xFC, 0xAE, 0x00, 0x19, 0xF4,
0x70, 0x1E, 0xB0, 0x54, 0x07, 0x58, 0x00, 0xFC, 0xB0, 0x00, 0x08,
0x58, 0x00, 0xFC, 0xB2, 0x00, 0x09, 0x58, 0x0A, 0x1C, 0x00, 0xE6,
0x0F, 0x00, 0x00, 0xEA, 0xB9, 0x00, 0x38, 0x54, 0x00, 0xFA, 0x24,
0x01, 0x00, 0xFA, 0xB6, 0x00, 0x18, 0x1C, 0x14, 0x1C, 0x10, 0x1C,
0x32, 0x1C, 0x12, 0x1C, 0x00, 0x16, 0x3E, 0x57, 0x0C, 0x14, 0x0E,
0x47, 0x07, 0xE6, 0x10, 0x00, 0xCE, 0x47, 0xF5, 0x13, 0x00, 0x16,
0x00, 0xF2, 0xA2, 0x0D, 0x02, 0x4B, 0x03, 0xF6, 0xE0, 0x00, 0x00,
0xF2, 0x68, 0x0A, 0x01, 0x48, 0x20, 0x12, 0x44, 0x58, 0x45, 0x58,
0x9E, 0xE7, 0x15, 0x00, 0x9C, 0xE7, 0x04, 0x00, 0x00, 0xF2, 0xF6,
0x0D, 0x00, 0xF2, 0x7E, 0x10, 0x00, 0xF2, 0xC6, 0x0F, 0x00, 0xF2,
0x7A, 0x0A, 0x1E, 0x1C, 0xD5, 0x10, 0x00, 0x16, 0x69, 0x08, 0x48,
0xE4, 0x04, 0x00, 0x64, 0x12, 0x48, 0xE4, 0x02, 0x00, 0x20, 0x12,
0x48, 0xE4, 0x03, 0x00, 0x1A, 0x12, 0x48, 0xE4, 0x08, 0x00, 0x14,
0x12, 0x48, 0xE4, 0x01, 0x00, 0xF0, 0x12, 0x48, 0xE4, 0x07, 0x00,
0x12, 0x12, 0x01, 0xE6, 0x07, 0x00, 0x00, 0xF2, 0x4E, 0x0D, 0x00,
0xF2, 0x12, 0x11, 0x05, 0xF0, 0x60, 0x0B, 0x00, 0x16, 0x00, 0xE6,
0x01, 0x00, 0x00, 0xEA, 0x99, 0x00, 0x02, 0x80, 0x48, 0xE4, 0x03,
0x00, 0xE7, 0x12, 0x48, 0xE4, 0x06, 0x00, 0xE1, 0x12, 0x01, 0xE6,
0x06, 0x00, 0x00, 0xF2, 0x4E, 0x0D, 0x00, 0xF2, 0x12, 0x11, 0x04,
0xE6, 0x02, 0x00, 0x9E, 0xE7, 0x15, 0x00, 0x01, 0xF0, 0x1C, 0x0A,
0x00, 0xF0, 0x02, 0x0A, 0x00, 0x16, 0x02, 0x80, 0x48, 0xE4, 0x10,
0x00, 0x1C, 0x12, 0x82, 0xE7, 0x08, 0x00, 0x3C, 0x56, 0x03, 0x82,
0x00, 0xF2, 0xE2, 0x0D, 0x30, 0xE7, 0x08, 0x00, 0x04, 0xF7, 0x70,
0x01, 0x06, 0xF7, 0x02, 0x00, 0x00, 0xF0, 0x80, 0x01, 0x6C, 0x19,
0xED, 0x19, 0x5D, 0xF0, 0xD4, 0x0B, 0x44, 0x55, 0xE5, 0x55, 0x59,
0xF0, 0x52, 0x0C, 0x04, 0x55, 0xA5, 0x55, 0x1F, 0x80, 0x01, 0xEC,
0xB8, 0x00, 0x82, 0x48, 0x82, 0x80, 0x49, 0x44, 0x2E, 0x13, 0x01,
0xEC, 0xB8, 0x00, 0x41, 0xE4, 0x02, 0x00, 0x01, 0xEA, 0xB8, 0x00,
0x49, 0xE4, 0x11, 0x00, 0x59, 0xF0, 0x2E, 0x0C, 0x01, 0xE6, 0x17,
0x00, 0x01, 0xEA, 0xB8, 0x00, 0x02, 0x4B, 0x88, 0x90, 0xAC, 0x50,
0x8A, 0x90, 0xAE, 0x50, 0x01, 0xEC, 0xB8, 0x00, 0x82, 0x48, 0x82,
0x80, 0x10, 0x44, 0x02, 0x4B, 0x1F, 0x40, 0xC0, 0x44, 0x00, 0xF2,
0xB4, 0x0D, 0x04, 0x55, 0xA5, 0x55, 0x9F, 0x10, 0x0C, 0x51, 0x8E,
0x51, 0x30, 0x90, 0xB2, 0x90, 0x00, 0x56, 0xA1, 0x56, 0x30, 0x50,
0xB2, 0x50, 0x34, 0x90, 0xB6, 0x90, 0x40, 0x56, 0xE1, 0x56, 0x34,
0x50, 0xB6, 0x50, 0x65, 0x10, 0xB1, 0xF0, 0x70, 0x0C, 0x85, 0xF0,
0xCA, 0x0B, 0xE9, 0x09, 0x4B, 0xE4, 0x03, 0x00, 0x78, 0x12, 0x4B,
0xE4, 0x02, 0x00, 0x01, 0x13, 0xB1, 0xF0, 0x86, 0x0C, 0x85, 0xF0,
0xCA, 0x0B, 0x69, 0x08, 0x48, 0xE4, 0x03, 0x00, 0xD5, 0xF0, 0x86,
0x0B, 0x00, 0xF2, 0x12, 0x11, 0x85, 0xF0, 0xCA, 0x0B, 0xE8, 0x09,
0x3C, 0x56, 0x00, 0xFC, 0x20, 0x01, 0x98, 0x57, 0x02, 0x13, 0xBB,
0x45, 0x4B, 0xE4, 0x00, 0x00, 0x08, 0x12, 0x03, 0xE6, 0x01, 0x00,
0x04, 0xF6, 0x00, 0x80, 0xA8, 0x14, 0xD2, 0x14, 0x30, 0x1C, 0x02,
0x80, 0x48, 0xE4, 0x03, 0x00, 0x10, 0x13, 0x00, 0xFC, 0xB6, 0x00,
0x98, 0x57, 0x02, 0x13, 0x4C, 0x1C, 0x3E, 0x1C, 0x00, 0xF0, 0x8E,
0x0B, 0x00, 0xFC, 0x24, 0x01, 0xB0, 0x57, 0x00, 0xFA, 0x24, 0x01,
0x4C, 0x1C, 0x3E, 0x1C, 0x00, 0xF2, 0x12, 0x11, 0x86, 0xF0, 0x8E,
0x0B, 0x00, 0xF2, 0x8C, 0x0E, 0x00, 0xF0, 0x8E, 0x0B, 0xB1, 0xF0,
0xF8, 0x0C, 0x85, 0xF0, 0x86, 0x0B, 0x69, 0x08, 0x48, 0xE4, 0x01,
0x00, 0xD5, 0xF0, 0x86, 0x0B, 0xFC, 0x14, 0x42, 0x58, 0x6C, 0x14,
0x80, 0x14, 0x30, 0x1C, 0x4A, 0xF4, 0x02, 0x00, 0x55, 0xF0, 0x86,
0x0B, 0x4A, 0xF4, 0x01, 0x00, 0x0E, 0x12, 0x02, 0x80, 0x48, 0xE4,
0x03, 0x00, 0x06, 0x13, 0x3E, 0x1C, 0x00, 0xF0, 0x8E, 0x0B, 0x00,
0xFC, 0xB6, 0x00, 0xB0, 0x57, 0x00, 0xFA, 0xB6, 0x00, 0x4C, 0x1C,
0x3E, 0x1C, 0x00, 0xF2, 0x12, 0x11, 0x86, 0xF0, 0x8E, 0x0B, 0x00,
0xF2, 0xBA, 0x0E, 0x00, 0xF0, 0x8E, 0x0B, 0x4C, 0x1C, 0xB1, 0xF0,
0x50, 0x0D, 0x85, 0xF0, 0x5C, 0x0D, 0x69, 0x08, 0xF3, 0x10, 0x86,
0xF0, 0x64, 0x0D, 0x4E, 0x1C, 0x89, 0x48, 0x00, 0x16, 0x00, 0xF6,
0x00, 0x01, 0x00, 0x57, 0x00, 0x57, 0x03, 0x58, 0x00, 0xDC, 0x18,
0xF4, 0xFF, 0x7F, 0x30, 0x56, 0x00, 0x5C, 0x00, 0x16, 0x00, 0xF6,
0x00, 0x01, 0x00, 0x57, 0x00, 0x57, 0x03, 0x58, 0x00, 0xDC, 0x18,
0xF4, 0x00, 0x80, 0x30, 0x56, 0x00, 0x5C, 0x00, 0x16, 0x00, 0xF6,
0x00, 0x01, 0x00, 0x57, 0x00, 0x57, 0x03, 0x58, 0x00, 0xDC, 0x0B,
0x58, 0x00, 0x16, 0x03, 0xF6, 0x24, 0x01, 0x00, 0xF2, 0x58, 0x0A,
0x03, 0xF6, 0xB6, 0x00, 0x00, 0xF2, 0x58, 0x0A, 0x00, 0x16, 0x02,
0xEC, 0xB8, 0x00, 0x02, 0x49, 0x18, 0xF4, 0xFF, 0x00, 0x00, 0x54,
0x00, 0x54, 0x00, 0x54, 0x00, 0xF4, 0x08, 0x00, 0xE1, 0x18, 0x80,
0x54, 0x03, 0x58, 0x00, 0xDD, 0x01, 0xDD, 0x02, 0xDD, 0x03, 0xDC,
0x02, 0x4B, 0x30, 0x50, 0xB2, 0x50, 0x34, 0x51, 0xB6, 0x51, 0x00,
0x16, 0x45, 0x5A, 0x1D, 0xF4, 0xFF, 0x00, 0x85, 0x56, 0x85, 0x56,
0x85, 0x56, 0x05, 0xF4, 0x02, 0x12, 0x83, 0x5A, 0x00, 0x16, 0x1D,
0xF4, 0xFF, 0x00, 0x85, 0x56, 0x85, 0x56, 0x85, 0x56, 0x05, 0xF4,
0x00, 0x12, 0x83, 0x5A, 0x00, 0x16, 0x38, 0x54, 0xBB, 0x55, 0x3C,
0x56, 0xBD, 0x56, 0x00, 0xF2, 0x12, 0x11, 0x85, 0xF0, 0x82, 0x0E,
0xE9, 0x09, 0xC1, 0x59, 0x00, 0xF2, 0x12, 0x11, 0x85, 0xF0, 0x82,
0x0E, 0xE8, 0x0A, 0x83, 0x55, 0x83, 0x55, 0x4B, 0xF4, 0x90, 0x01,
0x5C, 0xF0, 0x36, 0x0E, 0xBD, 0x56, 0x40, 0x10, 0x4B, 0xF4, 0x30,
0x00, 0x59, 0xF0, 0x48, 0x0E, 0x01, 0xF6, 0x0C, 0x00, 0x00, 0xF6,
0x01, 0x00, 0x2E, 0x10, 0x02, 0xFC, 0x9C, 0x00, 0x9A, 0x57, 0x14,
0x13, 0x4B, 0xF4, 0x64, 0x00, 0x59, 0xF0, 0x64, 0x0E, 0x03, 0xF6,
0x64, 0x00, 0x01, 0xF6, 0x19, 0x00, 0x00, 0xF6, 0x01, 0x00, 0x43,
0xF4, 0x33, 0x00, 0x56, 0xF0, 0x76, 0x0E, 0x04, 0xF4, 0x00, 0x01,
0x43, 0xF4, 0x19, 0x00, 0xF3, 0x10, 0xB4, 0x56, 0xC3, 0x58, 0x02,
0xFC, 0x9E, 0x00, 0x9A, 0x57, 0x08, 0x13, 0x3C, 0x56, 0x00, 0xF6,
0x02, 0x00, 0x00, 0x16, 0x00, 0x16, 0x09, 0xE7, 0x01, 0x00, 0x00,
0xF2, 0x12, 0x11, 0x86, 0xF0, 0xB8, 0x0E, 0x09, 0xE7, 0x02, 0x00,
0x00, 0xF2, 0x12, 0x11, 0x86, 0xF0, 0xB8, 0x0E, 0x09, 0xE7, 0x03,
0x00, 0x00, 0xF2, 0x12, 0x11, 0x86, 0xF0, 0xB8, 0x0E, 0x4E, 0x1C,
0x89, 0x49, 0x00, 0xF2, 0x12, 0x11, 0x00, 0x16, 0x09, 0xE7, 0x01,
0x00, 0x00, 0xF2, 0x12, 0x11, 0x86, 0xF0, 0xF2, 0x0E, 0x09, 0xE7,
0x03, 0x00, 0x00, 0xF2, 0x12, 0x11, 0x86, 0xF0, 0xF2, 0x0E, 0x09,
0xE7, 0x01, 0x00, 0x00, 0xF2, 0x12, 0x11, 0x86, 0xF0, 0xF2, 0x0E,
0x89, 0x49, 0x00, 0xF2, 0x12, 0x11, 0x86, 0xF0, 0xF2, 0x0E, 0x4E,
0x1C, 0x89, 0x4A, 0x00, 0xF2, 0x12, 0x11, 0x00, 0x16, 0x3C, 0x56,
0x00, 0x16, 0x00, 0xEC, 0x26, 0x01, 0x48, 0xE4, 0x01, 0x00, 0x1E,
0x13, 0x38, 0x44, 0x00, 0xEA, 0x26, 0x01, 0x49, 0xF4, 0x00, 0x00,
0x04, 0x12, 0x4E, 0x1C, 0x02, 0x10, 0x4C, 0x1C, 0x01, 0xEC, 0x27,
0x01, 0x89, 0x48, 0x00, 0xF2, 0x12, 0x11, 0x02, 0x14, 0x00, 0x16,
0x85, 0xF0, 0x52, 0x0F, 0x38, 0x54, 0x00, 0xEA, 0x99, 0x00, 0x00,
0xF2, 0x60, 0x0B, 0x02, 0x80, 0x48, 0xE4, 0x06, 0x00, 0x1C, 0x13,
0x00, 0xEC, 0x99, 0x00, 0x48, 0xE4, 0x01, 0x00, 0x0A, 0x12, 0x04,
0x80, 0x30, 0xE4, 0x01, 0x00, 0x04, 0x40, 0x08, 0x10, 0x04, 0x80,
0x18, 0xE4, 0xFE, 0x00, 0x04, 0x40, 0x00, 0x16, 0x02, 0xF6, 0xE0,
0x00, 0x02, 0x57, 0x03, 0x59, 0x01, 0xCC, 0x81, 0x48, 0x22, 0x12,
0x00, 0x4E, 0x83, 0x5A, 0x90, 0x4C, 0x20, 0xE7, 0x00, 0x00, 0xC3,
0x58, 0x1B, 0xF4, 0xFF, 0x00, 0x83, 0x55, 0x83, 0x55, 0x83, 0x55,
0x03, 0xF4, 0x00, 0x12, 0x8B, 0x55, 0x83, 0x59, 0x00, 0x4E, 0x00,
0x16, 0x00, 0x4E, 0x02, 0xF6, 0xF0, 0x00, 0x02, 0x57, 0x03, 0x59,
0x00, 0x4E, 0x83, 0x5A, 0x30, 0xE7, 0x00, 0x00, 0x20, 0xE7, 0x00,
0x00, 0x00, 0x16, 0x02, 0xF6, 0xF0, 0x00, 0x02, 0x57, 0x03, 0x59,
0x01, 0xCC, 0x00, 0x4E, 0x83, 0x5A, 0x30, 0xE7, 0x00, 0x00, 0x80,
0x4C, 0xC3, 0x58, 0x1B, 0xF4, 0xFF, 0x00, 0x83, 0x55, 0x83, 0x55,
0x83, 0x55, 0x03, 0xF4, 0x00, 0x12, 0x83, 0x59, 0x00, 0x4E, 0x00,
0x16, 0x03, 0xF6, 0xE0, 0x00, 0x03, 0x57, 0x83, 0x59, 0x3A, 0x55,
0x02, 0xCC, 0x45, 0x5A, 0x00, 0xF2, 0xF6, 0x0D, 0xC0, 0x5A, 0x40,
0x5C, 0x38, 0x54, 0x00, 0xCD, 0x01, 0xCC, 0x4A, 0x46, 0x0A, 0x13,
0x83, 0x59, 0x00, 0x4C, 0x01, 0x48, 0x16, 0x13, 0x0C, 0x10, 0xC5,
0x58, 0x00, 0xF2, 0xF6, 0x0D, 0x00, 0x4C, 0x01, 0x48, 0x08, 0x13,
0x05, 0xF6, 0xF0, 0x00, 0x05, 0x57, 0x08, 0x10, 0x45, 0x58, 0x00,
0xF2, 0xF6, 0x0D, 0x8D, 0x56, 0x83, 0x5A, 0x80, 0x4C, 0x05, 0x17,
0x00, 0x16, 0x02, 0x4B, 0x06, 0xF7, 0x04, 0x00, 0x62, 0x0B, 0x03,
0x82, 0x00, 0xF2, 0xE2, 0x0D, 0x02, 0x80, 0x00, 0x4C, 0x45, 0xF4,
0x02, 0x00, 0x52, 0x14, 0x06, 0xF7, 0x02, 0x00, 0x06, 0x14, 0x00,
0xF2, 0x54, 0x0F, 0x00, 0x16, 0x02, 0x4B, 0x01, 0xF6, 0xFF, 0x00,
0x38, 0x1C, 0x05, 0xF4, 0x04, 0x00, 0x83, 0x5A, 0x18, 0xDF, 0x19,
0xDF, 0x1D, 0xF7, 0x3C, 0x00, 0xB8, 0xF0, 0x4E, 0x10, 0x9C, 0x14,
0x01, 0x48, 0x1C, 0x13, 0x0E, 0xF7, 0x3C, 0x00, 0x03, 0xF7, 0x04,
0x00, 0xAF, 0x19, 0x03, 0x42, 0x45, 0xF4, 0x02, 0x00, 0x83, 0x5A,
0x02, 0xCC, 0x02, 0x41, 0x45, 0xF4, 0x02, 0x00, 0x00, 0x16, 0x91,
0x44, 0xD5, 0xF0, 0x3E, 0x10, 0x00, 0xF0, 0x9E, 0x02, 0x01, 0xF6,
0xFF, 0x00, 0x38, 0x1C, 0x05, 0xF4, 0x04, 0x00, 0x83, 0x5A, 0x18,
0xDF, 0x19, 0xDF, 0x0E, 0xF7, 0x3C, 0x00, 0x03, 0xF7, 0x04, 0x00,
0x0F, 0x79, 0x1C, 0xF7, 0x3C, 0x00, 0xB8, 0xF0, 0x9C, 0x10, 0x4E,
0x14, 0x01, 0x48, 0x06, 0x13, 0x45, 0xF4, 0x04, 0x00, 0x00, 0x16,
0x91, 0x44, 0xD5, 0xF0, 0x82, 0x10, 0x00, 0xF0, 0x9E, 0x02, 0x02,
0xF6, 0xFF, 0x00, 0x38, 0x1C, 0x2C, 0xBC, 0xAE, 0xBC, 0xE2, 0x08,
0x00, 0xEC, 0xB8, 0x00, 0x02, 0x48, 0x1D, 0xF7, 0x80, 0x00, 0xB8,
0xF0, 0xCC, 0x10, 0x1E, 0x14, 0x01, 0x48, 0x0E, 0x13, 0x0E, 0xF7,
0x80, 0x00, 0x38, 0x54, 0x03, 0x58, 0xAF, 0x19, 0x82, 0x48, 0x00,
0x16, 0x82, 0x48, 0x12, 0x45, 0xD5, 0xF0, 0xBA, 0x10, 0x00, 0xF0,
0x9E, 0x02, 0x39, 0xF0, 0xF8, 0x10, 0x38, 0x44, 0x00, 0x16, 0x7E,
0x18, 0x18, 0xF4, 0x03, 0x00, 0x04, 0x13, 0x61, 0x18, 0x00, 0x16,
0x38, 0x1C, 0x00, 0xFC, 0x22, 0x01, 0x18, 0xF4, 0x01, 0x00, 0xF1,
0x12, 0xE3, 0x10, 0x30, 0x44, 0x30, 0x44, 0x30, 0x44, 0xB1, 0xF0,
0x18, 0x11, 0x00, 0x16, 0x3E, 0x57, 0x03, 0xF6, 0xE0, 0x00, 0x03,
0x57, 0x83, 0x59, 0x04, 0xCC, 0x01, 0x4A, 0x6A, 0x12, 0x45, 0x5A,
0x00, 0xF2, 0xF6, 0x0D, 0x02, 0x4B, 0x70, 0x14, 0x34, 0x13, 0x02,
0x80, 0x48, 0xE4, 0x08, 0x00, 0x18, 0x12, 0x9C, 0xE7, 0x02, 0x00,
0x9E, 0xE7, 0x15, 0x00, 0x00, 0xF2, 0xC6, 0x0F, 0x00, 0xF2, 0x7A,
0x0A, 0x1E, 0x1C, 0x01, 0xF6, 0x01, 0x00, 0x00, 0x16, 0x30, 0xE4,
0x10, 0x00, 0x04, 0x40, 0x00, 0xF2, 0xE2, 0x0D, 0x20, 0xE7, 0x01,
0x00, 0x01, 0xF6, 0x01, 0x00, 0x00, 0x16, 0x04, 0xDC, 0x01, 0x4A,
0x24, 0x12, 0x45, 0x5A, 0x00, 0xF2, 0xF6, 0x0D, 0x43, 0x5B, 0x06,
0xEC, 0x98, 0x00, 0x00, 0xF2, 0x38, 0x10, 0xC6, 0x59, 0x20, 0x14,
0x0A, 0x13, 0x00, 0xF2, 0xC6, 0x0F, 0x00, 0xF2, 0x14, 0x10, 0xA7,
0x10, 0x83, 0x5A, 0xD7, 0x10, 0x0E, 0x47, 0x07, 0xE6, 0x10, 0x00,
0xCE, 0x47, 0x5A, 0xF0, 0x20, 0x11, 0xB9, 0x54, 0x00, 0x16, 0x14,
0x90, 0x96, 0x90, 0x02, 0xFC, 0xA8, 0x00, 0x03, 0xFC, 0xAA, 0x00,
0x48, 0x55, 0x02, 0x13, 0xC9, 0x55, 0x00, 0x16, 0x00, 0xEC, 0xBA,
0x00, 0x10, 0x44, 0x00, 0xEA, 0xBA, 0x00, 0x00, 0x16, 0x03, 0xF6,
0xC0, 0x00, 0x00, 0xF2, 0x68, 0x0A, 0x10, 0x44, 0x00, 0x4C, 0x00,
0x16
};
u_int16_t adw_mcode_size = sizeof(adw_mcode);
u_int32_t adw_mcode_chksum = 0x03494981;

126
sys/dev/advansys/adwmcode.h Normal file
View File

@ -0,0 +1,126 @@
/*
* Exported interface to downloadable microcode for AdvanSys SCSI Adapters
*
* $Id: advmcode.h,v 1.4 1998/09/15 07:03:34 gibbs Exp $
*
* Obtained from:
*
* Copyright (c) 1995-1998 Advanced System Products, Inc.
* All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that redistributions of source
* code retain the above copyright notice and this comment without
* modification.
*/
#ifndef _ADMCODE_H_
#define _ADMCODE_H_
extern u_int16_t adw_mcode[];
extern u_int16_t adw_mcode_size;
extern u_int32_t adw_mcode_chksum;
/*
* Fixed LRAM locations of microcode operating variables.
*/
#define ADW_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
#define ADW_MC_CODE_END_ADDR 0x002A /* microcode end address */
#define ADW_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
#define ADW_MC_STACK_BEGIN 0x002E /* microcode stack begin */
#define ADW_MC_STACK_END 0x0030 /* microcode stack end */
#define ADW_MC_VERSION_DATE 0x0038 /* microcode version */
#define ADW_MC_VERSION_NUM 0x003A /* microcode number */
#define ADW_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
#define ADW_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
#define ADW_MC_HALTCODE 0x0094 /* microcode halt code */
#define ADW_MC_CALLERPC 0x0096 /* microcode halt caller PC */
#define ADW_MC_ADAPTER_SCSI_ID 0x0098 /* one ID byte + reserved */
#define ADW_MC_ULTRA_ABLE 0x009C
#define ADW_MC_SDTR_ABLE 0x009E
#define ADW_MC_TAGQNG_ABLE 0x00A0
#define ADW_MC_DISC_ENABLE 0x00A2
#define ADW_MC_IDLE_CMD 0x00A6
#define ADW_MC_IDLE_PARA_STAT 0x00A8
#define ADW_MC_DEFAULT_SCSI_CFG0 0x00AC
#define ADW_MC_DEFAULT_SCSI_CFG1 0x00AE
#define ADW_MC_DEFAULT_MEM_CFG 0x00B0
#define ADW_MC_DEFAULT_SEL_MASK 0x00B2
#define ADW_MC_RISC_NEXT_READY 0x00B4
#define ADW_MC_RISC_NEXT_DONE 0x00B5
#define ADW_MC_SDTR_DONE 0x00B6
#define ADW_MC_NUMBER_OF_QUEUED_CMD 0x00C0
#define ADW_MC_NUMBER_OF_MAX_CMD 0x00D0
#define ADW_MC_DEVICE_HSHK_CFG_TABLE 0x0100
#define ADW_HSHK_CFG_WIDE_XFR 0x8000
#define ADW_HSHK_CFG_RATE_MASK 0x0F00
#define ADW_HSHK_CFG_RATE_SHIFT 8
#define ADW_HSHK_CFG_PERIOD_FACTOR(cfg_val) \
((((((cfg_val) & ADW_HSHK_CFG_RATE_MASK) >> ADW_HSHK_CFG_RATE_SHIFT) \
* 25) + 50)/4)
#define ADW_HSHK_CFG_OFFSET 0x001F
#define ADW_MC_WDTR_ABLE 0x0120 /* Wide Transfer TID bitmask. */
#define ADW_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
#define ADW_MC_CONTROL_IGN_PERR 0x0001 /* Ignore DMA Parity Errors */
#define ADW_MC_WDTR_DONE 0x0124
#define ADW_MC_HOST_NEXT_READY 0x0128 /* Host Next Ready RQL Entry. */
#define ADW_MC_HOST_NEXT_DONE 0x0129 /* Host Next Done RQL Entry. */
/*
* LRAM RISC Queue Lists (LRAM addresses 0x1200 - 0x19FF)
*
* Each of the 255 Adv Library/Microcode RISC queue lists or mailboxes
* starting at LRAM address 0x1200 is 8 bytes and has the following
* structure. Only 253 of these are actually used for command queues.
*/
#define ADW_MC_RISC_Q_LIST_BASE 0x1200
#define ADW_MC_RISC_Q_LIST_SIZE 0x0008
#define ADW_MC_RISC_Q_TOTAL_CNT 0x00FF /* Num. queue slots in LRAM. */
#define ADW_MC_RISC_Q_FIRST 0x0001
#define ADW_MC_RISC_Q_LAST 0x00FF
/* RISC Queue List structure - 8 bytes */
#define RQL_FWD 0 /* forward pointer (1 byte) */
#define RQL_BWD 1 /* backward pointer (1 byte) */
#define RQL_STATE 2 /* state byte - free, ready, done, aborted (1 byte) */
#define RQL_TID 3 /* request target id (1 byte) */
#define RQL_PHYADDR 4 /* request physical pointer (4 bytes) */
/* RISC Queue List state values */
#define ADW_MC_QS_FREE 0x00
#define ADW_MC_QS_READY 0x01
#define ADW_MC_QS_DONE 0x40
#define ADW_MC_QS_ABORTED 0x80
/* RISC Queue List pointer values */
#define ADW_MC_NULL_Q 0x00
#define ADW_MC_BIOS_Q 0xFF
/* ADW_SCSI_REQ_Q 'cntl' field values */
#define ADW_MC_QC_START_MOTOR 0x02 /* Issue start motor. */
#define ADW_MC_QC_NO_OVERRUN 0x04 /* Don't report overrun. */
#define ADW_MC_QC_FIRST_DMA 0x08 /* Internal microcode flag. */
#define ADW_MC_QC_ABORTED 0x10 /* Request aborted by host. */
#define ADW_MC_QC_REQ_SENSE 0x20 /* Auto-Request Sense. */
#define ADW_MC_QC_DOS_REQ 0x80 /* Request issued by DOS. */
/*
* Microcode idle loop commands
*/
typedef enum {
ADW_IDLE_CMD_COMPLETED = 0x0000,
ADW_IDLE_CMD_STOP_CHIP = 0x0001,
ADW_IDLE_CMD_STOP_CHIP_SEND_INT = 0x0002,
ADW_IDLE_CMD_SEND_INT = 0x0004,
ADW_IDLE_CMD_ABORT = 0x0008,
ADW_IDLE_CMD_DEVICE_RESET = 0x0010,
ADW_IDLE_CMD_SCSI_RESET = 0x0020
} adw_idle_cmd_t;
typedef enum {
ADW_IDLE_CMD_FAILURE = 0x0000,
ADW_IDLE_CMD_SUCCESS = 0x0001
} adw_idle_cmd_status_t;
#endif /* _ADMCODE_H_ */

56
sys/dev/advansys/adwvar.h Normal file
View File

@ -0,0 +1,56 @@
/*
* Generic driver definitions and exported functions for the Advanced
* Systems Inc. Second Generation SCSI controllers
*
* Copyright (c) 1998 Justin Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
* All rights reserved.
*
* $Id$
*/
#ifndef _ADWVAR_H_
#define _ADWVAR_H_
#include "adw.h"
#include <dev/advansys/adwlib.h>
struct adw_softc * adw_alloc(int unit, bus_space_tag_t tag,
bus_space_handle_t bsh);
void adw_map(void *arg, bus_dma_segment_t *segs,
int nseg, int error);
void adw_free(struct adw_softc *adw);
int adw_init(struct adw_softc *adw);
void adw_intr(void *arg);
int adw_attach(struct adw_softc *adw);
void adw_done(struct adw_softc *adw, union ccb* ccb,
u_int done_stat, u_int host_stat,
u_int scsi_stat, u_int q_no);
timeout_t adw_timeout;
extern u_long adw_unit;
#endif /* _ADWVAR_H_ */

185
sys/pci/adw_pci.c Normal file
View File

@ -0,0 +1,185 @@
/*
* Device probe and attach routines for the following
* Advanced Systems Inc. SCSI controllers:
*
* ABP940UW - Bus-Master PCI Ultra-Wide (240 CDB)
*
* Copyright (c) 1998 Justin Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id$
*/
#include <pci.h>
#if NPCI > 0
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <machine/bus_pio.h>
#include <machine/bus.h>
#include <pci/pcireg.h>
#include <pci/pcivar.h>
#include <cam/cam.h>
#include <cam/scsi/scsi_all.h>
#include <dev/advansys/adwvar.h>
#include <dev/advansys/adwlib.h>
#include <dev/advansys/adwmcode.h>
#define PCI_BASEADR0 PCI_MAP_REG_START /* I/O Address */
#define PCI_BASEADR1 PCI_MAP_REG_START + 4 /* Mem I/O Address */
#define PCI_DEVICE_ID_ADVANSYS_3550 0x230010CD
#define ADW_PCI_MAX_DMA_ADDR (0xFFFFFFFFUL)
#define ADW_PCI_MAX_DMA_COUNT (0xFFFFFFFFUL)
static char* adwpciprobe(pcici_t tag, pcidi_t type);
static void adwpciattach(pcici_t config_id, int unit);
static struct pci_device adw_pci_driver = {
"adw",
adwpciprobe,
adwpciattach,
&adw_unit,
NULL
};
DATA_SET (pcidevice_set, adw_pci_driver);
static char*
adwpciprobe(pcici_t tag, pcidi_t type)
{
switch (type) {
case PCI_DEVICE_ID_ADVANSYS_3550:
return ("AdvanSys ASC3550 SCSI controller");
default:
break;
}
return (NULL);
}
static void
adwpciattach(pcici_t config_id, int unit)
{
u_int32_t id;
u_int32_t command;
vm_offset_t vaddr;
vm_offset_t paddr;
u_int16_t io_port;
bus_space_tag_t tag;
bus_space_handle_t bsh;
struct adw_softc *adw;
int error;
/*
* Determine the chip version.
*/
id = pci_cfgread(config_id, PCI_ID_REG, /*bytes*/4);
command = pci_cfgread(config_id, PCIR_COMMAND, /*bytes*/1);
/*
* These cards do not allow memory mapped accesses, so we must
* ensure that I/O accesses are available or we won't be able
* to talk to them.
*/
vaddr = 0;
#ifdef ADW_ALLOW_MEMIO
if ((command & PCI_COMMAND_MEM_ENABLE) == 0
|| (pci_map_mem(config_id, PCI_BASEADR1, &vaddr, &paddr)) == 0)
#endif
if ((command & PCI_COMMAND_IO_ENABLE) == 0
|| (pci_map_port(config_id, PCI_BASEADR0, &io_port)) == 0)
return;
/* XXX Should be passed in by parent bus */
/* XXX Why isn't the 0x10 offset incorporated into the reg defs? */
if (vaddr != 0) {
tag = I386_BUS_SPACE_MEM;
bsh = vaddr;
} else {
tag = I386_BUS_SPACE_IO;
bsh = io_port;
}
if (adw_find_signature(tag, bsh) == 0)
return;
adw = adw_alloc(unit, tag, bsh);
if (adw == NULL)
return;
/* Allocate a dmatag for our transfer DMA maps */
/* XXX Should be a child of the PCI bus dma tag */
error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/0,
/*boundary*/0,
/*lowaddr*/ADW_PCI_MAX_DMA_ADDR,
/*highaddr*/BUS_SPACE_MAXADDR,
/*filter*/NULL, /*filterarg*/NULL,
/*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
/*nsegments*/BUS_SPACE_UNRESTRICTED,
/*maxsegsz*/ADW_PCI_MAX_DMA_COUNT,
/*flags*/0,
&adw->parent_dmat);
adw->init_level++;
if (error != 0) {
printf("%s: Could not allocate DMA tag - error %d\n",
adw_name(adw), error);
adw_free(adw);
return;
}
adw->init_level++;
if (adw_init(adw) != 0) {
adw_free(adw);
return;
}
/*
* If the PCI Configuration Command Register "Parity Error Response
* Control" Bit was clear (0), then set the microcode variable
* 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
* to ignore DMA parity errors.
*/
if ((command & PCIM_CMD_PERRESPEN) == 0)
adw_lram_write_16(adw, ADW_MC_CONTROL_FLAG,
adw_lram_read_16(adw, ADW_MC_CONTROL_FLAG)
| ADW_MC_CONTROL_IGN_PERR);
if ((pci_map_int(config_id, adw_intr, (void *)adw, &cam_imask)) == 0) {
adw_free(adw);
return;
}
adw_attach(adw);
}
#endif /* NPCI > 0 */