This is an update to the new Intel 10G 82598 driver.
The first drop was Beta, this code is expected to be the release version. Note that this driver code will build in either 6.2 or 7. If you use the code in 6.2 you will not get TSO or MSI/X support but it will function in a legacy mode. Approved by: re
This commit is contained in:
Jack F Vogel
parent
5060bcfacd
commit
3ec35e52b8
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=172043
File diff suppressed because it is too large
Load Diff
@ -86,39 +86,35 @@ POSSIBILITY OF SUCH DAMAGE.
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/* Tunables */
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/*
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** The number of queues: right now significant performance
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** seems to be gained by using muliple RX queues. The
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** infrastructure for multiple TX is there but its not
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** completely working, dont set greater than 1 for now.
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** OTHER is the vector used for link changes, it also
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** should only be set to 1.
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*/
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#define IXGBE_TX_QUEUES 1
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#define IXGBE_RX_QUEUES 8
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#define IXGBE_OTHER 1
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/*
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* TxDescriptors Valid Range: 64-4096 Default Value: 2048 This value is the
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* TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
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* number of transmit descriptors allocated by the driver. Increasing this
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* value allows the driver to queue more transmits. Each descriptor is 16
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* bytes.
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* bytes. Performance tests have show the 2K value to be optimal for top
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* performance.
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*/
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#define DEFAULT_TXD 2048
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#define DEFAULT_TXD 256
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#define PERFORM_TXD 2048
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#define MAX_TXD 4096
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#define MIN_TXD 64
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/*
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* RxDescriptors Valid Range: 64-4096 Default Value: 2048 This value is the
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* number of receive descriptors allocated by the driver. Increasing this
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* RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
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* number of receive descriptors allocated for each RX queue. Increasing this
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* value allows the driver to buffer more incoming packets. Each descriptor
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* is 16 bytes. A receive buffer is also allocated for each descriptor. The
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* maximum MTU size is 16110.
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* is 16 bytes. A receive buffer is also allocated for each descriptor.
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*
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* Note: with 8 rings and a dual port card, it is possible to bump up
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* against the system mbuf pool limit, you can tune nmbclusters
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* to adjust for this.
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*/
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#define DEFAULT_RXD 2048
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#define DEFAULT_RXD 256
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#define PERFORM_RXD 2048
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#define MAX_RXD 4096
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#define MIN_RXD 64
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/* Alignment for rings */
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#define DBA_ALIGN 128
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/*
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* This parameter controls the maximum no of times the driver will loop in
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* the isr. Minimum Value = 1
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@ -138,15 +134,11 @@ POSSIBILITY OF SUCH DAMAGE.
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#define IXGBE_TX_OP_THRESHOLD (adapter->num_tx_desc / 32)
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#define IXGBE_MAX_FRAME_SIZE 0x3F00
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#define PERFORMANCE_MTU 9000 /* Best thruput results */
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/*
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** This controls the size mbuf pool used, it
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** may ultimately be automatic, but for now its
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** a compile time option.
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** - use MCLBYTES for legacy size
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*/
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#define IXGBE_RXBUF MJUMPAGESIZE
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/* Flow control constants */
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#define IXGBE_FC_PAUSE 0x680
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#define IXGBE_FC_HI 0x20000
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#define IXGBE_FC_LO 0x10000
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/* Defines for printing debug information */
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#define DEBUG_INIT 0
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@ -174,13 +166,23 @@ POSSIBILITY OF SUCH DAMAGE.
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/* The number of MSIX messages the 82598 supports */
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#define IXGBE_MSGS 18
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/* For 6.X code compatibility */
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#if __FreeBSD_version < 700000
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#define ETHER_BPF_MTAP BPF_MTAP
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#define CSUM_TSO 0
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#define IFCAP_TSO4 0
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#define FILTER_STRAY
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#define FILTER_HANDLED
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#endif
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/*
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* Interrupt Moderation parameters
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* for now we hardcode, later
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* it would be nice to do dynamic
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*/
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#define DEFAULT_ITR 8000
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#define LINK_ITR 1950
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#define MAX_IRQ_SEC 8000
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#define DEFAULT_ITR 1000000000/(MAX_IRQ_SEC * 256)
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#define LINK_ITR 1000000000/(1950 * 256)
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/*
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* ******************************************************************************
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@ -232,7 +234,6 @@ struct ixgbe_dma_alloc {
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struct tx_ring {
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struct adapter *adapter;
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u32 me;
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struct mtx mtx;
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union ixgbe_adv_tx_desc *tx_base;
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struct ixgbe_dma_alloc txdma;
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uint32_t next_avail_tx_desc;
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@ -250,7 +251,6 @@ struct tx_ring {
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struct rx_ring {
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struct adapter *adapter;
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u32 me;
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struct mtx mtx;
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u32 payload;
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union ixgbe_adv_rx_desc *rx_base;
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struct ixgbe_dma_alloc rxdma;
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@ -292,7 +292,12 @@ struct adapter {
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int watchdog_timer;
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int msix;
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int if_flags;
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struct mtx mtx;
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struct mtx core_mtx;
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struct mtx tx_mtx;
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/* Legacy Fast Intr handling */
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struct task link_task;
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struct task rxtx_task;
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struct taskqueue *tq;
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/* Info about the board itself */
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uint32_t part_num;
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@ -338,11 +343,4 @@ struct adapter {
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struct ixgbe_hw_stats stats;
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};
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#define IXGBE_LOCK_INIT(_sc, _name) \
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mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
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#define IXGBE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
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#define IXGBE_LOCK(_sc) mtx_lock(&(_sc)->mtx)
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#define IXGBE_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
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#define IXGBE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
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#endif /* _IXGBE_H_ */
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@ -32,6 +32,7 @@
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*******************************************************************************/
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/* $FreeBSD$ */
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#include "ixgbe_type.h"
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#include "ixgbe_api.h"
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#include "ixgbe_common.h"
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@ -73,6 +74,10 @@ s32 ixgbe_reset_hw_rev_0_82598(struct ixgbe_hw *hw);
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#endif
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s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
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u32 ixgbe_get_num_rx_addrs_82598(struct ixgbe_hw *hw);
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s32 ixgbe_configure_fiber_serdes_fc_82598(struct ixgbe_hw *hw);
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s32 ixgbe_setup_fiber_serdes_link_82598(struct ixgbe_hw *hw);
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s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);
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s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);
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/**
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@ -84,9 +89,6 @@ u32 ixgbe_get_num_rx_addrs_82598(struct ixgbe_hw *hw);
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**/
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s32 ixgbe_init_shared_code_82598(struct ixgbe_hw *hw)
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{
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/* Set MAC type */
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hw->mac.type = ixgbe_mac_82598EB;
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/* Assign function pointers */
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ixgbe_assign_func_pointers_82598(hw);
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@ -109,6 +111,10 @@ s32 ixgbe_assign_func_pointers_82598(struct ixgbe_hw *hw)
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&ixgbe_get_num_of_tx_queues_82598;
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hw->func.ixgbe_func_get_num_of_rx_queues =
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&ixgbe_get_num_of_rx_queues_82598;
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hw->func.ixgbe_func_read_analog_reg8 =
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&ixgbe_read_analog_reg8_82598;
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hw->func.ixgbe_func_write_analog_reg8 =
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&ixgbe_write_analog_reg8_82598;
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#ifndef NO_82598_A0_SUPPORT
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if (hw->revision_id == 0) {
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hw->func.ixgbe_func_reset_hw =
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@ -250,18 +256,11 @@ enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
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/* Media type for I82598 is based on device ID */
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switch (hw->device_id) {
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case IXGBE_DEV_ID_82598:
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/* Default device ID is mezzanine card KX/KX4 */
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media_type = ixgbe_media_type_backplane;
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break;
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case IXGBE_DEV_ID_82598_FPGA:
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case IXGBE_DEV_ID_82598AF_DUAL_PORT:
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case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
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case IXGBE_DEV_ID_82598EB_CX4:
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media_type = ixgbe_media_type_fiber;
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break;
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case IXGBE_DEV_ID_82598AT_DUAL_PORT:
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media_type = ixgbe_media_type_copper;
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break;
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default:
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media_type = ixgbe_media_type_unknown;
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break;
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@ -278,9 +277,6 @@ enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
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**/
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u32 ixgbe_get_num_of_tx_queues_82598(struct ixgbe_hw *hw)
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{
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if (hw->device_id == IXGBE_DEV_ID_82598_FPGA)
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return 8;
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return IXGBE_82598_MAX_TX_QUEUES;
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}
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@ -292,9 +288,6 @@ u32 ixgbe_get_num_of_tx_queues_82598(struct ixgbe_hw *hw)
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**/
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u32 ixgbe_get_num_of_rx_queues_82598(struct ixgbe_hw *hw)
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{
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if (hw->device_id == IXGBE_DEV_ID_82598_FPGA)
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return 8;
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return IXGBE_82598_MAX_RX_QUEUES;
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}
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@ -307,6 +300,8 @@ u32 ixgbe_get_num_of_rx_queues_82598(struct ixgbe_hw *hw)
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**/
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s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
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{
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ixgbe_link_speed speed;
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bool link_up;
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u32 autoc_reg;
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u32 links_reg;
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u32 i;
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@ -346,6 +341,22 @@ s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
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}
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}
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/*
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* We want to save off the original Flow Control configuration just in
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* case we get disconnected and then reconnected into a different hub
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* or switch with different Flow Control capabilities.
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*/
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hw->fc.type = hw->fc.original_type;
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/*
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* Set up the SerDes link if in 1Gb mode, otherwise just set up
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* 10Gb flow control.
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*/
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ixgbe_check_link(hw, &speed, &link_up);
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if (speed == IXGBE_LINK_SPEED_1GB_FULL)
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status = ixgbe_setup_fiber_serdes_link_82598(hw);
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else
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ixgbe_setup_fc_generic(hw, 0);
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/* Add delay to filter out noises during initial link setup */
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msec_delay(50);
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@ -380,6 +391,236 @@ s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
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return IXGBE_SUCCESS;
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}
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/**
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* ixgbe_configure_fiber_serdes_fc_82598 - Configure fiber flow control
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* @hw: pointer to hardware structure
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*
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* Reads PCS registers and sets flow control settings, based on
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* link-partner's abilities.
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**/
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s32 ixgbe_configure_fiber_serdes_fc_82598(struct ixgbe_hw *hw)
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{
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s32 ret_val = IXGBE_SUCCESS;
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u32 delay = 300, pcs_anadv_reg, pcs_lpab_reg, pcs_lstat_reg, i;
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DEBUGFUNC("ixgbe_configure_fiber_serdes_fc_82598");
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/* Check that autonegotiation has completed */
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for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
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/*
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* Delay 300msec before reading PCS1GLSTA. Reading PCS1GLSTA
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* before then will sometimes result in AN_COMPLETE not being
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* set.
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*/
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msec_delay(delay);
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pcs_lstat_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
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if (pcs_lstat_reg & IXGBE_PCS1GLSTA_AN_COMPLETE) {
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if (pcs_lstat_reg & (IXGBE_PCS1GLSTA_LINK_OK)) {
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if (!(pcs_lstat_reg &
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(IXGBE_PCS1GLSTA_AN_TIMED_OUT)))
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hw->mac.autoneg_failed = 0;
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else
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hw->mac.autoneg_failed = 1;
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break;
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} else {
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hw->mac.autoneg_failed = 1;
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break;
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}
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}
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/*
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* Increment the delay time by 50ms to wait before reading
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* PCS1GLSTA again.
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*/
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delay += 50;
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}
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if (i == FIBER_LINK_UP_LIMIT)
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hw->mac.autoneg_failed = 1;
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if (hw->mac.autoneg_failed) {
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/*
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* AutoNeg failed to achieve a link, so we will turn
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* flow control off.
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*/
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hw->fc.type = ixgbe_fc_none;
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DEBUGOUT("Flow Control = NONE.\n");
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ret_val = ixgbe_setup_fc_generic(hw, 0);
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goto out;
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}
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/*
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* Read the AN advertisement and LP ability registers and resolve
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* local flow control settings accordingly
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*/
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pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
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pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
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if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
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(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
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/*
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* Now we need to check if the user selected RX ONLY
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* of pause frames. In this case, we had to advertise
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* FULL flow control because we could not advertise RX
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* ONLY. Hence, we must now check to see if we need to
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* turn OFF the TRANSMISSION of PAUSE frames.
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*/
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if (hw->fc.original_type == ixgbe_fc_full) {
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hw->fc.type = ixgbe_fc_full;
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DEBUGOUT("Flow Control = FULL.\n");
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} else {
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hw->fc.type = ixgbe_fc_rx_pause;
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DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
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}
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} else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
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(pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
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(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
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(pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
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hw->fc.type = ixgbe_fc_tx_pause;
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DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
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} else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
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(pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
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!(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
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(pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
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hw->fc.type = ixgbe_fc_rx_pause;
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DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
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} else if ((hw->fc.original_type == ixgbe_fc_none ||
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hw->fc.original_type == ixgbe_fc_tx_pause) ||
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hw->fc.strict_ieee) {
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hw->fc.type = ixgbe_fc_none;
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DEBUGOUT("Flow Control = NONE.\n");
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} else {
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hw->fc.type = ixgbe_fc_rx_pause;
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DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
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}
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ret_val = ixgbe_setup_fc_generic(hw, 0);
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if (ret_val) {
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DEBUGOUT("Error forcing flow control settings\n");
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goto out;
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}
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out:
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return ret_val;
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}
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/**
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* ixgbe_setup_fiber_serdes_link_82598 - Configure fiber serdes link
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* @hw: pointer to hardware structure
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*
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* Sets up PCS registers and sets flow control settings, based on
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* link-partner's abilities.
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**/
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s32 ixgbe_setup_fiber_serdes_link_82598(struct ixgbe_hw *hw)
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{
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u32 reg;
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s32 ret_val;
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DEBUGFUNC("ixgbe_setup_fiber_serdes_link_82598");
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/*
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* 82598 fiber/serdes devices require that flow control be resolved in
|
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* software. Set up flow control advertisement if autoneg is enabled.
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*/
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if (hw->mac.autoneg) {
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reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
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/*
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* Check for a software override of the flow control settings,
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* and setup the device accordingly. If auto-negotiation is
|
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* enabled, then software will have to set the "PAUSE" bits to
|
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* the correct value and re-start auto- negotiation. However,
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* if auto-negotiation is disabled, then software will have to
|
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* manually configure flow control.
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*
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* The possible values of the "fc" parameter are:
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* 0: Flow control is completely disabled
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* 1: Rx flow control is enabled (we can receive pause frames,
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* but not send pause frames).
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* 2: Tx flow control is enabled (we can send pause frames but
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* we do not support receiving pause frames).
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* 3: Both Rx and TX flow control (symmetric) are enabled.
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*/
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switch (hw->fc.type) {
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case ixgbe_fc_none:
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/*
|
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* Flow control completely disabled by a software
|
||||
* over-ride.
|
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*/
|
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reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE |
|
||||
IXGBE_PCS1GANA_ASM_PAUSE);
|
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break;
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case ixgbe_fc_rx_pause:
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||||
/*
|
||||
* RX Flow control is enabled and TX Flow control is
|
||||
* disabled by a software over-ride. Since there really
|
||||
* isn't a way to advertise that we are capable of RX
|
||||
* Pause ONLY, we will advertise that we support both
|
||||
* symmetric and asymmetric RX PAUSE. Later, we will
|
||||
* disable the adapter's ability to send PAUSE frames.
|
||||
*/
|
||||
reg |= (IXGBE_PCS1GANA_SYM_PAUSE |
|
||||
IXGBE_PCS1GANA_ASM_PAUSE);
|
||||
break;
|
||||
case ixgbe_fc_tx_pause:
|
||||
/*
|
||||
* TX Flow control is enabled, and RX Flow control is
|
||||
* disabled, by a software over-ride.
|
||||
*/
|
||||
reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
|
||||
reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
|
||||
break;
|
||||
case ixgbe_fc_full:
|
||||
/*
|
||||
* Flow control (both RX and TX) is enabled by a
|
||||
* software over-ride.
|
||||
*/
|
||||
reg |= (IXGBE_PCS1GANA_SYM_PAUSE |
|
||||
IXGBE_PCS1GANA_ASM_PAUSE);
|
||||
break;
|
||||
default:
|
||||
DEBUGOUT("Flow control param set incorrectly\n");
|
||||
ret_val = -IXGBE_ERR_CONFIG;
|
||||
goto out;
|
||||
break;
|
||||
}
|
||||
|
||||
IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
|
||||
}
|
||||
|
||||
/*
|
||||
* New SerDes mode allows for forcing speed or autonegotiating speed
|
||||
* at 1gb. Autoneg should be default set by most drivers. This is the
|
||||
* mode that will be compatible with older link partners and switches.
|
||||
* However, both are supported by the hardware and some drivers/tools.
|
||||
*/
|
||||
reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
|
||||
reg &= ~(IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN);
|
||||
|
||||
if (hw->mac.autoneg) {
|
||||
/* Set PCS register for autoneg */
|
||||
reg |= IXGBE_PCS1GLCTL_AN_ENABLE | /* Enable Autoneg */
|
||||
IXGBE_PCS1GLCTL_AN_RESTART; /* Restart autoneg */
|
||||
DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
|
||||
} else {
|
||||
/* Set PCS register for forced speed */
|
||||
reg |= IXGBE_PCS1GLCTL_FLV_LINK_UP | /* Force link up */
|
||||
IXGBE_PCS1GLCTL_FORCE_LINK; /* Force Link */
|
||||
DEBUGOUT1("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
|
||||
}
|
||||
IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
|
||||
|
||||
/*
|
||||
* Configure flow control. If we aren't auto-negotiating,
|
||||
* just setup the flow control and do not worry about PCS autoneg.
|
||||
*/
|
||||
if (hw->mac.autoneg)
|
||||
ixgbe_configure_fiber_serdes_fc_82598(hw);
|
||||
|
||||
out:
|
||||
return IXGBE_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
|
||||
* @hw: pointer to hardware structure
|
||||
@ -644,10 +885,36 @@ s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
|
||||
u32 gheccr;
|
||||
u32 i;
|
||||
u32 autoc;
|
||||
u8 analog_val;
|
||||
|
||||
/* Call adapter stop to disable tx/rx and clear interrupts */
|
||||
ixgbe_stop_adapter(hw);
|
||||
|
||||
/*
|
||||
* Power up the Atlas TX lanes if they are currently powered down.
|
||||
* Atlas TX lanes are powered down for MAC loopback tests, but
|
||||
* they are not automatically restored on reset.
|
||||
*/
|
||||
ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
|
||||
if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
|
||||
/* Enable TX Atlas so packets can be transmitted again */
|
||||
ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
|
||||
analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
|
||||
ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, analog_val);
|
||||
|
||||
ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &analog_val);
|
||||
analog_val &= ~ IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
|
||||
ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, analog_val);
|
||||
|
||||
ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &analog_val);
|
||||
analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
|
||||
ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, analog_val);
|
||||
|
||||
ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &analog_val);
|
||||
analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
|
||||
ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, analog_val);
|
||||
}
|
||||
|
||||
/* Reset PHY */
|
||||
ixgbe_reset_phy(hw);
|
||||
|
||||
@ -713,6 +980,47 @@ s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_read_analog_reg8_82598 - Reads 8 bit 82598 Atlas analog register
|
||||
* @hw: pointer to hardware structure
|
||||
* @reg: analog register to read
|
||||
* @val: read value
|
||||
*
|
||||
* Performs write operation to analog register specified.
|
||||
**/
|
||||
s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
|
||||
{
|
||||
u32 atlas_ctl;
|
||||
|
||||
IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
|
||||
IXGBE_WRITE_FLUSH(hw);
|
||||
usec_delay(10);
|
||||
atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
|
||||
*val = (u8)atlas_ctl;
|
||||
|
||||
return IXGBE_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_write_analog_reg8_82598 - Writes 8 bit 82598 Atlas analog register
|
||||
* @hw: pointer to hardware structure
|
||||
* @reg: atlas register to write
|
||||
* @val: value to write
|
||||
*
|
||||
* Performs write operation to Atlas analog register specified.
|
||||
**/
|
||||
s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
|
||||
{
|
||||
u32 atlas_ctl;
|
||||
|
||||
atlas_ctl = (reg << 8) | val;
|
||||
IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
|
||||
IXGBE_WRITE_FLUSH(hw);
|
||||
usec_delay(10);
|
||||
|
||||
return IXGBE_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_get_num_rx_addrs_82598 - Get RX address registers
|
||||
* @hw: pointer to hardware structure
|
||||
|
||||
@ -32,6 +32,7 @@
|
||||
*******************************************************************************/
|
||||
/* $FreeBSD$ */
|
||||
|
||||
|
||||
#include "ixgbe_api.h"
|
||||
#include "ixgbe_common.h"
|
||||
|
||||
@ -52,7 +53,7 @@ extern s32 ixgbe_init_shared_code_phy(struct ixgbe_hw *hw);
|
||||
**/
|
||||
s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
|
||||
{
|
||||
s32 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
|
||||
s32 status;
|
||||
|
||||
/*
|
||||
* Assign generic function pointers before entering adapter-specific
|
||||
@ -60,25 +61,55 @@ s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
|
||||
*/
|
||||
ixgbe_assign_func_pointers_generic(hw);
|
||||
|
||||
if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) {
|
||||
switch (hw->device_id) {
|
||||
case IXGBE_DEV_ID_82598:
|
||||
case IXGBE_DEV_ID_82598_FPGA:
|
||||
case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
|
||||
case IXGBE_DEV_ID_82598AF_DUAL_PORT:
|
||||
case IXGBE_DEV_ID_82598AT_DUAL_PORT:
|
||||
status = ixgbe_init_shared_code_82598(hw);
|
||||
status = ixgbe_init_shared_code_phy(hw);
|
||||
break;
|
||||
default:
|
||||
status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
|
||||
break;
|
||||
}
|
||||
/*
|
||||
* Set the mac type
|
||||
*/
|
||||
ixgbe_set_mac_type(hw);
|
||||
|
||||
switch (hw->mac.type) {
|
||||
case ixgbe_mac_82598EB:
|
||||
status = ixgbe_init_shared_code_82598(hw);
|
||||
status = ixgbe_init_shared_code_phy(hw);
|
||||
break;
|
||||
default:
|
||||
status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
|
||||
break;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_set_mac_type - Sets MAC type
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* This function sets the mac type of the adapter based on the
|
||||
* vendor ID and device ID stored in the hw structure.
|
||||
**/
|
||||
s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
|
||||
{
|
||||
s32 ret_val = IXGBE_SUCCESS;
|
||||
|
||||
DEBUGFUNC("ixgbe_set_mac_type");
|
||||
|
||||
if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) {
|
||||
switch (hw->device_id) {
|
||||
case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
|
||||
case IXGBE_DEV_ID_82598AF_DUAL_PORT:
|
||||
case IXGBE_DEV_ID_82598EB_CX4:
|
||||
hw->mac.type = ixgbe_mac_82598EB;
|
||||
break;
|
||||
default:
|
||||
ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_init_hw - Initialize the hardware
|
||||
* @hw: pointer to hardware structure
|
||||
@ -643,3 +674,32 @@ s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
|
||||
IXGBE_NOT_IMPLEMENTED);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* ixgbe_read_analog_reg8 - Reads 8 bit analog register
|
||||
* @hw: pointer to hardware structure
|
||||
* @reg: analog register to read
|
||||
* @val: read value
|
||||
*
|
||||
* Performs write operation to analog register specified.
|
||||
**/
|
||||
s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
|
||||
{
|
||||
return ixgbe_call_func(hw, ixgbe_func_read_analog_reg8, (hw, reg, val),
|
||||
IXGBE_NOT_IMPLEMENTED);
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_write_analog_reg8 - Writes 8 bit analog register
|
||||
* @hw: pointer to hardware structure
|
||||
* @reg: analog register to write
|
||||
* @val: value to write
|
||||
*
|
||||
* Performs write operation to Atlas analog register specified.
|
||||
**/
|
||||
s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)
|
||||
{
|
||||
return ixgbe_call_func(hw, ixgbe_func_write_analog_reg8, (hw, reg, val),
|
||||
IXGBE_NOT_IMPLEMENTED);
|
||||
}
|
||||
|
||||
|
||||
@ -39,6 +39,7 @@
|
||||
|
||||
s32 ixgbe_init_shared_code(struct ixgbe_hw *hw);
|
||||
|
||||
s32 ixgbe_set_mac_type(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_init_hw(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_reset_hw(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_start_hw(struct ixgbe_hw *hw);
|
||||
@ -90,5 +91,7 @@ s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan,
|
||||
s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
|
||||
|
||||
void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr);
|
||||
s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);
|
||||
s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);
|
||||
|
||||
#endif /* _IXGBE_API_H_ */
|
||||
|
||||
@ -32,6 +32,7 @@
|
||||
*******************************************************************************/
|
||||
/* $FreeBSD$ */
|
||||
|
||||
|
||||
#include "ixgbe_common.h"
|
||||
#include "ixgbe_api.h"
|
||||
|
||||
@ -133,9 +134,6 @@ s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
|
||||
/* Clear statistics registers */
|
||||
ixgbe_clear_hw_cntrs(hw);
|
||||
|
||||
/* Set up flow control */
|
||||
ixgbe_setup_fc(hw, 0);
|
||||
|
||||
/* Set No Snoop Disable */
|
||||
ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
|
||||
ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
|
||||
|
||||
@ -87,7 +87,7 @@ typedef uint16_t u16;
|
||||
typedef uint32_t u32;
|
||||
typedef int32_t s32;
|
||||
typedef uint64_t u64;
|
||||
typedef booleant bool;
|
||||
typedef boolean_t bool;
|
||||
|
||||
#define le16_to_cpu
|
||||
|
||||
|
||||
@ -32,6 +32,7 @@
|
||||
*******************************************************************************/
|
||||
/* $FreeBSD$ */
|
||||
|
||||
|
||||
#include "ixgbe_api.h"
|
||||
#include "ixgbe_common.h"
|
||||
#include "ixgbe_phy.h"
|
||||
@ -66,24 +67,6 @@ s32 ixgbe_assign_func_pointers_phy(struct ixgbe_hw *hw)
|
||||
hw->func.ixgbe_func_identify_phy =
|
||||
&ixgbe_identify_phy_generic;
|
||||
|
||||
if (ixgbe_get_media_type(hw) == ixgbe_media_type_copper) {
|
||||
/* Call PHY identify routine to get the phy type */
|
||||
ixgbe_identify_phy(hw);
|
||||
|
||||
switch (hw->phy.type) {
|
||||
case ixgbe_phy_tn:
|
||||
hw->func.ixgbe_func_setup_phy_link =
|
||||
&ixgbe_setup_tnx_phy_link;
|
||||
hw->func.ixgbe_func_check_phy_link =
|
||||
&ixgbe_check_tnx_phy_link;
|
||||
hw->func.ixgbe_func_setup_phy_link_speed =
|
||||
&ixgbe_setup_tnx_phy_link_speed;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return IXGBE_SUCCESS;
|
||||
}
|
||||
|
||||
@ -171,14 +154,9 @@ enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
|
||||
enum ixgbe_phy_type phy_type;
|
||||
|
||||
switch (phy_id) {
|
||||
case TN1010_PHY_ID:
|
||||
phy_type = ixgbe_phy_tn;
|
||||
break;
|
||||
|
||||
case QT2022_PHY_ID:
|
||||
phy_type = ixgbe_phy_qt;
|
||||
break;
|
||||
|
||||
default:
|
||||
phy_type = ixgbe_phy_unknown;
|
||||
break;
|
||||
@ -213,7 +191,6 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
|
||||
{
|
||||
u32 command;
|
||||
u32 i;
|
||||
u32 timeout = 10;
|
||||
u32 data;
|
||||
s32 status = IXGBE_SUCCESS;
|
||||
u16 gssr;
|
||||
@ -240,7 +217,7 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
|
||||
* The MDI Command bit will clear when the operation is
|
||||
* complete
|
||||
*/
|
||||
for (i = 0; i < timeout; i++) {
|
||||
for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
|
||||
usec_delay(10);
|
||||
|
||||
command = IXGBE_READ_REG(hw, IXGBE_MSCA);
|
||||
@ -251,7 +228,7 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
|
||||
}
|
||||
|
||||
if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
|
||||
DEBUGFUNC("PHY address command did not complete.\n");
|
||||
DEBUGOUT("PHY address command did not complete.\n");
|
||||
status = IXGBE_ERR_PHY;
|
||||
}
|
||||
|
||||
@ -272,7 +249,7 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
|
||||
* completed. The MDI Command bit will clear when the
|
||||
* operation is complete
|
||||
*/
|
||||
for (i = 0; i < timeout; i++) {
|
||||
for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
|
||||
usec_delay(10);
|
||||
|
||||
command = IXGBE_READ_REG(hw, IXGBE_MSCA);
|
||||
@ -282,7 +259,7 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
|
||||
}
|
||||
|
||||
if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
|
||||
DEBUGFUNC("PHY read command didn't complete\n");
|
||||
DEBUGOUT("PHY read command didn't complete\n");
|
||||
status = IXGBE_ERR_PHY;
|
||||
} else {
|
||||
/*
|
||||
@ -312,7 +289,6 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
|
||||
{
|
||||
u32 command;
|
||||
u32 i;
|
||||
u32 timeout = 10;
|
||||
s32 status = IXGBE_SUCCESS;
|
||||
u16 gssr;
|
||||
|
||||
@ -341,7 +317,7 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
|
||||
* The MDI Command bit will clear when the operation is
|
||||
* complete
|
||||
*/
|
||||
for (i = 0; i < timeout; i++) {
|
||||
for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
|
||||
usec_delay(10);
|
||||
|
||||
command = IXGBE_READ_REG(hw, IXGBE_MSCA);
|
||||
@ -372,7 +348,7 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
|
||||
* completed. The MDI Command bit will clear when the
|
||||
* operation is complete
|
||||
*/
|
||||
for (i = 0; i < timeout; i++) {
|
||||
for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
|
||||
usec_delay(10);
|
||||
|
||||
command = IXGBE_READ_REG(hw, IXGBE_MSCA);
|
||||
@ -437,156 +413,3 @@ s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
|
||||
IXGBE_NOT_IMPLEMENTED);
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_setup_tnx_phy_link - Set and restart autoneg
|
||||
* @hw: pointer to hardware structure
|
||||
*
|
||||
* Restart autonegotiation and PHY and waits for completion.
|
||||
**/
|
||||
s32 ixgbe_setup_tnx_phy_link(struct ixgbe_hw *hw)
|
||||
{
|
||||
s32 status = IXGBE_NOT_IMPLEMENTED;
|
||||
u32 time_out;
|
||||
u32 max_time_out = 10;
|
||||
u16 autoneg_speed_selection_register = 0x10;
|
||||
u16 autoneg_restart_mask = 0x0200;
|
||||
u16 autoneg_complete_mask = 0x0020;
|
||||
u16 autoneg_reg = 0;
|
||||
|
||||
/*
|
||||
* Set advertisement settings in PHY based on autoneg_advertised
|
||||
* settings. If autoneg_advertised = 0, then advertise default values
|
||||
* txn devices cannot be "forced" to a autoneg 10G and fail. But can
|
||||
* for a 1G.
|
||||
*/
|
||||
ixgbe_read_phy_reg(hw,
|
||||
autoneg_speed_selection_register,
|
||||
IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
|
||||
&autoneg_reg);
|
||||
|
||||
if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
|
||||
autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */
|
||||
else
|
||||
autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */
|
||||
|
||||
ixgbe_write_phy_reg(hw,
|
||||
autoneg_speed_selection_register,
|
||||
IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
|
||||
autoneg_reg);
|
||||
|
||||
|
||||
/* Restart PHY autonegotiation and wait for completion */
|
||||
ixgbe_read_phy_reg(hw,
|
||||
IXGBE_MDIO_AUTO_NEG_CONTROL,
|
||||
IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
|
||||
&autoneg_reg);
|
||||
|
||||
autoneg_reg |= autoneg_restart_mask;
|
||||
|
||||
ixgbe_write_phy_reg(hw,
|
||||
IXGBE_MDIO_AUTO_NEG_CONTROL,
|
||||
IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
|
||||
autoneg_reg);
|
||||
|
||||
/* Wait for autonegotiation to finish */
|
||||
for (time_out = 0; time_out < max_time_out; time_out++) {
|
||||
usec_delay(10);
|
||||
/* Restart PHY autonegotiation and wait for completion */
|
||||
status = ixgbe_read_phy_reg(hw,
|
||||
IXGBE_MDIO_AUTO_NEG_STATUS,
|
||||
IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
|
||||
&autoneg_reg);
|
||||
|
||||
autoneg_reg &= autoneg_complete_mask;
|
||||
if (autoneg_reg == autoneg_complete_mask) {
|
||||
status = IXGBE_SUCCESS;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (time_out == max_time_out)
|
||||
status = IXGBE_ERR_LINK_SETUP;
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_check_tnx_phy_link - Determine link and speed status
|
||||
* @hw: pointer to hardware structure
|
||||
*
|
||||
* Reads the VS1 register to determine if link is up and the current speed for
|
||||
* the PHY.
|
||||
**/
|
||||
s32 ixgbe_check_tnx_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
|
||||
bool *link_up)
|
||||
{
|
||||
s32 status = IXGBE_SUCCESS;
|
||||
u32 time_out;
|
||||
u32 max_time_out = 10;
|
||||
u16 phy_link = 0;
|
||||
u16 phy_speed = 0;
|
||||
u16 phy_data = 0;
|
||||
|
||||
/* Initialize speed and link to default case */
|
||||
*link_up = FALSE;
|
||||
*speed = IXGBE_LINK_SPEED_10GB_FULL;
|
||||
|
||||
/*
|
||||
* Check current speed and link status of the PHY register.
|
||||
* This is a vendor specific register and may have to
|
||||
* be changed for other copper PHYs.
|
||||
*/
|
||||
for (time_out = 0; time_out < max_time_out; time_out++) {
|
||||
usec_delay(10);
|
||||
if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
|
||||
*link_up = TRUE;
|
||||
if (phy_speed ==
|
||||
IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
|
||||
*speed = IXGBE_LINK_SPEED_1GB_FULL;
|
||||
break;
|
||||
} else {
|
||||
status = ixgbe_read_phy_reg(hw,
|
||||
IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
|
||||
IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
|
||||
&phy_data);
|
||||
phy_link = phy_data &
|
||||
IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
|
||||
phy_speed = phy_data &
|
||||
IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_setup_tnx_phy_link_speed - Sets the auto advertised capabilities
|
||||
* @hw: pointer to hardware structure
|
||||
* @speed: new link speed
|
||||
* @autoneg: TRUE if autonegotiation enabled
|
||||
**/
|
||||
s32 ixgbe_setup_tnx_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
|
||||
bool autoneg,
|
||||
bool autoneg_wait_to_complete)
|
||||
{
|
||||
UNREFERENCED_PARAMETER(autoneg);
|
||||
UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
|
||||
|
||||
/*
|
||||
* Clear autoneg_advertised and set new values based on input link
|
||||
* speed.
|
||||
*/
|
||||
hw->phy.autoneg_advertised = 0;
|
||||
|
||||
if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
|
||||
hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
|
||||
}
|
||||
if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
|
||||
hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
|
||||
}
|
||||
|
||||
/* Setup link based on the new speed settings */
|
||||
ixgbe_setup_tnx_phy_link(hw);
|
||||
|
||||
return IXGBE_SUCCESS;
|
||||
}
|
||||
|
||||
@ -57,14 +57,4 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
|
||||
s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
|
||||
u32 device_type, u16 phy_data);
|
||||
|
||||
/* PHY specific */
|
||||
s32 ixgbe_setup_tnx_phy_link(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_check_tnx_phy_link(struct ixgbe_hw *hw,
|
||||
ixgbe_link_speed *speed,
|
||||
bool *link_up);
|
||||
s32 ixgbe_setup_tnx_phy_link_speed(struct ixgbe_hw *hw,
|
||||
ixgbe_link_speed speed,
|
||||
bool autoneg,
|
||||
bool autoneg_wait_to_complete);
|
||||
|
||||
#endif /* _IXGBE_PHY_H_ */
|
||||
|
||||
@ -41,11 +41,9 @@
|
||||
#define IXGBE_INTEL_VENDOR_ID 0x8086
|
||||
|
||||
/* Device IDs */
|
||||
#define IXGBE_DEV_ID_82598 0x10B6
|
||||
#define IXGBE_DEV_ID_82598_FPGA 0xF0C0
|
||||
#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
|
||||
#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
|
||||
#define IXGBE_DEV_ID_82598AT_DUAL_PORT 0x10C8
|
||||
#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
|
||||
|
||||
/* General Registers */
|
||||
#define IXGBE_CTRL 0x00000
|
||||
@ -280,23 +278,17 @@
|
||||
#define IXGBE_DCA_CTRL 0x11074
|
||||
|
||||
/* Diagnostic Registers */
|
||||
#define IXGBE_RDSTATCTL 0x02C20
|
||||
#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
|
||||
#define IXGBE_RDHMPN 0x02F08
|
||||
#define IXGBE_RIC_DW0 0x02F10
|
||||
#define IXGBE_RIC_DW1 0x02F14
|
||||
#define IXGBE_RIC_DW2 0x02F18
|
||||
#define IXGBE_RIC_DW3 0x02F1C
|
||||
#define IXGBE_RDPROBE 0x02F20
|
||||
#define IXGBE_TDSTATCTL 0x07C20
|
||||
#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
|
||||
#define IXGBE_TDHMPN 0x07F08
|
||||
#define IXGBE_TIC_DW0 0x07F10
|
||||
#define IXGBE_TIC_DW1 0x07F14
|
||||
#define IXGBE_TIC_DW2 0x07F18
|
||||
#define IXGBE_TIC_DW3 0x07F1C
|
||||
#define IXGBE_TDPROBE 0x07F20
|
||||
#define IXGBE_TXBUFCTRL 0x0C600
|
||||
#define IXGBE_RDSTATCTL 0x02C20
|
||||
#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
|
||||
#define IXGBE_RDHMPN 0x02F08
|
||||
#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
|
||||
#define IXGBE_RDPROBE 0x02F20
|
||||
#define IXGBE_TDSTATCTL 0x07C20
|
||||
#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
|
||||
#define IXGBE_TDHMPN 0x07F08
|
||||
#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
|
||||
#define IXGBE_TDPROBE 0x07F20
|
||||
#define IXGBE_TXBUFCTRL 0x0C600
|
||||
#define IXGBE_TXBUFDATA0 0x0C610
|
||||
#define IXGBE_TXBUFDATA1 0x0C614
|
||||
#define IXGBE_TXBUFDATA2 0x0C618
|
||||
@ -393,6 +385,8 @@
|
||||
|
||||
#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
|
||||
#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
|
||||
#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* TX Desc writeback RO bit */
|
||||
#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
|
||||
|
||||
/* MSCA Bit Masks */
|
||||
#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */
|
||||
@ -415,10 +409,23 @@
|
||||
#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */
|
||||
|
||||
/* MSRWD bit masks */
|
||||
#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
|
||||
#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
|
||||
#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
|
||||
#define IXGBE_MSRWD_READ_DATA_SHIFT 16
|
||||
#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
|
||||
#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
|
||||
#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
|
||||
#define IXGBE_MSRWD_READ_DATA_SHIFT 16
|
||||
|
||||
/* Atlas registers */
|
||||
#define IXGBE_ATLAS_PDN_LPBK 0x24
|
||||
#define IXGBE_ATLAS_PDN_10G 0xB
|
||||
#define IXGBE_ATLAS_PDN_1G 0xC
|
||||
#define IXGBE_ATLAS_PDN_AN 0xD
|
||||
|
||||
/* Atlas bit masks */
|
||||
#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
|
||||
#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
|
||||
#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
|
||||
#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
|
||||
#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
|
||||
|
||||
/* Device Type definitions for new protocol MDIO commands */
|
||||
#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
|
||||
@ -427,6 +434,8 @@
|
||||
#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
|
||||
#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
|
||||
|
||||
#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
|
||||
|
||||
#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */
|
||||
#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
|
||||
#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
|
||||
@ -448,7 +457,6 @@
|
||||
#define IXGBE_MAX_PHY_ADDR 32
|
||||
|
||||
/* PHY IDs*/
|
||||
#define TN1010_PHY_ID 0x00A19410
|
||||
#define QT2022_PHY_ID 0x0043A400
|
||||
|
||||
/* General purpose Interrupt Enable */
|
||||
@ -689,7 +697,29 @@
|
||||
#define IXGBE_LINKS_TL_FAULT 0x00001000
|
||||
#define IXGBE_LINKS_SIGNAL 0x00000F00
|
||||
|
||||
#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
|
||||
#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
|
||||
|
||||
#define FIBER_LINK_UP_LIMIT 50
|
||||
|
||||
/* PCS1GLSTA Bit Masks */
|
||||
#define IXGBE_PCS1GLSTA_LINK_OK 1
|
||||
#define IXGBE_PCS1GLSTA_SYNK_OK 0x10
|
||||
#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000
|
||||
#define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000
|
||||
#define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000
|
||||
#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
|
||||
#define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000
|
||||
|
||||
#define IXGBE_PCS1GANA_SYM_PAUSE 0x80
|
||||
#define IXGBE_PCS1GANA_ASM_PAUSE 0x100
|
||||
|
||||
/* PCS1GLCTL Bit Masks */
|
||||
#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg timeout enable (bit 18) */
|
||||
#define IXGBE_PCS1GLCTL_FLV_LINK_UP 1
|
||||
#define IXGBE_PCS1GLCTL_FORCE_LINK 0x20
|
||||
#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40
|
||||
#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
|
||||
#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
|
||||
|
||||
/* SW Semaphore Register bitmasks */
|
||||
#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
|
||||
@ -741,6 +771,11 @@
|
||||
#define IXGBE_CSR1_CONFIG_PTR 0x0E
|
||||
#define IXGBE_FW_PTR 0x0F
|
||||
|
||||
/* Legacy EEPROM word offsets */
|
||||
#define IXGBE_ISCSI_BOOT_CAPS 0x0033
|
||||
#define IXGBE_ISCSI_SETUP_PORT_0 0x0030
|
||||
#define IXGBE_ISCSI_SETUP_PORT_1 0x0034
|
||||
|
||||
/* EEPROM Commands - SPI */
|
||||
#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */
|
||||
#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
|
||||
@ -783,6 +818,8 @@
|
||||
#define IXGBE_PCI_LINK_SPEED 0xF
|
||||
#define IXGBE_PCI_LINK_SPEED_2500 0x1
|
||||
#define IXGBE_PCI_LINK_SPEED_5000 0x2
|
||||
#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
|
||||
#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
|
||||
|
||||
/* Number of 100 microseconds we wait for PCI Express master disable */
|
||||
#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
|
||||
@ -911,14 +948,15 @@
|
||||
#define IXGBE_RXD_CFI_SHIFT 12
|
||||
|
||||
/* SRRCTL bit definitions */
|
||||
#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
|
||||
#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
|
||||
#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
|
||||
#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
|
||||
#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
|
||||
#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
|
||||
#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
|
||||
#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
|
||||
#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
|
||||
#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
|
||||
#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
|
||||
#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
|
||||
#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
|
||||
|
||||
#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
|
||||
#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
|
||||
@ -1107,6 +1145,7 @@ typedef u32 ixgbe_autoneg_advertised;
|
||||
/* Link speed */
|
||||
typedef u32 ixgbe_link_speed;
|
||||
#define IXGBE_LINK_SPEED_UNKNOWN 0
|
||||
#define IXGBE_LINK_SPEED_100_FULL 0x0008
|
||||
#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
|
||||
#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
|
||||
|
||||
@ -1125,7 +1164,6 @@ enum ixgbe_mac_type {
|
||||
|
||||
enum ixgbe_phy_type {
|
||||
ixgbe_phy_unknown = 0,
|
||||
ixgbe_phy_tn,
|
||||
ixgbe_phy_qt,
|
||||
ixgbe_phy_xaui
|
||||
};
|
||||
@ -1287,8 +1325,8 @@ struct ixgbe_functions
|
||||
u32 (*ixgbe_func_get_num_of_rx_queues)(struct ixgbe_hw *);
|
||||
s32 (*ixgbe_func_stop_adapter)(struct ixgbe_hw *);
|
||||
s32 (*ixgbe_func_get_bus_info)(struct ixgbe_hw *);
|
||||
|
||||
|
||||
s32 (*ixgbe_func_read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
|
||||
s32 (*ixgbe_func_write_analog_reg8)(struct ixgbe_hw*, u32, u8);
|
||||
/* PHY */
|
||||
s32 (*ixgbe_func_identify_phy)(struct ixgbe_hw *);
|
||||
s32 (*ixgbe_func_reset_phy)(struct ixgbe_hw *);
|
||||
@ -1347,6 +1385,8 @@ struct ixgbe_mac_info {
|
||||
u32 link_attach_type;
|
||||
u32 link_mode_select;
|
||||
bool link_settings_loaded;
|
||||
bool autoneg;
|
||||
bool autoneg_failed;
|
||||
};
|
||||
|
||||
struct ixgbe_phy_info {
|
||||
|
||||
15
sys/modules/ixgbe/Makefile
Normal file
15
sys/modules/ixgbe/Makefile
Normal file
@ -0,0 +1,15 @@
|
||||
#$FreeBSD$
|
||||
.PATH: ${.CURDIR}/../../dev/ixgbe
|
||||
KMOD = ixgbe
|
||||
SRCS = device_if.h bus_if.h pci_if.h opt_bdg.h
|
||||
SRCS += ixgbe.c
|
||||
# Shared source
|
||||
SRCS += ixgbe_common.c ixgbe_api.c ixgbe_phy.c ixgbe_82598.c
|
||||
CFLAGS+= -I${.CURDIR}/../../dev/ixgbe
|
||||
|
||||
clean:
|
||||
rm -f opt_bdg.h device_if.h bus_if.h pci_if.h setdef* *_StripErr
|
||||
rm -f *.o *.kld *.ko
|
||||
rm -f @ machine
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
Loading…
Reference in New Issue
Block a user