On i386, make "prescott" an alias for "nocona" (instead of the other way
around), and introduce "core", along with the alias "core2". All of these enable SSE3. On amd64, add "core2" (enables SSE3). MFC after: 3 weeks
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=166069
@ -32,11 +32,12 @@
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# Intel x86 architecture:
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# (AMD CPUs) opteron athlon64 athlon-mp athlon-xp athlon-4
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# athlon-tbird athlon k8 k6-3 k6-2 k6 k5
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# (Intel CPUs) nocona pentium4[m] prescott pentium3[m] pentium-m
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# pentium2 pentiumpro pentium-mmx pentium i486 i386
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# (Intel CPUs) core2 core nocona pentium4m pentium4 prescott
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# pentium3m pentium3 pentium-m pentium2
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# pentiumpro pentium-mmx pentium i486 i386
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# (Via CPUs) c3 c3-2
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# Alpha/AXP architecture: ev67 ev6 pca56 ev56 ev5 ev45 ev4
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# AMD64 architecture: opteron, athlon64, nocona
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# AMD64 architecture: opteron, athlon64, nocona, prescott, core2
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# Intel ia64 architecture: itanium2, itanium
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#
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# (?= allows to buildworld for a different CPUTYPE.)
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@ -22,8 +22,10 @@ MACHINE_CPU = arm
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# between e.g. i586 and pentium)
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. if ${MACHINE_ARCH} == "i386"
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. if ${CPUTYPE} == "nocona"
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CPUTYPE = prescott
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. if ${CPUTYPE} == "prescott"
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CPUTYPE = nocona
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. elif ${CPUTYPE} == "core2"
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CPUTYPE = core
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. elif ${CPUTYPE} == "p4"
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CPUTYPE = pentium4
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. elif ${CPUTYPE} == "p4m"
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@ -131,6 +133,8 @@ MACHINE_CPU = k5 i586 i486 i386
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MACHINE_CPU = 3dnow mmx i586 i486 i386
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. elif ${CPUTYPE} == "c3-2"
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MACHINE_CPU = sse mmx i586 i486 i386
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. elif ${CPUTYPE} == "nocona" || ${CPUTYPE} == "core"
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MACHINE_CPU = sse3 sse2 sse i686 mmx i586 i486 i386
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. elif ${CPUTYPE} == "pentium4" || ${CPUTYPE} == "pentium4m" || ${CPUTYPE} == "pentium-m"
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MACHINE_CPU = sse2 sse i686 mmx i586 i486 i386
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. elif ${CPUTYPE} == "pentium3" || ${CPUTYPE} == "pentium3m"
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@ -151,7 +155,7 @@ MACHINE_CPU = i386
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. elif ${MACHINE_ARCH} == "amd64"
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. if ${CPUTYPE} == "opteron" || ${CPUTYPE} == "athlon64" || ${CPUTYPE} == "k8"
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MACHINE_CPU = k8 3dnow
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. elif ${CPUTYPE} == "nocona"
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. elif ${CPUTYPE} == "nocona" || ${CPUTYPE} == "core2"
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MACHINE_CPU = sse3
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. endif
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MACHINE_CPU += amd64 sse2 sse mmx
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