o Add device tree files and kernel configuration files

for RISC-V cpus synthesized on FPGA hardware.
o Include new files to the build.

sys/boot/fdt/dts/riscv/lowrisc.dts

@@ -0,0 +1,108 @@
+/*-
+ * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
+ * All rights reserved.
+ *
+ * Portions of this software were developed by SRI International and the
+ * University of Cambridge Computer Laboratory under DARPA/AFRL contract
+ * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
+ *
+ * Portions of this software were developed by the University of Cambridge
+ * Computer Laboratory as part of the CTSRD Project, with support from the
+ * UK Higher Education Innovation Fund (HEIF).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+
+/ {
+	model = "UC Berkeley Spike Simulator RV64I";
+	compatible = "riscv,rv64i";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	#interrupt-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "riscv,rv64i";
+			reg = <0x40002000>;
+		};
+	};
+
+	aliases {
+		serial0 = &serial0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x8000000>; /* 128MB at 0x0 */
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		#interrupt-cells = <1>;
+
+		compatible = "simple-bus";
+		ranges;
+
+		pic0: pic@0 {
+			compatible = "riscv,pic";
+			interrupt-controller;
+		};
+
+		serial0: serial@80001000 {
+			compatible = "ns16550";
+			reg = <0x80001000 0x1000>;
+			reg-shift = <2>;
+			interrupts = < 4 >;
+			interrupt-parent = <&pic0>;
+			current-speed = <115200>;
+			clock-frequency = < 1000000 >;
+			status = "okay";
+		};
+
+		spi0: spi@80010000 {
+			compatible = "xlnx,xps-spi-3.2";
+			reg = <0x80010000 0x1000>;
+		};
+
+		timer0: timer@0 {
+			compatible = "riscv,timer";
+			interrupts = < 1 >;
+			interrupt-parent = < &pic0 >;
+			clock-frequency = < 1000000 >;
+		};
+	};
+
+	chosen {
+		bootargs = "-v";
+		stdin = "serial0";
+		stdout = "serial0";
+	};
+};

sys/boot/fdt/dts/riscv/rocket.dts

@@ -0,0 +1,103 @@
+/*-
+ * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
+ * All rights reserved.
+ *
+ * Portions of this software were developed by SRI International and the
+ * University of Cambridge Computer Laboratory under DARPA/AFRL contract
+ * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
+ *
+ * Portions of this software were developed by the University of Cambridge
+ * Computer Laboratory as part of the CTSRD Project, with support from the
+ * UK Higher Education Innovation Fund (HEIF).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+
+/ {
+	model = "UC Berkeley Spike Simulator RV64I";
+	compatible = "riscv,rv64i";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	#interrupt-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "riscv,rv64i";
+			reg = <0x40002000>;
+		};
+	};
+
+	aliases {
+		console0 = &console0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x10000000>; /* 256MB at 0x0 */
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+
+		compatible = "simple-bus";
+		ranges;
+
+		pic0: pic@0 {
+			compatible = "riscv,pic";
+			interrupt-controller;
+		};
+
+		timer0: timer@0 {
+			compatible = "riscv,timer";
+			interrupts = < 1 >;
+			interrupt-parent = < &pic0 >;
+			clock-frequency = < 1000000 >;
+		};
+
+		htif0: htif@0 {
+			compatible = "riscv,htif";
+			interrupts = < 0 >;
+			interrupt-parent = < &pic0 >;
+
+			console0: console@0 {
+				compatible = "htif,console";
+				status = "okay";
+			};
+		};
+	};
+
+	chosen {
+		bootargs = "-v";
+		stdin = "console0";
+		stdout = "console0";
+	};
+};

sys/conf/files.riscv

@@ -2,6 +2,8 @@
 crypto/blowfish/bf_enc.c	optional	crypto | ipsec
 crypto/des/des_enc.c		optional	crypto | ipsec | netsmb
 dev/ofw/ofw_cpu.c		optional	fdt
+dev/uart/uart_cpu_fdt.c		optional	uart fdt
+dev/xilinx/axi_quad_spi.c	optional	xilinx_spi
 kern/kern_clocksource.c		standard
 kern/subr_devmap.c		standard
 kern/subr_dummy_vdso_tc.c	standard
@@ -13,12 +15,13 @@ libkern/flsl.c			standard
 libkern/flsll.c			standard
 libkern/memmove.c		standard
 libkern/memset.c		standard
-riscv/htif/htif.c		standard
-riscv/htif/htif_block.c		standard
-riscv/htif/htif_console.c	standard
+riscv/htif/htif.c		optional	htif
+riscv/htif/htif_block.c		optional	htif
+riscv/htif/htif_console.c	optional	htif
 riscv/riscv/autoconf.c		standard
 riscv/riscv/bcopy.c		standard
 riscv/riscv/bus_machdep.c	standard
+riscv/riscv/bus_space_asm.S	standard
 riscv/riscv/busdma_machdep.c	standard
 riscv/riscv/clock.c		standard
 riscv/riscv/copyinout.S		standard
@@ -38,6 +41,7 @@ riscv/riscv/minidump_machdep.c	standard
 riscv/riscv/mp_machdep.c	optional	smp
 riscv/riscv/mem.c		standard
 riscv/riscv/nexus.c		standard
+riscv/riscv/ofw_machdep.c	optional	fdt
 riscv/riscv/pmap.c		standard
 riscv/riscv/stack_machdep.c	optional	ddb | stack
 riscv/riscv/support.S		standard

sys/riscv/conf/GENERIC

@@ -90,8 +90,6 @@ options 	INVARIANT_SUPPORT	# Extra sanity checks of internal structures, require
 # options 	WITNESS			# Enable checks to detect deadlocks and cycles
 # options 	WITNESS_SKIPSPIN	# Don't run witness on spinlocks for speed
 options 	MALLOC_DEBUG_MAXZONES=8	# Separate malloc(9) zones
-
-options 	ROOTDEVNAME=\"ufs:/dev/htif_blk0\"
 # options 	EARLY_PRINTF
 
 # Pseudo devices.

sys/riscv/conf/LOWRISC

@@ -0,0 +1,43 @@
+#
+# Kernel configuration file for lowRISC.
+#
+# For more information on this file, please read the config(5) manual page,
+# and/or the handbook section on Kernel Configuration Files:
+#
+#    http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD$
+
+include		GENERIC
+ident		LOWRISC
+
+hints		"LOWRISC.hints"
+
+options		ROOTDEVNAME=\"ufs:mmcsd0s2\"
+
+# MMC/SD
+device		mmc
+device		mmcsd
+# device	mmc_spi
+
+# SPI
+device		spibus
+device		xilinx_spi
+
+# Serial (COM) ports
+device		uart		# Generic UART driver
+device		uart_ns8250	# ns8250-type UART driver
+
+# RISCVTODO: This needs to be done via loader (when it's available).
+options 	FDT_DTB_STATIC
+makeoptions	FDT_DTS_FILE=lowrisc.dts

sys/riscv/conf/LOWRISC.hints

@@ -0,0 +1,5 @@
+# $FreeBSD$
+
+# MMC device
+hint.mmc_spi.0.at="spibus0"
+hint.mmc_spi.0.cs=0

sys/riscv/conf/QEMU

@@ -21,6 +21,9 @@
 include		GENERIC
 ident		QEMU
 
+device		htif
+options 	ROOTDEVNAME=\"ufs:/dev/htif_blk0\"
+
 # RISCVTODO: This needs to be done via loader (when it's available).
 options 	FDT_DTB_STATIC
 makeoptions	FDT_DTS_FILE=qemu.dts

sys/riscv/conf/ROCKET

@@ -0,0 +1,29 @@
+#
+# Kernel configuration file for Rocket Core.
+#
+# For more information on this file, please read the config(5) manual page,
+# and/or the handbook section on Kernel Configuration Files:
+#
+#    http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD$
+
+include		GENERIC
+ident		ROCKET
+
+device		htif
+options 	ROOTDEVNAME=\"ufs:/dev/htif_blk0\"
+
+# RISCVTODO: This needs to be done via loader (when it's available).
+options 	FDT_DTB_STATIC
+makeoptions	FDT_DTS_FILE=rocket.dts

sys/riscv/conf/SPIKE

@@ -21,6 +21,9 @@
 include		GENERIC
 ident		SPIKE
 
+device		htif
+options 	ROOTDEVNAME=\"ufs:/dev/htif_blk0\"
+
 # RISCVTODO: This needs to be done via loader (when it's available).
 options 	FDT_DTB_STATIC
 makeoptions	FDT_DTS_FILE=spike.dts